From nobody Mon Apr 6 09:09:46 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B97E31714C; Fri, 20 Mar 2026 05:46:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773985611; cv=none; b=i+eIvVINzpWAKjeR8ilb5/kj4AQPgKth0ch+Xox2gT1yJAxGVZWak8OETUCbzYnhv/dF2gAsUTJA6BQN4ZtAKOMxCJQRcjVr+gH+o4/NcpVB6URu5x9DpOlEmclEDjDjcbsbWsZIllfG+/CewCwB5ibvYN0dduTtkqoAtxIXXhI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773985611; c=relaxed/simple; bh=U9UIMT5MY4p71koRPdELGX4IvlmgyoiNubG0RreHjtA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Diimuab1QrnvHuk1yc7qBBBi1n5Ve9pfJslFAz5PMjmkY1EWxDbPJJ7ZJluYawfZcHrj9eYTzn3hLOuRrsMcPxbOtMBel5wnORZuZ186llW/1Tlv6uv9A9KVX+++u1wS82+ivN9c6wLg4m10Xt+C9Zxc0bx4GIvF1HF89tsNq8g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 20 Mar 2026 13:46:40 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 20 Mar 2026 13:46:40 +0800 From: Billy Tsai Date: Fri, 20 Mar 2026 13:46:35 +0800 Subject: [PATCH v3 1/4] iio: adc: Add battery channel definition for ADC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-adc-v3-1-bc0eac04ef7c@aspeedtech.com> References: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> In-Reply-To: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773985600; l=1633; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=U9UIMT5MY4p71koRPdELGX4IvlmgyoiNubG0RreHjtA=; b=S/vv1jCj2l2SomhOwzSgeS124qs/Mb7r4uTu4QaXqK1A6yYlgQ1LI3SXtTfiJ5WYfKrz7Z0l/ V16DTdvnu9jCcTaHZkL6Un1lFxrfbhpb+vOPUkGMskBrk3oABIQkZOC X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Defines a constant for the battery sensing channel, typically the last channel of the ADC. Clarifies channel usage and improves code readability. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 4be44c524b4d..8eebaa3dc534 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -75,6 +75,8 @@ =20 #define ASPEED_ADC_INIT_POLLING_TIME 500 #define ASPEED_ADC_INIT_TIMEOUT 500000 +/* Battery sensing is typically on the last channel */ +#define ASPEED_ADC_BATTERY_CHANNEL 7 /* * When the sampling rate is too high, the ADC may not have enough charging * time, resulting in a low voltage value. Thus, the default uses a slow @@ -285,7 +287,7 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_de= v, =20 switch (mask) { case IIO_CHAN_INFO_RAW: - if (data->battery_sensing && chan->channel =3D=3D 7) { + if (data->battery_sensing && chan->channel =3D=3D ASPEED_ADC_BATTERY_CHA= NNEL) { adc_engine_control_reg_val =3D readl(data->base + ASPEED_REG_ENGINE_CONTROL); writel(adc_engine_control_reg_val | @@ -309,7 +311,7 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_de= v, return IIO_VAL_INT; =20 case IIO_CHAN_INFO_OFFSET: - if (data->battery_sensing && chan->channel =3D=3D 7) + if (data->battery_sensing && chan->channel =3D=3D ASPEED_ADC_BATTERY_CHA= NNEL) *val =3D (data->cv * data->battery_mode_gain.mult) / data->battery_mode_gain.div; else --=20 2.34.1 From nobody Mon Apr 6 09:09:46 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D35A3195FB; Fri, 20 Mar 2026 05:46:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773985613; cv=none; b=T0jjoxf5Y65iFOVeEymx7Jq/H3gjbZKl4OFjUcYE0tIamutCbVWgEiUjSpFm0h2Dgt2toUD6RyyAoT7Z2pBtS3AqpeIYXX4Br8gbtuKcXYmOLyQ0Ix7e0feh/ljDBgn2OGUM2ntIQ69aisnY0YOfYVrL6PIaqHAAjkDm1E4XRgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773985613; c=relaxed/simple; bh=NmmhJK7uvUVre1uvvr5Vjz5lKqP/DkupFhrPhytp+BM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=qZCW/y0io2H5xfQQ6JYNnV1/iwTZgSYtg0+P8/LQhMCtYrZ2wfk0UUAZ3RHJg7mJFnBHBH0tSjoLmH/RwZ3P4KZDexVYnzuFObcniMTwVVTK70sZD7yWbhx5Pm//T6iVY4kLxSdSuGNkjSV/z10RkyZPUNsU1S4qA3IZU86ViIg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 20 Mar 2026 13:46:40 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 20 Mar 2026 13:46:40 +0800 From: Billy Tsai Date: Fri, 20 Mar 2026 13:46:36 +0800 Subject: [PATCH v3 2/4] iio: adc: Enable multiple consecutive channels based on model data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-adc-v3-2-bc0eac04ef7c@aspeedtech.com> References: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> In-Reply-To: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773985600; l=1731; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=NmmhJK7uvUVre1uvvr5Vjz5lKqP/DkupFhrPhytp+BM=; b=gjpKlIm9OA6WHPNLApb+1XgFzo7WUdGq9UT4iOA2UGLsak9TbZYPWpTilmInbAtps5oQztHh0 5xUT1/v5ZAlDgV06+pcVwoPjla6BPWGia5EpXe9BoSVfqmeYFm13uVZ X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Add helpers to generate channel masks and enable multiple ADC channels according to the device model's channel count. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 8eebaa3dc534..3ff24474f394 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -123,6 +123,24 @@ struct aspeed_adc_data { struct adc_gain battery_mode_gain; }; =20 +/* + * Enable multiple consecutive channels starting from channel 0. + * This creates a bitmask for channels 0 to (num_channels - 1). + * For example: num_channels=3D3 creates mask 0x0007 (channels 0,1,2) + */ +static inline u32 aspeed_adc_channels_mask(unsigned int num_channels) +{ + if (num_channels > 16) + return GENMASK(15, 0); + + return BIT(num_channels) - 1; +} + +static inline unsigned int aspeed_adc_get_active_channels(const struct asp= eed_adc_data *data) +{ + return data->model_data->num_channels; +} + #define ASPEED_CHAN(_idx, _data_reg_addr) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -612,7 +630,9 @@ static int aspeed_adc_probe(struct platform_device *pde= v) /* Start all channels in normal mode. */ adc_engine_control_reg_val =3D readl(data->base + ASPEED_REG_ENGINE_CONTROL); - adc_engine_control_reg_val |=3D ASPEED_ADC_CTRL_CHANNEL; + FIELD_MODIFY(ASPEED_ADC_CTRL_CHANNEL, &adc_engine_control_reg_val, + aspeed_adc_channels_mask(aspeed_adc_get_active_channels(data))); + writel(adc_engine_control_reg_val, data->base + ASPEED_REG_ENGINE_CONTROL); =20 --=20 2.34.1 From nobody Mon Apr 6 09:09:46 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E476931715F; Fri, 20 Mar 2026 05:46:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773985615; cv=none; b=RhlA/gmQQjIUDlgvSf5d5xZ06sUkL2FVgr866Igi6pPrVlt1kyVzlmRC04RYEDz1jlXdXybu3Ic08lalaYoGGXHmI+drq60JzFRnZVlB6zZNJFFMgKt9YxJyAVNIKu9oXgfr1qHIlTnY5hsqcEZMKebtwmRjsgni7GQP5Baz+vw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773985615; c=relaxed/simple; bh=nns6L1IWBrZoZF9du3xsZHyx3aa79UG/Vd6Iwrl6+E4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=WMrg+TyuViQqX4Gk7uuDgHVq9yKCM8L0y4QQ329/ra4Gr0hMplV8Z4cqsqbwdT1WKKP2aFeWB9Kbp+EPzNuURqhFBHn7s7bEYbvY2z1p0pN7Hp/0X0XiGb/mAxZrKl/HczMALGZlSmjuJn4c1IEzJxV3cPQkULBokIJPFS6rS3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 20 Mar 2026 13:46:40 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 20 Mar 2026 13:46:40 +0800 From: Billy Tsai Date: Fri, 20 Mar 2026 13:46:37 +0800 Subject: [PATCH v3 3/4] iio: adc: aspeed: Replace mdelay() with fsleep() for ADC stabilization delay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-adc-v3-3-bc0eac04ef7c@aspeedtech.com> References: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> In-Reply-To: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai , "Andy Shevchenko" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773985600; l=1623; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=nns6L1IWBrZoZF9du3xsZHyx3aa79UG/Vd6Iwrl6+E4=; b=Qc5vqncqRGLGuLM3Fsty10mqFKuRhZ1K7YvVPDSfqOOI7GdSgN9c7iYBIUjuu+r/PXnsiWOSN xvgaZ6SBLT/B4iMZs8MNxA6NU+aeBkM4p6HjYbiLcTYDEzWDGEZyaYw X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= The ADC stabilization delays in compensation mode and battery sensing mode do not require atomic context. Using mdelay() here results in unnecessary busy waiting. Replace mdelay(1) with fsleep(1000) to allow the scheduler to run other tasks while waiting for the ADC to stabilize. Also fix a minor typo in the comment ("adc" -> "ADC"). Suggested-by: Andy Shevchenko Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 3ff24474f394..a1a6296d3003 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -259,7 +259,7 @@ static int aspeed_adc_compensation(struct iio_dev *indi= o_dev) * After enable compensating sensing mode need to wait some time for ADC = stable * Experiment result is 1ms. */ - mdelay(1); + fsleep(1000); =20 for (index =3D 0; index < 16; index++) { /* @@ -314,10 +314,10 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_= dev, ASPEED_ADC_BAT_SENSING_ENABLE, data->base + ASPEED_REG_ENGINE_CONTROL); /* - * After enable battery sensing mode need to wait some time for adc sta= ble + * After enable battery sensing mode need to wait some time for ADC sta= ble * Experiment result is 1ms. */ - mdelay(1); + fsleep(1000); *val =3D readw(data->base + chan->address); *val =3D (*val * data->battery_mode_gain.mult) / data->battery_mode_gain.div; --=20 2.34.1 From nobody Mon Apr 6 09:09:46 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94C7E31B10B; Fri, 20 Mar 2026 05:46:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773985617; cv=none; b=mXu9iS01cbRuk8qvAWvgZwaBCGpDorPIOrCMFskWbj8iLzJGagKaDmq4T4tFWNuIXpIccXxR7E1PD2GM4rG8spahDHqFhH9sxLNu7vy8V8bhkfTjUllCPmuVbWEgwSOm0TzsSw6QDlKLTeYrK+PKn8poFtjJAOIvqtXnK7Kw3qE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773985617; c=relaxed/simple; bh=/PC/NyBFthLGN9cW7uymrG04TM1B2jgffJp1BtJPzvk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=EnCtaFPlhgjga+/9S6P85S0w2ch+o4g8wUfX/ll7C55Q7QYJKKiSyldDbE97W4KyapCwr7XmmY43SaJ3V7EAN61F3ofZD7ATRrE390sN/ppmThJmikDn6iJdSZ6lSmOqRdpVDuumpeiZVtqOpghrpQLCR2ilkVAEt6ciD1tFmtg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 20 Mar 2026 13:46:40 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 20 Mar 2026 13:46:40 +0800 From: Billy Tsai Date: Fri, 20 Mar 2026 13:46:38 +0800 Subject: [PATCH v3 4/4] iio: adc: aspeed: Reserve battery sensing channel for on-demand use Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-adc-v3-4-bc0eac04ef7c@aspeedtech.com> References: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> In-Reply-To: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773985600; l=3092; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=/PC/NyBFthLGN9cW7uymrG04TM1B2jgffJp1BtJPzvk=; b=RB0NDy13+uaIk/DhgVlJNMyfDOujB1yWJsODg/DzzJixBX0EPQO4bj3PrRMZ6FyO9JwEA9sjk oZj077hCYySDDdpXtifv5kTKDBB2UvkJ3EWbmhtBLqw2kADoQ7YRzNB X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= For controllers with battery sensing capability (AST2600/AST2700), the last channel uses a different circuit design optimized for battery voltage measurement. This channel should not be enabled by default along with other channels to avoid potential interference and power efficiency issues. This ensures optimal power efficiency for normal ADC operations while maintaining full functionality when battery sensing is needed. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index a1a6296d3003..b3dee172adbf 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -138,6 +138,13 @@ static inline u32 aspeed_adc_channels_mask(unsigned in= t num_channels) =20 static inline unsigned int aspeed_adc_get_active_channels(const struct asp= eed_adc_data *data) { + /* + * For controllers with battery sensing capability, the last channel + * is reserved for battery sensing and should not be included in + * normal channel operations. + */ + if (data->model_data->bat_sense_sup) + return data->model_data->num_channels - 1; return data->model_data->num_channels; } =20 @@ -305,9 +312,26 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_d= ev, =20 switch (mask) { case IIO_CHAN_INFO_RAW: + adc_engine_control_reg_val =3D readl(data->base + ASPEED_REG_ENGINE_CONT= ROL); + /* + * For battery sensing capable controllers, we need to enable + * the specific channel before reading. This is required because + * the battery channel may not be enabled by default. + */ + if (data->model_data->bat_sense_sup && + chan->channel =3D=3D ASPEED_ADC_BATTERY_CHANNEL) { + u32 ctrl_reg =3D adc_engine_control_reg_val & ~ASPEED_ADC_CTRL_CHANNEL; + + ctrl_reg |=3D ASPEED_ADC_CTRL_CHANNEL_ENABLE(chan->channel); + writel(ctrl_reg, data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * After enable a new channel need to wait some time for ADC stable + * Experiment result is 1ms. + */ + fsleep(1000); + } + if (data->battery_sensing && chan->channel =3D=3D ASPEED_ADC_BATTERY_CHA= NNEL) { - adc_engine_control_reg_val =3D - readl(data->base + ASPEED_REG_ENGINE_CONTROL); writel(adc_engine_control_reg_val | FIELD_PREP(ASPEED_ADC_CH7_MODE, ASPEED_ADC_CH7_BAT) | @@ -321,11 +345,11 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_= dev, *val =3D readw(data->base + chan->address); *val =3D (*val * data->battery_mode_gain.mult) / data->battery_mode_gain.div; - /* Restore control register value */ - writel(adc_engine_control_reg_val, - data->base + ASPEED_REG_ENGINE_CONTROL); } else *val =3D readw(data->base + chan->address); + /* Restore control register value */ + writel(adc_engine_control_reg_val, + data->base + ASPEED_REG_ENGINE_CONTROL); return IIO_VAL_INT; =20 case IIO_CHAN_INFO_OFFSET: --=20 2.34.1