From nobody Mon Apr 6 09:19:39 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 805743803D4 for ; Thu, 19 Mar 2026 20:53:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773953592; cv=none; b=Z8XzkvMAc4lANAPJU3l+DEHkdHWcGE9LiXR0VvDio10HzK4ybU9l3JVz9GjRRJwlE/j1NxHtPBT7cDOrqN90HTLhKtjppzcbhqQUc2OE9D+txdXAJ8pvd1o7tsfwdAuBBE6BP6L/wAW078NqGCaHdD3KhHu7hluXsCQoneEp6Ag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773953592; c=relaxed/simple; bh=1Wt2RJNSUdsclmDRyhyj3eVjEZz+1kdkT6/YVAbFK6Q=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=HEifjxMNeV4JlucfvnZ/6PWLyxDadOvV7q53Bpf43w71toLhgCjccRyJggvVvh3uqJ0VlE2vyV5Atrl+87/kfULf22otwD0PmfAym6b+i7b+EAJfElGar6y114AtJxkmO2bjl01yZ6wLaZD+1LDmnxXa0kUjH9LXMkIfpn1BFpk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=McXBw5W3; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="McXBw5W3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1773953589; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=pDuNk1maIwkM81h0xNfMndhfHmB77PaC4WV88nssjB0=; b=McXBw5W3N11+uelusVDq9juErpwySXLli2+9NwR7jSzr735n54ehiOYbsVT2RwWlpwg0WC 9swT66SLRXRMhQMpTFprNFZB64EJ8cH9tYE6Tx71av6QMFF+Kitt2tg6+bgVoEDOFNi30G RqJVXj1vcwZeh0gUGu6fY78TUNhgSTI= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-493-pHpjlvk4OxSbyGwG68z_pg-1; Thu, 19 Mar 2026 16:53:05 -0400 X-MC-Unique: pHpjlvk4OxSbyGwG68z_pg-1 X-Mimecast-MFC-AGG-ID: pHpjlvk4OxSbyGwG68z_pg_1773953583 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 591CD18002C8; Thu, 19 Mar 2026 20:53:03 +0000 (UTC) Received: from ShadowPeak.redhat.com (unknown [10.45.224.50]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 627931955F21; Thu, 19 Mar 2026 20:52:59 +0000 (UTC) From: Petr Oros To: netdev@vger.kernel.org Cc: ivecera@redhat.com, Petr Oros , Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Arkadiusz Kubalewski , Simon Horman , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH iwl-net v4] ice: fix missing dpll notifications for SW pins Date: Thu, 19 Mar 2026 21:52:56 +0100 Message-ID: <20260319205256.998876-1-poros@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" The SMA/U.FL pin redesign (commit 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")) introduced software-controlled pins that wrap backing CGU input/output pins, but never updated the notification and data paths to propagate pin events to these SW wrappers. There are three problems: 1) ice_dpll_notify_changes() sends dpll_pin_change_ntf() only for the direct CGU input pin stored in d->active_input. When the active input changes, SW pins (SMA/U.FL) that wrap the old or new active input never receive a change notification. As a result, userspace consumers such as synce4l that monitor SMA pins via dpll netlink never learn when the pin state transitions (e.g. from SELECTABLE to CONNECTED). 2) ice_dpll_phase_offset_get() returns p->phase_offset for non-active SW pins, but this field is never updated for SW pins. The PPS phase offset monitor updates the backing CGU input's phase_offset (p->input->phase_offset), not the SW pin's own field. As a result non-active SW pins always report zero phase offset even when the backing CGU input has valid PPS measurements. 3) ice_dpll_pins_notify_mask() does not propagate phase offset change notifications to SW pins either. When a HW CGU pin gets a phase offset change notification, the SMA/U.FL pin wrapping it is never notified, so userspace consumers (ts2phc, synce4l) monitoring SW pins via dpll netlink never receive phase offset updates. Fix all three by: - In ice_dpll_phase_offset_get(), return the backing CGU input's phase_offset for input-direction SW pins instead of the SW pin's own (always zero) field. - Introduce ice_dpll_pin_ntf(), a thin wrapper around dpll_pin_change_ntf() that also sends notifications to any registered SMA/U.FL pin whose backing CGU input matches. Replace all direct dpll_pin_change_ntf() calls in the periodic notification paths with ice_dpll_pin_ntf(), so SW pins are automatically notified whenever their backing HW pin is. Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control") Signed-off-by: Petr Oros Reviewed-by: Aleksandr Loktionov Reviewed-by: Ivan Vecera --- v4: - expanded scope to also fix phase offset reporting and phase offset notifications for SW pins (problems 2 and 3 above) - replaced ice_dpll_sw_pin_needs_notify() with ice_dpll_pin_ntf(), a unified wrapper that covers all notification paths - squashed into a single patch v3: https://lore.kernel.org/all/20260220140700.2910174-1-poros@redhat.com/ - added kdoc for ice_dpll_sw_pin_needs_notify() helper v2: https://lore.kernel.org/all/20260219131500.2271897-1-poros@redhat.com/ - extracted ice_dpll_sw_pin_needs_notify() helper for readability - moved loop variable into for() scope v1: https://lore.kernel.org/all/20260218211414.1411163-1-poros@redhat.com/ --- drivers/net/ethernet/intel/ice/ice_dpll.c | 47 +++++++++++++++++------ 1 file changed, 36 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index 62f75701d65205..5cfa19da099bfc 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -1915,7 +1915,10 @@ ice_dpll_phase_offset_get(const struct dpll_pin *pin= , void *pin_priv, d->active_input =3D=3D p->input->pin)) *phase_offset =3D d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; else if (d->phase_offset_monitor_period) - *phase_offset =3D p->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; + *phase_offset =3D (p->input && + p->direction =3D=3D DPLL_PIN_DIRECTION_INPUT ? + p->input->phase_offset : + p->phase_offset) * ICE_DPLL_PHASE_OFFSET_FACTOR; else *phase_offset =3D 0; mutex_unlock(&pf->dplls.lock); @@ -2609,6 +2612,27 @@ static u64 ice_generate_clock_id(struct ice_pf *pf) return pci_get_dsn(pf->pdev); } =20 +/** + * ice_dpll_pin_ntf - notify pin change including any SW pin wrappers + * @dplls: pointer to dplls struct + * @pin: the dpll_pin that changed + * + * Send a change notification for @pin and for any registered SMA/U.FL pin + * whose backing CGU input matches @pin. + */ +static void ice_dpll_pin_ntf(struct ice_dplls *dplls, struct dpll_pin *pin) +{ + dpll_pin_change_ntf(pin); + for (int i =3D 0; i < ICE_DPLL_PIN_SW_NUM; i++) { + if (dplls->sma[i].pin && dplls->sma[i].input && + dplls->sma[i].input->pin =3D=3D pin) + dpll_pin_change_ntf(dplls->sma[i].pin); + if (dplls->ufl[i].pin && dplls->ufl[i].input && + dplls->ufl[i].input->pin =3D=3D pin) + dpll_pin_change_ntf(dplls->ufl[i].pin); + } +} + /** * ice_dpll_notify_changes - notify dpll subsystem about changes * @d: pointer do dpll @@ -2617,6 +2641,7 @@ static u64 ice_generate_clock_id(struct ice_pf *pf) */ static void ice_dpll_notify_changes(struct ice_dpll *d) { + struct ice_dplls *dplls =3D &d->pf->dplls; bool pin_notified =3D false; =20 if (d->prev_dpll_state !=3D d->dpll_state) { @@ -2625,17 +2650,17 @@ static void ice_dpll_notify_changes(struct ice_dpll= *d) } if (d->prev_input !=3D d->active_input) { if (d->prev_input) - dpll_pin_change_ntf(d->prev_input); + ice_dpll_pin_ntf(dplls, d->prev_input); d->prev_input =3D d->active_input; if (d->active_input) { - dpll_pin_change_ntf(d->active_input); + ice_dpll_pin_ntf(dplls, d->active_input); pin_notified =3D true; } } if (d->prev_phase_offset !=3D d->phase_offset) { d->prev_phase_offset =3D d->phase_offset; if (!pin_notified && d->active_input) - dpll_pin_change_ntf(d->active_input); + ice_dpll_pin_ntf(dplls, d->active_input); } } =20 @@ -2664,6 +2689,7 @@ static bool ice_dpll_is_pps_phase_monitor(struct ice_= pf *pf) =20 /** * ice_dpll_pins_notify_mask - notify dpll subsystem about bulk pin changes + * @dplls: pointer to dplls struct * @pins: array of ice_dpll_pin pointers registered within dpll subsystem * @pin_num: number of pins * @phase_offset_ntf_mask: bitmask of pin indexes to notify @@ -2673,15 +2699,14 @@ static bool ice_dpll_is_pps_phase_monitor(struct ic= e_pf *pf) * * Context: Must be called while pf->dplls.lock is released. */ -static void ice_dpll_pins_notify_mask(struct ice_dpll_pin *pins, +static void ice_dpll_pins_notify_mask(struct ice_dplls *dplls, + struct ice_dpll_pin *pins, u8 pin_num, u32 phase_offset_ntf_mask) { - int i =3D 0; - - for (i =3D 0; i < pin_num; i++) - if (phase_offset_ntf_mask & (1 << i)) - dpll_pin_change_ntf(pins[i].pin); + for (int i =3D 0; i < pin_num; i++) + if (phase_offset_ntf_mask & BIT(i)) + ice_dpll_pin_ntf(dplls, pins[i].pin); } =20 /** @@ -2857,7 +2882,7 @@ static void ice_dpll_periodic_work(struct kthread_wor= k *work) ice_dpll_notify_changes(de); ice_dpll_notify_changes(dp); if (phase_offset_ntf) - ice_dpll_pins_notify_mask(d->inputs, d->num_inputs, + ice_dpll_pins_notify_mask(d, d->inputs, d->num_inputs, phase_offset_ntf); =20 resched: --=20 2.52.0