From nobody Mon Apr 6 12:17:08 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8F5283EE1FC for ; Thu, 19 Mar 2026 16:56:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773939371; cv=none; b=VR+s/VLdH+8qPnn+aF39sIq6v+nuYk/Gjgv8UFJJiQQ9uthcJO77wB1S2nBGJC7liqvcVSLg0amdDRgs9efh58Y1jGY09Zq4ehu2CCE0XXBBc5xhNmP9VV6iSWpS5miTWnmBpT3cdiVFpIjw+Q2d6p2Dq5/3wGPzGBUZeale6yM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773939371; c=relaxed/simple; bh=CzTvhG0iWztFjyCLI92Oywedfo2+U6jopMpG9EnHlNk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Rm9eP9T5AVeEQzA+vsVeCHgIiYd6j8BW4VWhxx4gykOyFTYk5nkmvOQNcwUvAmeJfvjCEWmlKbpS47VzTmCIeQgtzcxezJD0LoG8ZQykXelzkaaX/DjDv+h3LviGV6EY3Rd2XrABydwYpu9uxJLHTWaBsXOmhc9XgeCHi2HRbVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A2F791A25; Thu, 19 Mar 2026 09:55:59 -0700 (PDT) Received: from e134344.cambridge.arm.com (e134344.arm.com [10.1.196.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C7BAA3F7BD; Thu, 19 Mar 2026 09:56:02 -0700 (PDT) From: Ben Horgan To: ben.horgan@arm.com Cc: amitsinght@marvell.com, baisheng.gao@unisoc.com, baolin.wang@linux.alibaba.com, carl@os.amperecomputing.com, dave.martin@arm.com, david@kernel.org, dfustini@baylibre.com, fenghuay@nvidia.com, gshan@redhat.com, james.morse@arm.com, jonathan.cameron@huawei.com, kobak@nvidia.com, lcherian@marvell.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, peternewman@google.com, punit.agrawal@oss.qualcomm.com, quic_jiles@quicinc.com, reinette.chatre@intel.com, rohit.mathew@arm.com, scott@os.amperecomputing.com, sdonthineni@nvidia.com, tan.shaopeng@fujitsu.com, xhao@linux.alibaba.com, zengheng4@huawei.com Subject: [RFC PATCH v2 4/5] arm_mpam: resctrl: Add resctrl_arch_cntr_read() & resctrl_arch_reset_cntr() Date: Thu, 19 Mar 2026 16:55:39 +0000 Message-ID: <20260319165540.381410-5-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319165540.381410-1-ben.horgan@arm.com> References: <20260319165540.381410-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Morse When used in 'mbm_event' mode, ABMC emulation, resctrl uses arch hooks to read and reset the memory bandwidth utilization (MBWU) counters. Add these. Reviewed-by: Jonathan Cameron Signed-off-by: James Morse Signed-off-by: Ben Horgan --- Changes since rfc v1: Move __reset_mon() and reset_mon_cdp_safe() helpers here support mbwu in __read_mon() Mention mbm_event mode in commit message --- drivers/resctrl/mpam_resctrl.c | 99 +++++++++++++++++++++++++++++----- 1 file changed, 86 insertions(+), 13 deletions(-) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 4f49483f6445..9f6f0091f356 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -121,19 +121,6 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, s= truct rdt_l3_mon_domain *d { } =20 -void resctrl_arch_reset_cntr(struct rdt_resource *r, struct rdt_l3_mon_dom= ain *d, - u32 closid, u32 rmid, int cntr_id, - enum resctrl_event_id eventid) -{ -} - -int resctrl_arch_cntr_read(struct rdt_resource *r, struct rdt_l3_mon_domai= n *d, - u32 unused, u32 rmid, int cntr_id, - enum resctrl_event_id eventid, u64 *val) -{ - return -EOPNOTSUPP; -} - bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r) { return (r =3D=3D &mpam_resctrl_controls[RDT_RESOURCE_L3].resctrl_res); @@ -459,6 +446,14 @@ static int __read_mon(struct mpam_resctrl_mon *mon, st= ruct mpam_component *mon_c /* Shift closid to account for CDP */ closid =3D resctrl_get_config_index(closid, cdp_type); =20 + if (mon_idx =3D=3D USE_PRE_ALLOCATED) { + int mbwu_idx =3D resctrl_arch_rmid_idx_encode(closid, rmid); + + mon_idx =3D mon->mbwu_idx_to_mon[mbwu_idx]; + if (mon_idx =3D=3D -1) + return -ENOENT; + } + if (irqs_disabled()) { /* Check if we can access this domain without an IPI */ return -EIO; @@ -531,6 +526,84 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, str= uct rdt_domain_hdr *hdr, closid, rmid, val); } =20 +/* MBWU counters when in ABMC mode */ +int resctrl_arch_cntr_read(struct rdt_resource *r, struct rdt_l3_mon_domai= n *d, + u32 closid, u32 rmid, int mon_idx, + enum resctrl_event_id eventid, u64 *val) +{ + struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[eventid]; + struct mpam_resctrl_dom *l3_dom; + struct mpam_component *mon_comp; + + if (!mpam_is_enabled()) + return -EINVAL; + + if (eventid =3D=3D QOS_L3_OCCUP_EVENT_ID || !mon->class) + return -EINVAL; + + l3_dom =3D container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_comp =3D l3_dom->mon_comp[eventid]; + + return read_mon_cdp_safe(mon, mon_comp, mpam_feat_msmon_mbwu, mon_idx, + closid, rmid, val); +} + +static void __reset_mon(struct mpam_resctrl_mon *mon, struct mpam_componen= t *mon_comp, + int mon_idx, + enum resctrl_conf_type cdp_type, u32 closid, u32 rmid) +{ + struct mon_cfg cfg =3D { }; + + if (!mpam_is_enabled()) + return; + + /* Shift closid to account for CDP */ + closid =3D resctrl_get_config_index(closid, cdp_type); + + if (mon_idx =3D=3D USE_PRE_ALLOCATED) { + int mbwu_idx =3D resctrl_arch_rmid_idx_encode(closid, rmid); + + mon_idx =3D mon->mbwu_idx_to_mon[mbwu_idx]; + } + + if (mon_idx =3D=3D -1) + return; + cfg.mon =3D mon_idx; + mpam_msmon_reset_mbwu(mon_comp, &cfg); +} + +static void reset_mon_cdp_safe(struct mpam_resctrl_mon *mon, struct mpam_c= omponent *mon_comp, + int mon_idx, u32 closid, u32 rmid) +{ + if (cdp_enabled) { + __reset_mon(mon, mon_comp, mon_idx, CDP_CODE, closid, rmid); + __reset_mon(mon, mon_comp, mon_idx, CDP_DATA, closid, rmid); + } else { + __reset_mon(mon, mon_comp, mon_idx, CDP_NONE, closid, rmid); + } +} + +/* Reset an assigned counter */ +void resctrl_arch_reset_cntr(struct rdt_resource *r, struct rdt_l3_mon_dom= ain *d, + u32 closid, u32 rmid, int cntr_id, + enum resctrl_event_id eventid) +{ + struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[eventid]; + struct mpam_resctrl_dom *l3_dom; + struct mpam_component *mon_comp; + + if (!mpam_is_enabled()) + return; + + if (eventid =3D=3D QOS_L3_OCCUP_EVENT_ID || !mon->class) + return; + + l3_dom =3D container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_comp =3D l3_dom->mon_comp[eventid]; + + reset_mon_cdp_safe(mon, mon_comp, USE_PRE_ALLOCATED, closid, rmid); +} + /* * The rmid realloc threshold should be for the smallest cache exposed to * resctrl. --=20 2.43.0