From nobody Mon Apr 6 12:11:30 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4337F3E9F8B; Thu, 19 Mar 2026 15:55:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935708; cv=none; b=aL86/k9QLNIwRoIYXwV/nYHEAYuKc7JBbsrsh1bwFzr9iOL2iKFmFFS+kAc/H8QApjnkX6rjNkt99plUCmNiywPLHZSiBr916OoxrbJjupHnj4aIPyjq3flDCwU1eriGpSkEMo6xu+WAINNOl0tcoEq5rjZuaai6PwzJi37YSbI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935708; c=relaxed/simple; bh=5AiOb3jETxyRJvZGUFJ/xnBLl99mPGjZTXFFvUFA3ak=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LimGDLYai2JTwURGejJ++dLjFwX7xr41POxJwRxSWsiBjOsuTZryYzVFtoHO3rE5Iyjik5HvFPWACbwXoWinFIddLBJcll+uGljnYSF1qI8duhYvnFoh23pqZafKmixNsXzR0QhH0pbpl8+/DXoR8sd3M5fezjqkMAgUuL7/eXA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: eSkdCWfbRIeMYiQynzDSPw== X-CSE-MsgGUID: CV76qGvRQTWOkZiEj7rQ+g== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:55:05 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 45F7040189E4; Fri, 20 Mar 2026 00:54:55 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 02/22] arm64: dts: renesas: rzv2h: Add audio clock inputs Date: Thu, 19 Mar 2026 16:53:14 +0100 Message-ID: <20260319155334.51278-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Model external audio clock inputs as CPG input clocks for RZ/V2H family SoCs (RZ/V2H, RZ/V2N, RZ/G3E), allowing the Audio Clock Generator (ADG) to derive internal audio clocks from these external sources. The clock frequencies are board-specific and must be overridden in the board DTS files. Signed-off-by: John Madieu --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 27 ++++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 27 ++++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 27 ++++++++++++++++++++-- 3 files changed, 75 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index cbb48ff5028f..2787d316ea04 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -14,6 +14,27 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + audio_clka: audio-clka { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkb: audio-clkb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkc: audio-clkc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + audio_extal_clk: audio-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -270,8 +291,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible =3D "renesas,r9a09g047-cpg"; reg =3D <0 0x10420000 0 0x10000>; - clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names =3D "audio_extal", "rtxin", "qextal"; + clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>; + clock-names =3D "audio_extal", "rtxin", "qextal", + "audio_clka", "audio_clkb", "audio_clkc"; #clock-cells =3D <2>; #reset-cells =3D <1>; #power-domain-cells =3D <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g056.dtsi index 9192c5bf7e59..a16474184d92 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -32,6 +32,27 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + audio_clka: audio-clka { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkb: audio-clkb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkc: audio-clkc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + audio_extal_clk: audio-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -293,8 +314,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible =3D "renesas,r9a09g056-cpg"; reg =3D <0 0x10420000 0 0x10000>; - clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names =3D "audio_extal", "rtxin", "qextal"; + clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>; + clock-names =3D "audio_extal", "rtxin", "qextal", + "audio_clka", "audio_clkb", "audio_clkc"; #clock-cells =3D <2>; #reset-cells =3D <1>; #power-domain-cells =3D <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index 9581af58024e..e15b47dc93d4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -14,6 +14,27 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + audio_clka: audio-clka { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkb: audio-clkb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkc: audio-clkc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + audio_extal_clk: audio-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -275,8 +296,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible =3D "renesas,r9a09g057-cpg"; reg =3D <0 0x10420000 0 0x10000>; - clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names =3D "audio_extal", "rtxin", "qextal"; + clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>; + clock-names =3D "audio_extal", "rtxin", "qextal", + "audio_clka", "audio_clkb", "audio_clkc"; #clock-cells =3D <2>; #reset-cells =3D <1>; #power-domain-cells =3D <0>; --=20 2.25.1