From nobody Mon Apr 6 12:17:06 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6ACB53ED13C; Thu, 19 Mar 2026 15:57:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935867; cv=none; b=CI0HN47st45k9tvHKUMDoFTY6hrliZkZ1P6k4vHmEUTHD8hjsz4NK/87A57RoqvuRSvZpbQIqr2CyKrb1TjKsvrVfz498QcYbbQNtGprhQwDtdKCMY7VMF/82utcwoTHVBLO+OROd6nLjmWAEgaaj/Wz77WLTJEprBYmImlgMQ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935867; c=relaxed/simple; bh=ZWNA9uavhP8FrqatXX9iuu73+hNnRk30MT/RFhXnJ7M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kYz7zoMe0T1w3p5mmLl+hYi7rTV5gCbhHwK8Zp5DluIuGgcjWAEcFmaq/fl/7Esp2mtIJBdAK+7jwAUwfDSp7i2UtWzjIc19VR6XVaPxBZ3V5zvGpIOLQ4//1AgIzOIYsT4dKcmssMCiRFlM+88W8Gx9Ad4LxRlLxIVOzFN0QNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: bK8mxX0GQ0iDeaLJAx0Vnw== X-CSE-MsgGUID: B9Xz0Yt3Qb+xxlN3XP0S9A== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:57:44 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 09A28401BC72; Fri, 20 Mar 2026 00:57:34 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 19/22] arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator Date: Thu, 19 Mar 2026 16:53:31 +0100 Message-ID: <20260319155334.51278-20-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the Renesas 5P35023 (Versa3) programmable clock generator on the I2C2 bus along with its 24MHz input clock (x2 oscillator) to feed the audio subsystem. The Versa3 provides the following audio-related clock outputs: - Output 0: 24MHz (reference) - Output 1: 12.288MHz (audio, 48kHz family) - Output 2: 11.2896MHz (audio, 44.1kHz family) - Output 3: 12.288MHz (audio) These clocks are required for the audio codec found on the RZ/G3E SMARC EVK. Signed-off-by: John Madieu --- .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index 3b571c096752..2f1548d78c2c 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -71,6 +71,12 @@ reg_vdd0p8v_others: regulator-vdd0p8v-others { regulator-always-on; }; =20 + x2: x2-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + /* 32.768kHz crystal */ x3: x3-clock { compatible =3D "fixed-clock"; @@ -124,6 +130,20 @@ raa215300: pmic@12 { =20 interrupts-extended =3D <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING= >; }; + + versa3: clock-generator@68 { + compatible =3D "renesas,5p35023"; + reg =3D <0x68>; + #clock-cells =3D <1>; + clocks =3D <&x2>; + + assigned-clocks =3D <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates =3D <24000000>, <12288000>, + <11289600>, <12288000>, + <25000000>, <25000000>; + }; }; =20 &i3c { --=20 2.25.1