From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2F9C43E8C67; Thu, 19 Mar 2026 15:55:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935704; cv=none; b=B54brxNyRIuRipCm8dYxtYnddcDtCqLmvryiCif7qDmCpyLZzps5DFSpv7xxIRRy21xyZswrJWoTjYR77VDSrWDo6VDlf41GLltN4QXpCQvkGq2uSSNh4sKNqQ48Y5DbxI/GCKJp4/sblh9IT7ix8K3pZRRvlC2g1LVWl4VYDLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935704; c=relaxed/simple; bh=SV/OayDQfhRBvC34hoRJqvFiBa2hhApp5q8zHXZd8dY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sULF9J9a8DzduvRMyWsWlc5FBfirBOwMU49mFxyumLZCqY2F2g5cSEiv7q1WsOtIii9hQ5E02OF58iSD7pHfLoum6K/ZQfF+FK1qrJOTlW7HDpFI3bGY/Nj8kPbEz4byoddICCJ50soid6Jw5YlaTQh8+1ytzgwEV1RQsE4ysm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: iOnTbv/sQICmFYQO4rOrwQ== X-CSE-MsgGUID: 42cgRTraSzC981uwCYPIJA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:54:55 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8EA104018A06; Fri, 20 Mar 2026 00:54:46 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 01/22] dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family Date: Thu, 19 Mar 2026 16:53:13 +0100 Message-ID: <20260319155334.51278-2-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RZ/V2H, RZ/V2N, and RZ/G3E support external audio clock inputs (AUDIO_CLKA, AUDIO_CLKB, AUDIO_CLKC) that can be used by the Audio Clock Generator (ADG) to derive internal audio clocks. These clocks are optional and their frequencies are set by the board. Update the bindings to allow these optional clocks for all RZ/V2H family SoCs. Signed-off-by: John Madieu --- .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml= b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index f261445bf341..bed5643b39d3 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -26,16 +26,26 @@ properties: maxItems: 1 =20 clocks: + minItems: 3 + maxItems: 6 items: - description: AUDIO_EXTAL clock input - description: RTXIN clock input - description: QEXTAL clock input + - description: AUDIO_CLKA clock input + - description: AUDIO_CLKB clock input + - description: AUDIO_CLKC clock input =20 clock-names: + minItems: 3 + maxItems: 6 items: - const: audio_extal - const: rtxin - const: qextal + - const: audio_clka + - const: audio_clkb + - const: audio_clkc =20 '#clock-cells': description: | --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4337F3E9F8B; Thu, 19 Mar 2026 15:55:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935708; cv=none; b=aL86/k9QLNIwRoIYXwV/nYHEAYuKc7JBbsrsh1bwFzr9iOL2iKFmFFS+kAc/H8QApjnkX6rjNkt99plUCmNiywPLHZSiBr916OoxrbJjupHnj4aIPyjq3flDCwU1eriGpSkEMo6xu+WAINNOl0tcoEq5rjZuaai6PwzJi37YSbI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935708; c=relaxed/simple; bh=5AiOb3jETxyRJvZGUFJ/xnBLl99mPGjZTXFFvUFA3ak=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LimGDLYai2JTwURGejJ++dLjFwX7xr41POxJwRxSWsiBjOsuTZryYzVFtoHO3rE5Iyjik5HvFPWACbwXoWinFIddLBJcll+uGljnYSF1qI8duhYvnFoh23pqZafKmixNsXzR0QhH0pbpl8+/DXoR8sd3M5fezjqkMAgUuL7/eXA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: eSkdCWfbRIeMYiQynzDSPw== X-CSE-MsgGUID: CV76qGvRQTWOkZiEj7rQ+g== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:55:05 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 45F7040189E4; Fri, 20 Mar 2026 00:54:55 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 02/22] arm64: dts: renesas: rzv2h: Add audio clock inputs Date: Thu, 19 Mar 2026 16:53:14 +0100 Message-ID: <20260319155334.51278-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Model external audio clock inputs as CPG input clocks for RZ/V2H family SoCs (RZ/V2H, RZ/V2N, RZ/G3E), allowing the Audio Clock Generator (ADG) to derive internal audio clocks from these external sources. The clock frequencies are board-specific and must be overridden in the board DTS files. Signed-off-by: John Madieu --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 27 ++++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 27 ++++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 27 ++++++++++++++++++++-- 3 files changed, 75 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index cbb48ff5028f..2787d316ea04 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -14,6 +14,27 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + audio_clka: audio-clka { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkb: audio-clkb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkc: audio-clkc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + audio_extal_clk: audio-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -270,8 +291,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible =3D "renesas,r9a09g047-cpg"; reg =3D <0 0x10420000 0 0x10000>; - clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names =3D "audio_extal", "rtxin", "qextal"; + clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>; + clock-names =3D "audio_extal", "rtxin", "qextal", + "audio_clka", "audio_clkb", "audio_clkc"; #clock-cells =3D <2>; #reset-cells =3D <1>; #power-domain-cells =3D <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g056.dtsi index 9192c5bf7e59..a16474184d92 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -32,6 +32,27 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + audio_clka: audio-clka { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkb: audio-clkb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkc: audio-clkc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + audio_extal_clk: audio-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -293,8 +314,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible =3D "renesas,r9a09g056-cpg"; reg =3D <0 0x10420000 0 0x10000>; - clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names =3D "audio_extal", "rtxin", "qextal"; + clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>; + clock-names =3D "audio_extal", "rtxin", "qextal", + "audio_clka", "audio_clkb", "audio_clkc"; #clock-cells =3D <2>; #reset-cells =3D <1>; #power-domain-cells =3D <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index 9581af58024e..e15b47dc93d4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -14,6 +14,27 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + audio_clka: audio-clka { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkb: audio-clkb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkc: audio-clkc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + audio_extal_clk: audio-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -275,8 +296,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible =3D "renesas,r9a09g057-cpg"; reg =3D <0 0x10420000 0 0x10000>; - clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names =3D "audio_extal", "rtxin", "qextal"; + clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>; + clock-names =3D "audio_extal", "rtxin", "qextal", + "audio_clka", "audio_clkb", "audio_clkc"; #clock-cells =3D <2>; #reset-cells =3D <1>; #power-domain-cells =3D <0>; --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A22EA3E3179; Thu, 19 Mar 2026 15:55:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935717; cv=none; b=pdEXkn96ykP2mA+wkw9xmzokUV15mgk/+tJj2Qc6ptKBWgp6NvG2qFIcPVDeE56lNAaRKHpDLdmOEkJ3Xh4QiQSgm8mFas03VmGqFhLnAlentoRBeJnURpdfcz0Ff1ylh6T45h8sXKw45BG+EJABh8/8NnARSQYgu6OQaBUNuBg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935717; c=relaxed/simple; bh=4H5xNHQGaLEsYQIqbSLum1bdJ1kgsgD+WOf8GzjLQgM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VJSHmXQrLGhntKd98QUHsWmAvlP68/1HucGQDjtDHKO5bbDYBiIfVX5cCfCQbmSviuIe/b9z7W0aH6YbgWydXrreA0gCVfEziKzrqy5Bx+0KfONW/Lzo0WUUTc+BU+EgFHuB06pt8Rj804n4TSPiGTd3xzJtzecubAHIRdVWk8c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: w02E6jskQwmn5Juqr7KHWA== X-CSE-MsgGUID: tJFVv2+aRpiT4PUv8M4wqg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:55:13 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 95140401B2E9; Fri, 20 Mar 2026 00:55:05 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 03/22] clk: renesas: r9a09g047: Add audio clock and reset support Date: Thu, 19 Mar 2026 16:53:15 +0100 Message-ID: <20260319155334.51278-4-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clock and reset entries for audio-related modules on the RZ/G3E SoC. Target modules are: - SSIU (Serial Sound Interface Unit) with SSI ch0-ch9 - SCU (Sampling Rate Converter Unit) with SRC ch0-ch9, DVC ch0-ch1, CTU/MIX ch0-ch1 - ADMAC (Audio DMA Controller) - ADG (Audio Clock Generator) with divider input clocks and audio master clock outputs While at it, reorder plldty_div16 to group it with other plldty fixed dividers. Signed-off-by: John Madieu --- drivers/clk/renesas/r9a09g047-cpg.c | 130 +++++++++++++++++++++++++++- 1 file changed, 129 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a0= 9g047-cpg.c index 1e9896742a06..3623cc5db38d 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -22,6 +22,9 @@ enum clk_ids { CLK_AUDIO_EXTAL, CLK_RTXIN, CLK_QEXTAL, + CLK_AUDIO_CLKA, + CLK_AUDIO_CLKB, + CLK_AUDIO_CLKC, =20 /* PLL Clocks */ CLK_PLLCM33, @@ -34,6 +37,8 @@ enum clk_ids { /* Internal Core Clocks */ CLK_PLLCM33_DIV3, CLK_PLLCM33_DIV4, + CLK_PLLCM33_DIV4_DDIV2, + CLK_PLLCM33_DIV4_DDIV2_DIV2, CLK_PLLCM33_DIV5, CLK_PLLCM33_DIV16, CLK_PLLCM33_GEAR, @@ -41,15 +46,19 @@ enum clk_ids { CLK_SMUX2_XSPI_CLK1, CLK_PLLCM33_XSPI, CLK_PLLCLN_DIV2, + CLK_PLLCLN_DIV4, CLK_PLLCLN_DIV8, CLK_PLLCLN_DIV16, CLK_PLLCLN_DIV20, + CLK_PLLCLN_DIV32, CLK_PLLCLN_DIV64, CLK_PLLCLN_DIV256, CLK_PLLCLN_DIV1024, CLK_PLLDTY_ACPU, CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU_DIV4, + CLK_PLLDTY_DIV2, + CLK_PLLDTY_DIV4, CLK_PLLDTY_DIV8, CLK_PLLDTY_RCPU, CLK_PLLDTY_RCPU_DIV4, @@ -64,6 +73,7 @@ enum clk_ids { CLK_PLLDTY_DIV16, CLK_PLLVDO_CRU0, CLK_PLLVDO_GPU, + CLK_CDIV5_MAINOSC, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -120,6 +130,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] = __initconst =3D { DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), DEF_INPUT("rtxin", CLK_RTXIN), DEF_INPUT("qextal", CLK_QEXTAL), + DEF_INPUT("audio_clka", CLK_AUDIO_CLKA), + DEF_INPUT("audio_clkb", CLK_AUDIO_CLKB), + DEF_INPUT("audio_clkc", CLK_AUDIO_CLKC), =20 /* PLL Clocks */ DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), @@ -135,6 +148,12 @@ static const struct cpg_core_clk r9a09g047_core_clks[]= __initconst =3D { DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5), DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), =20 + DEF_DDIV(".pllcm33_div4_ddiv2", CLK_PLLCM33_DIV4_DDIV2, CLK_PLLCM33_DIV4, + CDDIV0_DIVCTL1, dtable_2_64), + DEF_FIXED(".pllcm33_div4_ddiv2_div2", CLK_PLLCM33_DIV4_DDIV2_DIV2, + CLK_PLLCM33_DIV4_DDIV2, 1, 2), + + DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVC= TL1, dtable_2_64), =20 DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xs= pi_clk0), @@ -142,9 +161,11 @@ static const struct cpg_core_clk r9a09g047_core_clks[]= __initconst =3D { DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_= DIVCTL3, dtable_2_16), DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), + DEF_FIXED(".pllcln_div4", CLK_PLLCLN_DIV4, CLK_PLLCLN, 1, 4), DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20), + DEF_FIXED(".pllcln_div32", CLK_PLLCLN_DIV32, CLK_PLLCLN, 1, 32), DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64), DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256), DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024), @@ -152,7 +173,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[]= __initconst =3D { DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dta= ble_2_64), DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, = 2), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, = 4), + DEF_FIXED(".plldty_div2", CLK_PLLDTY_DIV2, CLK_PLLDTY, 1, 2), + DEF_FIXED(".plldty_div4", CLK_PLLDTY_DIV4, CLK_PLLDTY, 1, 4), DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), + DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), =20 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_F= IX, 1, 2), @@ -164,9 +188,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] = __initconst =3D { DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_= gbe0_rxclk), DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_= gbe1_txclk), DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_= gbe1_rxclk), - DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dta= ble_2_64), DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, = 4), + DEF_FIXED(".cdiv5_mainosc", CLK_CDIV5_MAINOSC, CLK_QEXTAL, 1, 5), =20 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dta= ble_2_4), DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtabl= e_2_64), @@ -438,6 +462,96 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[]= __initconst =3D { BUS_MSTOP(3, BIT(4))), DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, BUS_MSTOP(2, BIT(15))), + DEF_MOD("ssif_clk", CLK_PLLCLN_DIV8, 15, 5, 7, 21, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("scu_clk", CLK_PLLCLN_DIV8, 15, 6, 7, 22, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("scu_clkx2", CLK_PLLCLN_DIV4, 15, 7, 7, 23, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("admac_clk", CLK_PLLCLN_DIV8, 15, 8, 7, 24, + BUS_MSTOP(2, BIT(5))), + DEF_MOD("adg_clks1", CLK_PLLCLN_DIV8, 15, 9, 7, 25, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_clk_200m", CLK_PLLCLN_DIV8, 15, 10, 7, 26, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_audio_clka", CLK_AUDIO_CLKA, 15, 11, 7, 27, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_audio_clkb", CLK_AUDIO_CLKB, 15, 12, 7, 28, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_audio_clkc", CLK_AUDIO_CLKC, 15, 13, 7, 29, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi0_clk", CLK_PLLCLN_DIV8, 22, 0, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi1_clk", CLK_PLLCLN_DIV8, 22, 1, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi2_clk", CLK_PLLCLN_DIV8, 22, 2, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi3_clk", CLK_PLLCLN_DIV8, 22, 3, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi4_clk", CLK_PLLCLN_DIV8, 22, 4, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi5_clk", CLK_PLLCLN_DIV8, 22, 5, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi6_clk", CLK_PLLCLN_DIV8, 22, 6, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi7_clk", CLK_PLLCLN_DIV8, 22, 7, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi8_clk", CLK_PLLCLN_DIV8, 22, 8, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi9_clk", CLK_PLLCLN_DIV8, 22, 9, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("dvc0_clk", CLK_PLLCLN_DIV8, 23, 0, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("dvc1_clk", CLK_PLLCLN_DIV8, 23, 1, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("ctu0_mix0_clk", CLK_PLLCLN_DIV8, 23, 2, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("ctu1_mix1_clk", CLK_PLLCLN_DIV8, 23, 3, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src0_clk", CLK_PLLCLN_DIV8, 23, 4, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src1_clk", CLK_PLLCLN_DIV8, 23, 5, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src2_clk", CLK_PLLCLN_DIV8, 23, 6, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src3_clk", CLK_PLLCLN_DIV8, 23, 7, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src4_clk", CLK_PLLCLN_DIV8, 23, 8, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src5_clk", CLK_PLLCLN_DIV8, 23, 9, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src6_clk", CLK_PLLCLN_DIV8, 23, 10, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src7_clk", CLK_PLLCLN_DIV8, 23, 11, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src8_clk", CLK_PLLCLN_DIV8, 23, 12, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src9_clk", CLK_PLLCLN_DIV8, 23, 13, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("scu_supply_clk", CLK_PLLCLN_DIV8, 23, 14, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("ssif_supply_clk", CLK_PLLCLN_DIV8, 24, 0, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi0_clk", CLK_PLLCLN_DIV8, 24, 1, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi1_clk", CLK_PLLCLN_DIV8, 24, 2, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi2_clk", CLK_PLLCLN_DIV8, 24, 3, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi3_clk", CLK_PLLCLN_DIV8, 24, 4, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi4_clk", CLK_PLLCLN_DIV8, 24, 5, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi5_clk", CLK_PLLCLN_DIV8, 24, 6, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi6_clk", CLK_PLLCLN_DIV8, 24, 7, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi7_clk", CLK_PLLCLN_DIV8, 24, 8, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi8_clk", CLK_PLLCLN_DIV8, 24, 9, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi9_clk", CLK_PLLCLN_DIV8, 24, 10, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), }; =20 static const struct rzv2h_reset r9a09g047_resets[] __initconst =3D { @@ -509,6 +623,20 @@ static const struct rzv2h_reset r9a09g047_resets[] __i= nitconst =3D { DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */ DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */ DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */ + DEF_RST(14, 1, 6, 18), /* SSIF_0_ASYNC_RESET_SSI */ + DEF_RST(14, 2, 6, 19), /* SSIF_0_SYNC_RESET_SSI0 */ + DEF_RST(14, 3, 6, 20), /* SSIF_0_SYNC_RESET_SSI1 */ + DEF_RST(14, 4, 6, 21), /* SSIF_0_SYNC_RESET_SSI2 */ + DEF_RST(14, 5, 6, 22), /* SSIF_0_SYNC_RESET_SSI3 */ + DEF_RST(14, 6, 6, 23), /* SSIF_0_SYNC_RESET_SSI4 */ + DEF_RST(14, 7, 6, 24), /* SSIF_0_SYNC_RESET_SSI5 */ + DEF_RST(14, 8, 6, 25), /* SSIF_0_SYNC_RESET_SSI6 */ + DEF_RST(14, 9, 6, 26), /* SSIF_0_SYNC_RESET_SSI7 */ + DEF_RST(14, 10, 6, 27), /* SSIF_0_SYNC_RESET_SSI8 */ + DEF_RST(14, 11, 6, 28), /* SSIF_0_SYNC_RESET_SSI9 */ + DEF_RST(14, 12, 6, 29), /* SCU_RESET_SRU */ + DEF_RST(14, 13, 6, 30), /* ADMAC_ARESETN */ + DEF_RST(14, 14, 6, 31), /* ADG_RST_RESET_ADG */ DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ }; =20 --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0919C3E5EFE; Thu, 19 Mar 2026 15:55:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935726; cv=none; b=FJU/5lzkvRTxg99nBT457XyGWUYvFQskaSdERgGB2JWd7n0UIrRaagiTa0mHbVDMC8ZfhI1LlvmseF76jwil5Gk84C93b+GLQ65PTpPA5W8F1KHj3O9L1RhUR0HoLn5chtuPF0XoO/XymNY6n0X93pONA8UW4heIAF9/jr6OGG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935726; c=relaxed/simple; bh=jHN1z2RQBeF4SF4pTau84UmLX++ijP/BwnLa6SKIfIg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GsIsvbxklw4POtJ/yUFHX3yVY+Rm/IhD0etN+bpQtg8clB8S140SP8EsaK1PW6unZgmiwh7NfZMpWRA/3Wg5lScrcDBSgubN20SqpB2daCVKVh7oWojBldFRKtZe3X+dMjsUH0iTK+645pWSiGKOa1RT67G97nVVMiJv3kpGkCE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 3Ks5o3k/RheGial0d3almQ== X-CSE-MsgGUID: hTCTNvf2RIeo74gClBGz7Q== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:55:23 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8B930401B307; Fri, 20 Mar 2026 00:55:14 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 04/22] dt-bindings: dma: renesas,rz-dmac: Document optional DMA ACK cell Date: Thu, 19 Mar 2026 16:53:16 +0100 Message-ID: <20260319155334.51278-5-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some peripherals on RZ/V2H, RZ/V2N, and RZ/G3E SoCs require explicit ACK signal routing through the ICU. Document the optional second cell in the DMA specifier for specifying the ACK signal number. The first cell remains unchanged and specifies the encoded MID/RID and channel configuration. The optional second cell specifies the DMA ACK signal number for peripherals requiring level-based handshaking. Signed-off-by: John Madieu --- .../bindings/dma/renesas,rz-dmac.yaml | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/D= ocumentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index 0155a15e200b..f3966c288890 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -63,17 +63,27 @@ properties: - const: register =20 '#dma-cells': - const: 1 - description: + description: | The cell specifies the encoded MID/RID or the REQ No values of the DMAC port connected to the DMA client and the slave channel configuration parameters. + Use 1 cell for basic DMA configuration. + Use 2 cells when DMA ACK signal routing through ICU is required + (RZ/V2H, RZ/V2N, RZ/G3E audio peripherals such as SSIU, SPDIF, SRC, = DVC). + + First cell: bits[0:9] - Specifies the MID/RID or the REQ No value bit[10] - Specifies DMA request high enable (HIEN) bit[11] - Specifies DMA request detection type (LVL) bits[12:14] - Specifies DMAACK output mode (AM) bit[15] - Specifies Transfer Mode (TM) =20 + Second cell (optional, when #dma-cells =3D <2>): + bits[6:0] - DMA acknowledge signal number (from ICU ACK table), + where 0 is a valid signal number. + Required for peripherals using level-based DMA + handshaking (SSIU, SPDIF, RSPI, SCU, ADC, PDM). + dma-channels: const: 16 =20 @@ -212,6 +222,20 @@ allOf: - renesas,icu - resets =20 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-dmac + then: + properties: + '#dma-cells': + enum: [1, 2] + else: + properties: + '#dma-cells': + const: 1 + - if: properties: compatible: --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BBA0B3E3165; Thu, 19 Mar 2026 15:55:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935734; cv=none; b=oz87tAfLu7RxgDsCoMz3Yuz+fwueeq2bYNboS90ILhOPeEIOzyisMZ+57xRiGkBDiZGusY/iypv22PYlC/ml6/Mxsfwnwhy/OMqylIe37GSpwaIVFqNbyLiyc2PKpcFUVQ1uHZHJdAwrh2fAQGD0u4wqqHazyFlNYZTpdJ85MTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935734; c=relaxed/simple; bh=D1SxVx/NovE4mVqL7CRPWG12P1m0PWzlzknGr5qNHPY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GwS3pAiqNn74kkTTEFWF96/r+4ope7Yj+yNfYtCSA4VEpXDZ+VCNpZBlkDSyK9AbBFTi9mEJhDk9P2Fyk7ioFb2yePu7XDczXwFNat2q2rNLY4k63okQRn/hz+zXpjI5Y2wJm+QZVTKxo1XcDEddATEq6LNmtr291C8RdYc858E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: qTtFXDT6SN6Efg7qGNScTQ== X-CSE-MsgGUID: gS+yZpz/TEmdxvkqMknL3g== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:55:31 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8CB44401B2FD; Fri, 20 Mar 2026 00:55:23 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 05/22] irqchip/renesas-rzv2h: Add DMA ACK signal routing support Date: Thu, 19 Mar 2026 16:53:17 +0100 Message-ID: <20260319155334.51278-6-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some peripherals (mainly from audio module) found on RZ/G3E SoCs require explicit ACK signal routing through the ICU via the ICU_DMACKSELk registers. Add rzv2h_icu_register_dma_ack() to configure this routing. Signed-off-by: John Madieu --- drivers/irqchip/irq-renesas-rzv2h.c | 36 +++++++++++++++++++++++ include/linux/irqchip/irq-renesas-rzv2h.h | 5 ++++ 2 files changed, 41 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index ce790590f7ca..4d10b19f7e09 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -151,6 +151,12 @@ struct rzv2h_hw_info { #define ICU_DMAC_PREP_DMAREQ(sel, up) (FIELD_PREP(ICU_DMAC_DkRQ_SEL_MASK,= (sel)) \ << ICU_DMAC_DMAREQ_SHIFT(up)) =20 +/* DMAC ACK routing - 4 x 7-bit fields per 32-bit register, 8-bit spacing = */ +#define ICU_DMAC_DACK_SEL_MASK GENMASK(6, 0) +#define ICU_DMAC_DACK_SHIFT(n) ((n) * 8) +#define ICU_DMAC_DACK_FIELD_MASK(n) (ICU_DMAC_DACK_SEL_MASK << ICU_DMAC_D= ACK_SHIFT(n)) +#define ICU_DMAC_PREP_DACK(val, n) (((val) & ICU_DMAC_DACK_SEL_MASK) << I= CU_DMAC_DACK_SHIFT(n)) + /** * struct rzv2h_icu_priv - Interrupt Control Unit controller private data = structure. * @base: Controller's base address @@ -188,6 +194,36 @@ void rzv2h_icu_register_dma_req(struct platform_device= *icu_dev, u8 dmac_index, } EXPORT_SYMBOL_GPL(rzv2h_icu_register_dma_req); =20 +/** + * rzv2h_icu_register_dma_ack - Configure DMA ACK signal routing + * @icu_dev: ICU platform device + * @dmac_index: DMAC instance index (0-4) + * @dmac_channel: DMAC channel number (0-15), or RZV2H_ICU_DMAC_ACK_NO_DEF= AULT to clear + * @ack_no: Peripheral ACK number (0-88), used as index into ICU_DMACKSELk + * + * Routes the DMAC channel's ACK signal to the peripheral specified by ack= _no, + * or clears the entry when dmac_channel is RZV2H_ICU_DMAC_ACK_NO_DEFAULT. + */ +void rzv2h_icu_register_dma_ack(struct platform_device *icu_dev, u8 dmac_i= ndex, + u8 dmac_channel, u16 ack_no) +{ + struct rzv2h_icu_priv *priv =3D platform_get_drvdata(icu_dev); + u8 reg_idx =3D ack_no / 4; + u8 field_idx =3D ack_no & 0x3; + u8 dmac_ack_src =3D (dmac_channel =3D=3D RZV2H_ICU_DMAC_ACK_NO_DEFAULT) ? + RZV2H_ICU_DMAC_ACK_NO_DEFAULT : + (dmac_index * 16 + dmac_channel); + u32 val; + + guard(raw_spinlock_irqsave)(&priv->lock); + + val =3D readl(priv->base + ICU_DMACKSELk(reg_idx)); + val &=3D ~ICU_DMAC_DACK_FIELD_MASK(field_idx); + val |=3D ICU_DMAC_PREP_DACK(dmac_ack_src, field_idx); + writel(val, priv->base + ICU_DMACKSELk(reg_idx)); +} +EXPORT_SYMBOL_GPL(rzv2h_icu_register_dma_ack); + static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *dat= a) { return data->domain->host_data; diff --git a/include/linux/irqchip/irq-renesas-rzv2h.h b/include/linux/irqc= hip/irq-renesas-rzv2h.h index 618a60d2eac0..4ffa898eaaf2 100644 --- a/include/linux/irqchip/irq-renesas-rzv2h.h +++ b/include/linux/irqchip/irq-renesas-rzv2h.h @@ -11,13 +11,18 @@ #include =20 #define RZV2H_ICU_DMAC_REQ_NO_DEFAULT 0x3ff +#define RZV2H_ICU_DMAC_ACK_NO_DEFAULT 0x7f =20 #ifdef CONFIG_RENESAS_RZV2H_ICU void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_i= ndex, u8 dmac_channel, u16 req_no); +void rzv2h_icu_register_dma_ack(struct platform_device *icu_dev, u8 dmac_i= ndex, + u8 dmac_channel, u16 ack_no); #else static inline void rzv2h_icu_register_dma_req(struct platform_device *icu_= dev, u8 dmac_index, u8 dmac_channel, u16 req_no) { } +static inline void rzv2h_icu_register_dma_ack(struct platform_device *icu_= dev, u8 dmac_index, + u8 dmac_channel, u16 ack_no) { } #endif =20 #endif /* __LINUX_IRQ_RENESAS_RZV2H */ --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7322D3E9F69; Thu, 19 Mar 2026 15:55:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935744; cv=none; b=dtysFWSYQREJue/kgduF0qLo3/FqOPdFISddFxQSuYXkF+1XkHUNy6XOsPVVZmtqe3Euq2RXhdU6QkOnTu7uvq/g5UyvG70vmURH7ooMqULyzM268CMuxbUMVcFyE1rKkxJyh6xDoCkgynFT+7GntK248yxHNycMIH8/B+VMMWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935744; c=relaxed/simple; bh=8Zc6OScGYb+5AvQgNfZdnReDdkm0l7MnThx/FKQQlXE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kCi/ZFkw8wxr6Dq6tugnFnoH5XLXAyo7IAScv2EaCw8JH07KZ8LdYYL31kjWYVYA3gpeal2Qrr5/LdTxRHh2bilRrnUeFxRVgRZblNfa2ugZ5Egjdm9q1nj4mZCmua6njJ61Fo8ZTC8GV7IV/oEy3U0Y+I98nd26bj6Tl0z3YiI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: iKDvIp6eQS6mGUie7p6U6A== X-CSE-MsgGUID: gjoqKmIDTFSnk/wIw57Zwg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:55:41 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 90E41401B2E9; Fri, 20 Mar 2026 00:55:32 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 06/22] dma: sh: rz-dmac: Add DMA ACK signal routing support Date: Thu, 19 Mar 2026 16:53:18 +0100 Message-ID: <20260319155334.51278-7-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some peripherals, mainly from the audio subsystem, on RZ/V2H and RZ/G3E SoCs require explicit ACK signal routing through the ICU. Extend the driver to support an optional second DMA specifier cell that contains the ACK signal number. When present, program the ICU accordingly during channel configuration. This maintains backward compatibility with single-cell DMA specifiers. Signed-off-by: John Madieu --- drivers/dma/sh/rz-dmac.c | 40 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 240c318b5753..d4a8cc95b871 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -97,6 +97,7 @@ struct rz_dmac_chan { u32 chcfg; u32 chctrl; int mid_rid; + int dmac_ack; =20 struct { u32 nxla; @@ -124,6 +125,9 @@ struct rz_dmac_icu { struct rz_dmac_info { void (*icu_register_dma_req)(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel, u16 req_no); + void (*icu_register_dma_ack)(struct platform_device *icu_dev, u8 dmac_ind= ex, + u8 dmac_channel, u16 ack_no); + u16 default_dma_ack_no; u16 default_dma_req_no; }; =20 @@ -362,6 +366,25 @@ static void rz_dmac_set_dma_req_no(struct rz_dmac *dma= c, unsigned int index, rz_dmac_set_dmars_register(dmac, index, req_no); } =20 +static void rz_dmac_set_dma_ack_no(struct rz_dmac *dmac, unsigned int inde= x, + u16 ack_no) +{ + if (!dmac->info->icu_register_dma_ack) + return; + + dmac->info->icu_register_dma_ack(dmac->icu.pdev, dmac->icu.dmac_index, + index, ack_no); +} + +static void rz_dmac_reset_dma_ack_no(struct rz_dmac *dmac, int ack_no) +{ + if (ack_no < 0 || !dmac->info->icu_register_dma_ack) + return; + + dmac->info->icu_register_dma_ack(dmac->icu.pdev, dmac->icu.dmac_index, + dmac->info->default_dma_ack_no, ack_no); +} + static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel) { struct dma_chan *chan =3D &channel->vc.chan; @@ -431,6 +454,7 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct r= z_dmac_chan *channel) channel->lmdesc.tail =3D lmdesc; =20 rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); + rz_dmac_set_dma_ack_no(dmac, channel->index, channel->dmac_ack); } =20 static void rz_dmac_prepare_descs_for_cyclic(struct rz_dmac_chan *channel) @@ -485,6 +509,7 @@ static void rz_dmac_prepare_descs_for_cyclic(struct rz_= dmac_chan *channel) channel->lmdesc.tail =3D lmdesc; =20 rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); + rz_dmac_set_dma_ack_no(dmac, channel->index, channel->dmac_ack); } =20 static int rz_dmac_xfer_desc(struct rz_dmac_chan *chan) @@ -567,6 +592,9 @@ static void rz_dmac_free_chan_resources(struct dma_chan= *chan) channel->mid_rid =3D -EINVAL; } =20 + rz_dmac_reset_dma_ack_no(dmac, channel->dmac_ack); + channel->dmac_ack =3D -EINVAL; + spin_unlock_irqrestore(&channel->vc.lock, flags); =20 list_for_each_entry_safe(desc, _desc, &channel->ld_free, node) { @@ -814,6 +842,7 @@ static void rz_dmac_device_synchronize(struct dma_chan = *chan) dev_warn(dmac->dev, "DMA Timeout"); =20 rz_dmac_set_dma_req_no(dmac, channel->index, dmac->info->default_dma_req_= no); + rz_dmac_reset_dma_ack_no(dmac, channel->dmac_ack); } =20 static struct rz_lmdesc * @@ -1164,6 +1193,10 @@ static bool rz_dmac_chan_filter(struct dma_chan *cha= n, void *arg) channel->chcfg =3D CHCFG_FILL_TM(ch_cfg) | CHCFG_FILL_AM(ch_cfg) | CHCFG_FILL_LVL(ch_cfg) | CHCFG_FILL_HIEN(ch_cfg); =20 + /* ACK signal number from optional second cell */ + if (dma_spec->args_count =3D=3D 2 && dmac->info->icu_register_dma_ack) + channel->dmac_ack =3D FIELD_GET(GENMASK(6, 0), dma_spec->args[1]); + return !test_and_set_bit(channel->mid_rid, dmac->modules); } =20 @@ -1172,7 +1205,8 @@ static struct dma_chan *rz_dmac_of_xlate(struct of_ph= andle_args *dma_spec, { dma_cap_mask_t mask; =20 - if (dma_spec->args_count !=3D 1) + /* Accept 1 cell (basic) or 2 cells (with ACK signal) */ + if (dma_spec->args_count < 1 || dma_spec->args_count > 2) return NULL; =20 /* Only slave DMA channels can be allocated via DT */ @@ -1200,6 +1234,7 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac, =20 channel->index =3D index; channel->mid_rid =3D -EINVAL; + channel->dmac_ack =3D -EINVAL; =20 /* Request the channel interrupt. */ scnprintf(pdev_irqname, sizeof(pdev_irqname), "ch%u", index); @@ -1568,6 +1603,7 @@ static int rz_dmac_resume(struct device *dev) guard(spinlock_irqsave)(&channel->vc.lock); =20 rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); + rz_dmac_set_dma_ack_no(dmac, channel->index, channel->dmac_ack); =20 if (!(channel->status & BIT(RZ_DMAC_CHAN_STATUS_CYCLIC))) { rz_dmac_ch_writel(&dmac->channels[i], CHCTRL_DEFAULT, CHCTRL, 1); @@ -1599,6 +1635,8 @@ static const struct dev_pm_ops rz_dmac_pm_ops =3D { =20 static const struct rz_dmac_info rz_dmac_v2h_info =3D { .icu_register_dma_req =3D rzv2h_icu_register_dma_req, + .icu_register_dma_ack =3D rzv2h_icu_register_dma_ack, + .default_dma_ack_no =3D RZV2H_ICU_DMAC_ACK_NO_DEFAULT, .default_dma_req_no =3D RZV2H_ICU_DMAC_REQ_NO_DEFAULT, }; =20 --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B331F3E9F98; Thu, 19 Mar 2026 15:55:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935753; cv=none; b=ECcOCjCIca2VnWyLzKdfogH8+G2ilWLVsFDPdP/iIg0fZYy6IEkS2glJfrtg0cc2hETAaQZHw+jN5RRXzFniHy6yIEf95f2AvW+OjKBucSmqBwASxJ8L8L5qwxOKfpNIDCL3ZgQriEJC7doObmY/ef6ErtsYvwLcVdiV6WRDOYk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935753; c=relaxed/simple; bh=WMGWqBcFvtN0MqdxLGHwwwFXLWkz09suF6r3VyqdT6o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C8hSZ7UrA4gqt+WvruirVvy2gVK2ujLzDsp6MLa1NPI1u/Y05s5oHVzehFKMzKvlEsQMFm9+gyg4XXdUTNvjgnBK39dY72EXbMhYCtQu6G9AlAk22L4noD97wbwIJe2xYnbOATOIhtr4OvJBiMD4LbapHNxRW9akl0E5A9gPI1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: USGzfxtPTtOp4X4fVEVwtg== X-CSE-MsgGUID: M1oSURy5ThW4E1gGpRs7pA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:55:50 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5AD4C401B2FD; Fri, 20 Mar 2026 00:55:41 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 07/22] ASoC: dt-bindings: renesas,rsnd: Add RZ/G3E support Date: Thu, 19 Mar 2026 16:53:19 +0100 Message-ID: <20260319155334.51278-8-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the RZ/G3E (R9A09G047) SoC audio subsystem. RZ/G3E has a different audio architecture from R-Car Gen2/Gen3/Gen4, with additional clocks and resets: - Per-SSI ADG clocks (adg.ssi.0-9) - SCU related clocks (scu, scu_x2, scu_supply) - SSIF supply clock - AUDMAC peri-peri clock - ADG clock - Additional resets for SCU, ADG, and AUDMAC peri-peri RZ/G3E has 5 DMA controllers that can all be used by audio peripherals. To allow the DMA core to distribute channels across all available controllers, increase the maximum number of DMA entries in DVC, SRC, and SSIU sub-nodes so that multiple providers can be listed with repeated channel names. Signed-off-by: John Madieu --- .../bindings/sound/renesas,rsnd.yaml | 169 +++++++++++++++--- 1 file changed, 148 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml b/Do= cumentation/devicetree/bindings/sound/renesas,rsnd.yaml index e8a2acb92646..bc8885c4fa24 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml @@ -58,6 +58,7 @@ properties: - renesas,rcar_sound-gen2 - renesas,rcar_sound-gen3 - renesas,rcar_sound-gen4 + - renesas,rcar_sound-r9a09g047 # RZ/G3E =20 reg: minItems: 1 @@ -97,20 +98,22 @@ properties: =20 resets: minItems: 1 - maxItems: 11 + maxItems: 14 =20 reset-names: minItems: 1 - maxItems: 11 + maxItems: 14 =20 clocks: description: References to SSI/SRC/MIX/CTU/DVC/AUDIO_CLK clocks. minItems: 1 - maxItems: 31 + maxItems: 47 =20 clock-names: description: List of necessary clock names. # details are defined below + minItems: 1 + maxItems: 47 =20 # ports is below port: @@ -136,9 +139,17 @@ properties: =20 properties: dmas: - maxItems: 1 + description: + Must contain unique DMA specifiers, one per available + DMAC. On RZ/G3E, up to 5 for transmission. + minItems: 1 + maxItems: 5 dma-names: - const: tx + minItems: 1 + maxItems: 5 + items: + enum: + - tx required: - dmas - dma-names @@ -174,13 +185,19 @@ properties: interrupts: maxItems: 1 dmas: - maxItems: 2 + description: + Must contain unique DMA specifiers, one per available + DMAC, for each transfer direction. On RZ/G3E, up to 5 + for transmission and up to 5 for reception. + minItems: 2 + maxItems: 10 dma-names: - allOf: - - items: - enum: - - tx - - rx + minItems: 2 + maxItems: 10 + items: + enum: + - tx + - rx additionalProperties: false =20 rcar_sound,ssiu: @@ -193,13 +210,19 @@ properties: =20 properties: dmas: - maxItems: 2 + description: + Must contain unique DMA specifiers, one per available + DMAC, for each transfer direction. On RZ/G3E, up to 5 + for transmission and up to 5 for reception. + minItems: 2 + maxItems: 10 dma-names: - allOf: - - items: - enum: - - tx - - rx + minItems: 2 + maxItems: 10 + items: + enum: + - tx + - rx required: - dmas - dma-names @@ -299,7 +322,7 @@ allOf: - sru - ssi - adg - # for Gen2/Gen3 + # for Gen2/Gen3/RZ/G3E - if: properties: compatible: @@ -307,6 +330,7 @@ allOf: enum: - renesas,rcar_sound-gen2 - renesas,rcar_sound-gen3 + - renesas,rcar_sound-r9a09g047 then: properties: reg: @@ -338,7 +362,7 @@ allOf: - sdmc =20 # -------------------- - # clock-names + # clock-names / reset-names # -------------------- - if: properties: @@ -354,10 +378,18 @@ allOf: - ssi.0 - ssiu.0 - clkin - else: + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar_sound-gen2 + - renesas,rcar_sound-gen3 + then: properties: + clocks: + maxItems: 31 clock-names: - minItems: 1 maxItems: 31 items: oneOf: @@ -368,6 +400,101 @@ allOf: - pattern: '^ctu\.[0-1]$' - pattern: '^dvc\.[0-1]$' - pattern: '^clk_(a|b|c|i)$' + resets: + maxItems: 11 + reset-names: + maxItems: 11 + items: + oneOf: + - const: ssi-all + - pattern: '^ssi\.[0-9]$' + rcar_sound,dvc: + patternProperties: + "^dvc-[0-1]$": + properties: + dmas: + maxItems: 1 + dma-names: + maxItems: 1 + rcar_sound,src: + patternProperties: + "^src-[0-9]$": + properties: + dmas: + maxItems: 2 + dma-names: + maxItems: 2 + rcar_sound,ssiu: + patternProperties: + "^ssiu-[0-9]+$": + properties: + dmas: + maxItems: 2 + dma-names: + maxItems: 2 + # for RZ/G3E + - if: + properties: + compatible: + contains: + const: renesas,rcar_sound-r9a09g047 + then: + properties: + clocks: + maxItems: 47 + clock-names: + maxItems: 47 + items: + oneOf: + - const: ssi-all + - pattern: '^ssi\.[0-9]$' + - pattern: '^src\.[0-9]$' + - pattern: '^mix\.[0-1]$' + - pattern: '^ctu\.[0-1]$' + - pattern: '^dvc\.[0-1]$' + - pattern: '^clk_(a|b|c|i)$' + - const: ssif_supply + - const: scu + - const: scu_x2 + - const: scu_supply + - pattern: '^adg\.ssi\.[0-9]$' + - const: audmac_pp + - const: adg + resets: + maxItems: 14 + reset-names: + maxItems: 14 + items: + oneOf: + - const: ssi-all + - pattern: '^ssi\.[0-9]$' + - const: scu + - const: adg + - const: audmac_pp + rcar_sound,dvc: + patternProperties: + "^dvc-[0-1]$": + properties: + dmas: + maxItems: 5 + dma-names: + maxItems: 5 + rcar_sound,src: + patternProperties: + "^src-[0-9]$": + properties: + dmas: + maxItems: 10 + dma-names: + maxItems: 10 + rcar_sound,ssiu: + patternProperties: + "^ssiu-[0-9]+$": + properties: + dmas: + maxItems: 10 + dma-names: + maxItems: 10 =20 unevaluatedProperties: false =20 --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 075B93E3C42; Thu, 19 Mar 2026 15:56:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935763; cv=none; b=YvY7C/rACdpn6CBDPvxT+mDeT9v5PNXVbVtYRJsOvQRwQ6s9qx9sdNIWgsJqkg3LZbSuzKAusryGc+S6SidDWCmfE/TcdATWbvcT1Sgon2DEMHXOdjOaXUsvv8V55pORSW3Z7RfrDIfusyw7my/9eoX8t0g8khvqGgBcxuY9iiM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935763; c=relaxed/simple; bh=xBi/6GdjjHb2f+q/zcIqO+EtIKlDvHhNI4h79qztEs8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pipdAqaZVDj8d6c1Sh875UuCT3i0F3KdXmLtD4FAGgm7CBtW/JZWgzqEbzQFgO/k1BWvgu/V9tlZKsaRU0XQsYLdqYQXJcxAUGsZZ3u7Tkx/c5yiwT9Vb+M/rD04C1FOjozjxYMIwCK3W1lB3M9Tp/Kul1zFDcd5ROuKuX0vWVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: bPvZtcP1RB2LatR+u0I+NA== X-CSE-MsgGUID: Os/YalWtRFWBrRxYQsVh9w== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:56:00 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 85E05401B2FD; Fri, 20 Mar 2026 00:55:51 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 08/22] ASoC: rsnd: Add reset controller support to rsnd_mod Date: Thu, 19 Mar 2026 16:53:20 +0100 Message-ID: <20260319155334.51278-9-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RZ/G3E SoC requires per-module reset control for the audio subsystem. Add reset controller support to struct rsnd_mod and update rsnd_mod_init() to accept and handle a reset_control parameter. Signed-off-by: John Madieu --- sound/soc/renesas/rcar/adg.c | 2 +- sound/soc/renesas/rcar/cmd.c | 2 +- sound/soc/renesas/rcar/core.c | 14 +++++++++++++- sound/soc/renesas/rcar/ctu.c | 2 +- sound/soc/renesas/rcar/dma.c | 4 ++-- sound/soc/renesas/rcar/dvc.c | 2 +- sound/soc/renesas/rcar/mix.c | 2 +- sound/soc/renesas/rcar/rsnd.h | 3 +++ sound/soc/renesas/rcar/src.c | 2 +- sound/soc/renesas/rcar/ssi.c | 2 +- sound/soc/renesas/rcar/ssiu.c | 2 +- 11 files changed, 26 insertions(+), 11 deletions(-) diff --git a/sound/soc/renesas/rcar/adg.c b/sound/soc/renesas/rcar/adg.c index 8641b73d1f77..0105c60a144e 100644 --- a/sound/soc/renesas/rcar/adg.c +++ b/sound/soc/renesas/rcar/adg.c @@ -780,7 +780,7 @@ int rsnd_adg_probe(struct rsnd_priv *priv) return -ENOMEM; =20 ret =3D rsnd_mod_init(priv, &adg->mod, &adg_ops, - NULL, 0, 0); + NULL, NULL, 0, 0); if (ret) return ret; =20 diff --git a/sound/soc/renesas/rcar/cmd.c b/sound/soc/renesas/rcar/cmd.c index 8d9a1e345a22..13beef389797 100644 --- a/sound/soc/renesas/rcar/cmd.c +++ b/sound/soc/renesas/rcar/cmd.c @@ -171,7 +171,7 @@ int rsnd_cmd_probe(struct rsnd_priv *priv) =20 for_each_rsnd_cmd(cmd, priv, i) { int ret =3D rsnd_mod_init(priv, rsnd_mod_get(cmd), - &rsnd_cmd_ops, NULL, + &rsnd_cmd_ops, NULL, NULL, RSND_MOD_CMD, i); if (ret) return ret; diff --git a/sound/soc/renesas/rcar/core.c b/sound/soc/renesas/rcar/core.c index 69fb19964a71..6de576736507 100644 --- a/sound/soc/renesas/rcar/core.c +++ b/sound/soc/renesas/rcar/core.c @@ -90,6 +90,7 @@ * */ =20 +#include #include #include #include "rsnd.h" @@ -196,18 +197,29 @@ int rsnd_mod_init(struct rsnd_priv *priv, struct rsnd_mod *mod, struct rsnd_mod_ops *ops, struct clk *clk, + struct reset_control *rstc, enum rsnd_mod_type type, int id) { - int ret =3D clk_prepare(clk); + int ret; =20 + ret =3D clk_prepare_enable(clk); if (ret) return ret; =20 + ret =3D reset_control_deassert(rstc); + if (ret) { + clk_disable_unprepare(clk); + return ret; + } + + clk_disable(clk); + mod->id =3D id; mod->ops =3D ops; mod->type =3D type; mod->clk =3D clk; + mod->rstc =3D rstc; mod->priv =3D priv; =20 return 0; diff --git a/sound/soc/renesas/rcar/ctu.c b/sound/soc/renesas/rcar/ctu.c index bd4c61f9fb3c..81bba6a1af6e 100644 --- a/sound/soc/renesas/rcar/ctu.c +++ b/sound/soc/renesas/rcar/ctu.c @@ -360,7 +360,7 @@ int rsnd_ctu_probe(struct rsnd_priv *priv) } =20 ret =3D rsnd_mod_init(priv, rsnd_mod_get(ctu), &rsnd_ctu_ops, - clk, RSND_MOD_CTU, i); + clk, NULL, RSND_MOD_CTU, i); if (ret) goto rsnd_ctu_probe_done; =20 diff --git a/sound/soc/renesas/rcar/dma.c b/sound/soc/renesas/rcar/dma.c index 2035ce06fe4c..68c859897e68 100644 --- a/sound/soc/renesas/rcar/dma.c +++ b/sound/soc/renesas/rcar/dma.c @@ -803,7 +803,7 @@ static int rsnd_dma_alloc(struct rsnd_dai_stream *io, s= truct rsnd_mod *mod, =20 *dma_mod =3D rsnd_mod_get(dma); =20 - ret =3D rsnd_mod_init(priv, *dma_mod, ops, NULL, + ret =3D rsnd_mod_init(priv, *dma_mod, ops, NULL, NULL, type, dma_id); if (ret < 0) return ret; @@ -879,5 +879,5 @@ int rsnd_dma_probe(struct rsnd_priv *priv) priv->dma =3D dmac; =20 /* dummy mem mod for debug */ - return rsnd_mod_init(NULL, &mem, &mem_ops, NULL, 0, 0); + return rsnd_mod_init(NULL, &mem, &mem_ops, NULL, NULL, 0, 0); } diff --git a/sound/soc/renesas/rcar/dvc.c b/sound/soc/renesas/rcar/dvc.c index 988cbddbc611..bf7146ceb5f6 100644 --- a/sound/soc/renesas/rcar/dvc.c +++ b/sound/soc/renesas/rcar/dvc.c @@ -364,7 +364,7 @@ int rsnd_dvc_probe(struct rsnd_priv *priv) } =20 ret =3D rsnd_mod_init(priv, rsnd_mod_get(dvc), &rsnd_dvc_ops, - clk, RSND_MOD_DVC, i); + clk, NULL, RSND_MOD_DVC, i); if (ret) goto rsnd_dvc_probe_done; =20 diff --git a/sound/soc/renesas/rcar/mix.c b/sound/soc/renesas/rcar/mix.c index aea74e703305..566e9b2a488c 100644 --- a/sound/soc/renesas/rcar/mix.c +++ b/sound/soc/renesas/rcar/mix.c @@ -328,7 +328,7 @@ int rsnd_mix_probe(struct rsnd_priv *priv) } =20 ret =3D rsnd_mod_init(priv, rsnd_mod_get(mix), &rsnd_mix_ops, - clk, RSND_MOD_MIX, i); + clk, NULL, RSND_MOD_MIX, i); if (ret) goto rsnd_mix_probe_done; =20 diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h index 04c70690f7a2..cd7e7df62298 100644 --- a/sound/soc/renesas/rcar/rsnd.h +++ b/sound/soc/renesas/rcar/rsnd.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -353,6 +354,7 @@ struct rsnd_mod { struct rsnd_mod_ops *ops; struct rsnd_priv *priv; struct clk *clk; + struct reset_control *rstc; u32 status; }; /* @@ -420,6 +422,7 @@ int rsnd_mod_init(struct rsnd_priv *priv, struct rsnd_mod *mod, struct rsnd_mod_ops *ops, struct clk *clk, + struct reset_control *rstc, enum rsnd_mod_type type, int id); void rsnd_mod_quit(struct rsnd_mod *mod); diff --git a/sound/soc/renesas/rcar/src.c b/sound/soc/renesas/rcar/src.c index 6a3dbc84f474..8b58cc20e7a8 100644 --- a/sound/soc/renesas/rcar/src.c +++ b/sound/soc/renesas/rcar/src.c @@ -766,7 +766,7 @@ int rsnd_src_probe(struct rsnd_priv *priv) } =20 ret =3D rsnd_mod_init(priv, rsnd_mod_get(src), - &rsnd_src_ops, clk, RSND_MOD_SRC, i); + &rsnd_src_ops, clk, NULL, RSND_MOD_SRC, i); if (ret) goto rsnd_src_probe_done; =20 diff --git a/sound/soc/renesas/rcar/ssi.c b/sound/soc/renesas/rcar/ssi.c index 0420041e282c..c06cebb36170 100644 --- a/sound/soc/renesas/rcar/ssi.c +++ b/sound/soc/renesas/rcar/ssi.c @@ -1225,7 +1225,7 @@ int rsnd_ssi_probe(struct rsnd_priv *priv) ops =3D &rsnd_ssi_dma_ops; =20 ret =3D rsnd_mod_init(priv, rsnd_mod_get(ssi), ops, clk, - RSND_MOD_SSI, i); + NULL, RSND_MOD_SSI, i); if (ret) goto rsnd_ssi_probe_done; =20 diff --git a/sound/soc/renesas/rcar/ssiu.c b/sound/soc/renesas/rcar/ssiu.c index 244fb833292a..0cfa84fe5ea8 100644 --- a/sound/soc/renesas/rcar/ssiu.c +++ b/sound/soc/renesas/rcar/ssiu.c @@ -586,7 +586,7 @@ int rsnd_ssiu_probe(struct rsnd_priv *priv) } =20 ret =3D rsnd_mod_init(priv, rsnd_mod_get(ssiu), - ops, NULL, RSND_MOD_SSIU, i); + ops, NULL, NULL, RSND_MOD_SSIU, i); if (ret) return ret; } --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F1EAE3033DC; Thu, 19 Mar 2026 15:56:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935772; cv=none; b=FeGgj0W202hg0BgBWEIr2Cl6ajKx8ZIh02edzPg2ILd09Rtjy31HSRzaEOZUEtjX50V4BVIPBpHtr3/lGpEzjWkpoH+Pn75FYsFojujwZ7J3Stimij/fTVyt1ND2qxOyP8wS4Ts4dNdPPQBhyu8tgV0qVZtAmJvbzwIB228exAw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935772; c=relaxed/simple; bh=ZWOReKKyPMl6xUpd3s80FsY+otBkxyOfAxaFxYC+lJg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CkVwV5cnHco5f5HWuxaMwVjut/Z2JRfXRUegOGvfJBKKZTh+BFsOcVf6BftpjHIrg6n7T5g6M8i6/bIyPWoC6aSp/h8uFv3HS+W2P74D/2eKrnVAZ3wKorN1hpPlnwYhagdlUrPFq/IneqvHROzxOXwhU8k4b1nA+/2OjpQIQtU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: lmuOayNCSY6M06bTV0tvEA== X-CSE-MsgGUID: crrVY76EQ2KXb0DmZYmXEw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:56:09 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C23A9401B307; Fri, 20 Mar 2026 00:56:00 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 09/22] ASoC: rsnd: Add RZ/G3E SoC probing and register map Date: Thu, 19 Mar 2026 16:53:21 +0100 Message-ID: <20260319155334.51278-10-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RZ/G3E audio subsystem has a different register layout compared to R-Car Gen2/Gen3/Gen4, as described below: - Different base address organization (SCU, ADG, SSIU, SSI as separate regions accessed by name) - Additional registers: AUDIO_CLK_SEL3, SSI_MODE3, SSI_CONTROL2 - Different register offsets within each region Add RZ/G3E SoC's audio subsystem register layouts and probe support. Signed-off-by: John Madieu --- sound/soc/renesas/rcar/core.c | 1 + sound/soc/renesas/rcar/gen.c | 184 ++++++++++++++++++++++++++++++++++ sound/soc/renesas/rcar/rsnd.h | 10 ++ 3 files changed, 195 insertions(+) diff --git a/sound/soc/renesas/rcar/core.c b/sound/soc/renesas/rcar/core.c index 6de576736507..86b2e9d06f9b 100644 --- a/sound/soc/renesas/rcar/core.c +++ b/sound/soc/renesas/rcar/core.c @@ -107,6 +107,7 @@ static const struct of_device_id rsnd_of_match[] =3D { { .compatible =3D "renesas,rcar_sound-gen4", .data =3D (void *)RSND_GEN4 = }, /* Special Handling */ { .compatible =3D "renesas,rcar_sound-r8a77990", .data =3D (void *)(RSND_= GEN3 | RSND_SOC_E) }, + { .compatible =3D "renesas,rcar_sound-r9a09g047", .data =3D (void *)RSND_= RZG3E }, {}, }; MODULE_DEVICE_TABLE(of, rsnd_of_match); diff --git a/sound/soc/renesas/rcar/gen.c b/sound/soc/renesas/rcar/gen.c index d1f20cde66be..789a14113f1b 100644 --- a/sound/soc/renesas/rcar/gen.c +++ b/sound/soc/renesas/rcar/gen.c @@ -464,6 +464,188 @@ static int rsnd_gen1_probe(struct rsnd_priv *priv) return ret_adg | ret_ssi; } =20 +/* + * RZ/G3E Generation + */ +static int rsnd_rzg3e_probe(struct rsnd_priv *priv) +{ + static const struct rsnd_regmap_field_conf conf_ssiu[] =3D { + RSND_GEN_S_REG(SSI_MODE1, 0x804), + RSND_GEN_S_REG(SSI_MODE2, 0x808), + RSND_GEN_S_REG(SSI_MODE3, 0x80c), + RSND_GEN_S_REG(SSI_CONTROL, 0x810), + RSND_GEN_S_REG(SSI_CONTROL2, 0x814), + RSND_GEN_S_REG(SSI_SYS_STATUS0, 0x840), + RSND_GEN_S_REG(SSI_SYS_STATUS1, 0x844), + RSND_GEN_S_REG(SSI_SYS_STATUS2, 0x848), + RSND_GEN_S_REG(SSI_SYS_STATUS3, 0x84c), + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE0, 0x850), + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE1, 0x854), + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE2, 0x858), + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE3, 0x85c), + RSND_GEN_M_REG(SSI_BUSIF0_MODE, 0x0, 0x80), + RSND_GEN_M_REG(SSI_BUSIF0_ADINR, 0x4, 0x80), + RSND_GEN_M_REG(SSI_BUSIF0_DALIGN, 0x8, 0x80), + RSND_GEN_M_REG(SSI_BUSIF1_MODE, 0x20, 0x80), + RSND_GEN_M_REG(SSI_BUSIF1_ADINR, 0x24, 0x80), + RSND_GEN_M_REG(SSI_BUSIF1_DALIGN, 0x28, 0x80), + RSND_GEN_M_REG(SSI_BUSIF2_MODE, 0x40, 0x80), + RSND_GEN_M_REG(SSI_BUSIF2_ADINR, 0x44, 0x80), + RSND_GEN_M_REG(SSI_BUSIF2_DALIGN, 0x48, 0x80), + RSND_GEN_M_REG(SSI_BUSIF3_MODE, 0x60, 0x80), + RSND_GEN_M_REG(SSI_BUSIF3_ADINR, 0x64, 0x80), + RSND_GEN_M_REG(SSI_BUSIF3_DALIGN, 0x68, 0x80), + RSND_GEN_M_REG(SSI_MODE, 0xc, 0x80), + RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80), + RSND_GEN_M_REG(SSI_INT_ENABLE, 0x18, 0x80), + RSND_GEN_S_REG(SSI9_BUSIF0_MODE, 0x480), + RSND_GEN_S_REG(SSI9_BUSIF0_ADINR, 0x484), + RSND_GEN_S_REG(SSI9_BUSIF0_DALIGN, 0x488), + RSND_GEN_S_REG(SSI9_BUSIF1_MODE, 0x4a0), + RSND_GEN_S_REG(SSI9_BUSIF1_ADINR, 0x4a4), + RSND_GEN_S_REG(SSI9_BUSIF1_DALIGN, 0x4a8), + RSND_GEN_S_REG(SSI9_BUSIF2_MODE, 0x4c0), + RSND_GEN_S_REG(SSI9_BUSIF2_ADINR, 0x4c4), + RSND_GEN_S_REG(SSI9_BUSIF2_DALIGN, 0x4c8), + RSND_GEN_S_REG(SSI9_BUSIF3_MODE, 0x4e0), + RSND_GEN_S_REG(SSI9_BUSIF3_ADINR, 0x4e4), + RSND_GEN_S_REG(SSI9_BUSIF3_DALIGN, 0x4e8), + }; + static const struct rsnd_regmap_field_conf conf_scu[] =3D { + RSND_GEN_M_REG(SRC_I_BUSIF_MODE, 0x0, 0x20), + RSND_GEN_M_REG(SRC_O_BUSIF_MODE, 0x4, 0x20), + RSND_GEN_M_REG(SRC_BUSIF_DALIGN, 0x8, 0x20), + RSND_GEN_M_REG(SRC_ROUTE_MODE0, 0xc, 0x20), + RSND_GEN_M_REG(SRC_CTRL, 0x10, 0x20), + RSND_GEN_M_REG(SRC_INT_ENABLE0, 0x18, 0x20), + RSND_GEN_M_REG(CMD_BUSIF_MODE, 0x184, 0x20), + RSND_GEN_M_REG(CMD_BUSIF_DALIGN, 0x188, 0x20), + RSND_GEN_M_REG(CMD_ROUTE_SLCT, 0x18c, 0x20), + RSND_GEN_M_REG(CMD_CTRL, 0x190, 0x20), + RSND_GEN_S_REG(SCU_SYS_STATUS0, 0x1c8), + RSND_GEN_S_REG(SCU_SYS_INT_EN0, 0x1cc), + RSND_GEN_S_REG(SCU_SYS_STATUS1, 0x1d0), + RSND_GEN_S_REG(SCU_SYS_INT_EN1, 0x1d4), + RSND_GEN_M_REG(SRC_SWRSR, 0x200, 0x40), + RSND_GEN_M_REG(SRC_SRCIR, 0x204, 0x40), + RSND_GEN_M_REG(SRC_ADINR, 0x214, 0x40), + RSND_GEN_M_REG(SRC_IFSCR, 0x21c, 0x40), + RSND_GEN_M_REG(SRC_IFSVR, 0x220, 0x40), + RSND_GEN_M_REG(SRC_SRCCR, 0x224, 0x40), + RSND_GEN_M_REG(SRC_BSDSR, 0x22c, 0x40), + RSND_GEN_M_REG(SRC_BSISR, 0x238, 0x40), + RSND_GEN_M_REG(CTU_SWRSR, 0x500, 0x100), + RSND_GEN_M_REG(CTU_CTUIR, 0x504, 0x100), + RSND_GEN_M_REG(CTU_ADINR, 0x508, 0x100), + RSND_GEN_M_REG(CTU_CPMDR, 0x510, 0x100), + RSND_GEN_M_REG(CTU_SCMDR, 0x514, 0x100), + RSND_GEN_M_REG(CTU_SV00R, 0x518, 0x100), + RSND_GEN_M_REG(CTU_SV01R, 0x51c, 0x100), + RSND_GEN_M_REG(CTU_SV02R, 0x520, 0x100), + RSND_GEN_M_REG(CTU_SV03R, 0x524, 0x100), + RSND_GEN_M_REG(CTU_SV04R, 0x528, 0x100), + RSND_GEN_M_REG(CTU_SV05R, 0x52c, 0x100), + RSND_GEN_M_REG(CTU_SV06R, 0x530, 0x100), + RSND_GEN_M_REG(CTU_SV07R, 0x534, 0x100), + RSND_GEN_M_REG(CTU_SV10R, 0x538, 0x100), + RSND_GEN_M_REG(CTU_SV11R, 0x53c, 0x100), + RSND_GEN_M_REG(CTU_SV12R, 0x540, 0x100), + RSND_GEN_M_REG(CTU_SV13R, 0x544, 0x100), + RSND_GEN_M_REG(CTU_SV14R, 0x548, 0x100), + RSND_GEN_M_REG(CTU_SV15R, 0x54c, 0x100), + RSND_GEN_M_REG(CTU_SV16R, 0x550, 0x100), + RSND_GEN_M_REG(CTU_SV17R, 0x554, 0x100), + RSND_GEN_M_REG(CTU_SV20R, 0x558, 0x100), + RSND_GEN_M_REG(CTU_SV21R, 0x55c, 0x100), + RSND_GEN_M_REG(CTU_SV22R, 0x560, 0x100), + RSND_GEN_M_REG(CTU_SV23R, 0x564, 0x100), + RSND_GEN_M_REG(CTU_SV24R, 0x568, 0x100), + RSND_GEN_M_REG(CTU_SV25R, 0x56c, 0x100), + RSND_GEN_M_REG(CTU_SV26R, 0x570, 0x100), + RSND_GEN_M_REG(CTU_SV27R, 0x574, 0x100), + RSND_GEN_M_REG(CTU_SV30R, 0x578, 0x100), + RSND_GEN_M_REG(CTU_SV31R, 0x57c, 0x100), + RSND_GEN_M_REG(CTU_SV32R, 0x580, 0x100), + RSND_GEN_M_REG(CTU_SV33R, 0x584, 0x100), + RSND_GEN_M_REG(CTU_SV34R, 0x588, 0x100), + RSND_GEN_M_REG(CTU_SV35R, 0x58c, 0x100), + RSND_GEN_M_REG(CTU_SV36R, 0x590, 0x100), + RSND_GEN_M_REG(CTU_SV37R, 0x594, 0x100), + RSND_GEN_M_REG(MIX_SWRSR, 0xd00, 0x40), + RSND_GEN_M_REG(MIX_MIXIR, 0xd04, 0x40), + RSND_GEN_M_REG(MIX_ADINR, 0xd08, 0x40), + RSND_GEN_M_REG(MIX_MIXMR, 0xd10, 0x40), + RSND_GEN_M_REG(MIX_MVPDR, 0xd14, 0x40), + RSND_GEN_M_REG(MIX_MDBAR, 0xd18, 0x40), + RSND_GEN_M_REG(MIX_MDBBR, 0xd1c, 0x40), + RSND_GEN_M_REG(MIX_MDBCR, 0xd20, 0x40), + RSND_GEN_M_REG(MIX_MDBDR, 0xd24, 0x40), + RSND_GEN_M_REG(MIX_MDBER, 0xd28, 0x40), + RSND_GEN_M_REG(DVC_SWRSR, 0xe00, 0x100), + RSND_GEN_M_REG(DVC_DVUIR, 0xe04, 0x100), + RSND_GEN_M_REG(DVC_ADINR, 0xe08, 0x100), + RSND_GEN_M_REG(DVC_DVUCR, 0xe10, 0x100), + RSND_GEN_M_REG(DVC_ZCMCR, 0xe14, 0x100), + RSND_GEN_M_REG(DVC_VRCTR, 0xe18, 0x100), + RSND_GEN_M_REG(DVC_VRPDR, 0xe1c, 0x100), + RSND_GEN_M_REG(DVC_VRDBR, 0xe20, 0x100), + RSND_GEN_M_REG(DVC_VOL0R, 0xe28, 0x100), + RSND_GEN_M_REG(DVC_VOL1R, 0xe2c, 0x100), + RSND_GEN_M_REG(DVC_VOL2R, 0xe30, 0x100), + RSND_GEN_M_REG(DVC_VOL3R, 0xe34, 0x100), + RSND_GEN_M_REG(DVC_VOL4R, 0xe38, 0x100), + RSND_GEN_M_REG(DVC_VOL5R, 0xe3c, 0x100), + RSND_GEN_M_REG(DVC_VOL6R, 0xe40, 0x100), + RSND_GEN_M_REG(DVC_VOL7R, 0xe44, 0x100), + RSND_GEN_M_REG(DVC_DVUER, 0xe48, 0x100), + }; + static const struct rsnd_regmap_field_conf conf_adg[] =3D { + RSND_GEN_S_REG(BRRA, 0x00), + RSND_GEN_S_REG(BRRB, 0x04), + RSND_GEN_S_REG(BRGCKR, 0x08), + RSND_GEN_S_REG(AUDIO_CLK_SEL0, 0x0c), + RSND_GEN_S_REG(AUDIO_CLK_SEL1, 0x10), + RSND_GEN_S_REG(AUDIO_CLK_SEL2, 0x14), + RSND_GEN_S_REG(AUDIO_CLK_SEL3, 0x18), + RSND_GEN_S_REG(DIV_EN, 0x30), + RSND_GEN_S_REG(SRCIN_TIMSEL0, 0x34), + RSND_GEN_S_REG(SRCIN_TIMSEL1, 0x38), + RSND_GEN_S_REG(SRCIN_TIMSEL2, 0x3c), + RSND_GEN_S_REG(SRCIN_TIMSEL3, 0x40), + RSND_GEN_S_REG(SRCIN_TIMSEL4, 0x44), + RSND_GEN_S_REG(SRCOUT_TIMSEL0, 0x48), + RSND_GEN_S_REG(SRCOUT_TIMSEL1, 0x4c), + RSND_GEN_S_REG(SRCOUT_TIMSEL2, 0x50), + RSND_GEN_S_REG(SRCOUT_TIMSEL3, 0x54), + RSND_GEN_S_REG(SRCOUT_TIMSEL4, 0x58), + RSND_GEN_S_REG(CMDOUT_TIMSEL, 0x5c), + }; + static const struct rsnd_regmap_field_conf conf_ssi[] =3D { + RSND_GEN_M_REG(SSICR, 0x00, 0x40), + RSND_GEN_M_REG(SSISR, 0x04, 0x40), + RSND_GEN_M_REG(SSIWSR, 0x20, 0x40), + }; + int ret; + + ret =3D rsnd_gen_regmap_init(priv, 10, RSND_RZG3E_SCU, + "scu", conf_scu); + if (ret < 0) + return ret; + + ret =3D rsnd_gen_regmap_init(priv, 10, RSND_RZG3E_ADG, + "adg", conf_adg); + if (ret < 0) + return ret; + + ret =3D rsnd_gen_regmap_init(priv, 10, RSND_RZG3E_SSIU, + "ssiu", conf_ssiu); + if (ret < 0) + return ret; + + return rsnd_gen_regmap_init(priv, 10, RSND_RZG3E_SSI, + "ssi", conf_ssi); +} + /* * Gen */ @@ -487,6 +669,8 @@ int rsnd_gen_probe(struct rsnd_priv *priv) ret =3D rsnd_gen2_probe(priv); else if (rsnd_is_gen4(priv)) ret =3D rsnd_gen4_probe(priv); + else if (rsnd_is_rzg3e(priv)) + ret =3D rsnd_rzg3e_probe(priv); =20 if (ret < 0) dev_err(dev, "unknown generation R-Car sound device\n"); diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h index cd7e7df62298..173fe475b7f8 100644 --- a/sound/soc/renesas/rcar/rsnd.h +++ b/sound/soc/renesas/rcar/rsnd.h @@ -26,6 +26,11 @@ #define RSND_BASE_SSIU 2 #define RSND_BASE_SCU 3 // for Gen2/Gen3 #define RSND_BASE_SDMC 3 // for Gen4 reuse + +#define RSND_RZG3E_SCU 0 +#define RSND_RZG3E_ADG 1 +#define RSND_RZG3E_SSIU 2 +#define RSND_RZG3E_SSI 3 #define RSND_BASE_MAX 4 =20 /* @@ -143,13 +148,16 @@ enum rsnd_reg { AUDIO_CLK_SEL0, AUDIO_CLK_SEL1, AUDIO_CLK_SEL2, + AUDIO_CLK_SEL3, =20 /* SSIU */ SSI_MODE, SSI_MODE0, SSI_MODE1, SSI_MODE2, + SSI_MODE3, SSI_CONTROL, + SSI_CONTROL2, SSI_CTRL, SSI_BUSIF0_MODE, SSI_BUSIF1_MODE, @@ -627,6 +635,7 @@ struct rsnd_priv { #define RSND_GEN2 (2 << 0) #define RSND_GEN3 (3 << 0) #define RSND_GEN4 (4 << 0) +#define RSND_RZG3E (5 << 0) #define RSND_SOC_MASK (0xFF << 4) #define RSND_SOC_E (1 << 4) /* E1/E2/E3 */ =20 @@ -708,6 +717,7 @@ struct rsnd_priv { #define rsnd_is_gen3_e3(priv) (((priv)->flags & \ (RSND_GEN_MASK | RSND_SOC_MASK)) =3D=3D \ (RSND_GEN3 | RSND_SOC_E)) +#define rsnd_is_rzg3e(priv) (((priv)->flags & RSND_GEN_MASK) =3D=3D RSND_R= ZG3E) =20 #define rsnd_flags_has(p, f) ((p)->flags & (f)) #define rsnd_flags_set(p, f) ((p)->flags |=3D (f)) --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1B62C3EBF05; Thu, 19 Mar 2026 15:56:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935781; cv=none; b=DIZw1cb4ytuK5Odkh9mukeBzcmdZcLFcoPuIGDkfqYOwpr80aVuCg2wsoffsKtZREzq8Ew5/6DSGfoRCU+8AeVorlfY3Zd2lo74FMIi6UID5mi348UZP8J/dDzlHj8EEX+G8FrmuFVFo6nsBRQP9x4eI0kJyZi3tGEojuTaMwgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935781; c=relaxed/simple; bh=YaT1vm3ZGZQJADPdtO3h5jlr2l0NVkxzr+E0zGp10+4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E4Ayao29RqUo6/culptaG85wrkxmEelww2q6aPXKMMHvAsSXp7cO3oRScNtQ197b7cARAxfbkvLq6u/C3vFZKZ+WF7Ad31jAOsEe+F1StAGVSgoJ0j7IBR1Rz3j0JeVhvmzg9zkyY7FvCMfehLm7WME66qIW5iDcMCK27lssiPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 9f3zlsATTEme95ClzlDzQw== X-CSE-MsgGUID: OoIBrNMxQAK+fz3fhjmBDA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:56:18 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id F26DF401B307; Fri, 20 Mar 2026 00:56:09 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 10/22] ASoC: rsnd: Add DMA support infrastructure for RZ/G3E Date: Thu, 19 Mar 2026 16:53:22 +0100 Message-ID: <20260319155334.51278-11-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RZ/G3E has different DMA register base addresses and offset calculations compared to R-Car platforms, and requires additional audmac-pp clock and reset lines for Audio DMAC operation. Add RZ/G3E-specific DMA address macros and audmac-pp clock/reset support using optional APIs to remain transparent to other platforms. Signed-off-by: John Madieu --- sound/soc/renesas/rcar/core.c | 2 +- sound/soc/renesas/rcar/dma.c | 171 +++++++++++++++++++++++++++------- sound/soc/renesas/rcar/rsnd.h | 12 +++ 3 files changed, 152 insertions(+), 33 deletions(-) diff --git a/sound/soc/renesas/rcar/core.c b/sound/soc/renesas/rcar/core.c index 86b2e9d06f9b..2f9c32c647a6 100644 --- a/sound/soc/renesas/rcar/core.c +++ b/sound/soc/renesas/rcar/core.c @@ -615,7 +615,7 @@ int rsnd_dai_connect(struct rsnd_mod *mod, return 0; } =20 -static void rsnd_dai_disconnect(struct rsnd_mod *mod, +void rsnd_dai_disconnect(struct rsnd_mod *mod, struct rsnd_dai_stream *io, enum rsnd_mod_type type) { diff --git a/sound/soc/renesas/rcar/dma.c b/sound/soc/renesas/rcar/dma.c index 68c859897e68..d3123ae3b402 100644 --- a/sound/soc/renesas/rcar/dma.c +++ b/sound/soc/renesas/rcar/dma.c @@ -496,24 +496,71 @@ static struct rsnd_mod_ops rsnd_dmapp_ops =3D { * SSIU: 0xec541000 / 0xec100000 / 0xec100000 / 0xec400000 / 0xec400000 * SCU : 0xec500000 / 0xec000000 / 0xec004000 / 0xec300000 / 0xec304000 * CMD : 0xec500000 / / 0xec008000 0xec308000 + * + * ex) G3E case + * mod / DMAC in / DMAC out / DMAC PP in / DMAC pp out + * SSI : 0x13C31000 / 0x13C40000 / 0x13C40000 + * SSIU: 0x13C31000 / 0x13C40000 / 0x13C40000 / 0xEC400000 / 0xEC400000 + * SCU : 0x13C00000 / 0x13C10000 / 0x13C14000 / 0xEC300000 / 0xEC304000 + * CMD : 0x13C00000 / / 0x13C18000 0xEC308000 */ -#define RDMA_SSI_I_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0x8) -#define RDMA_SSI_O_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0xc) =20 -#define RDMA_SSIU_I_N(addr, i, j) (addr ##_reg - 0x00441000 + (0x1000 * (i= )) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) * ((j= ) / 4))) -#define RDMA_SSIU_O_N(addr, i, j) RDMA_SSIU_I_N(addr, i, j) +/* RZ/G3E DMA address macros */ +#define RDMA_SSI_I_N_G3E(addr, i) (addr ##_reg + 0x0000F000 + (0x1000 * i)) +#define RDMA_SSI_O_N_G3E(addr, i) (addr ##_reg + 0x0000F000 + (0x1000 * i)) + +#define RDMA_SSIU_I_N_G3E(addr, i, j) (addr ##_reg + 0x0000F000 + (0x1000 = * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) *= ((j) / 4))) +#define RDMA_SSIU_O_N_G3E(addr, i, j) RDMA_SSIU_I_N_G3E(addr, i, j) + +#define RDMA_SSIU_I_P_G3E(addr, i, j) (addr ##_reg + 0xD87CF000 + (0x1000 = * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) *= ((j) / 4))) +#define RDMA_SSIU_O_P_G3E(addr, i, j) RDMA_SSIU_I_P_G3E(addr, i, j) + +#define RDMA_SRC_I_N_G3E(addr, i) (addr ##_reg + 0x00010000 + (0x400 * i)) +#define RDMA_SRC_O_N_G3E(addr, i) (addr ##_reg + 0x00014000 + (0x400 * i)) + +#define RDMA_SRC_I_P_G3E(addr, i) (addr ##_reg + 0xD8700000 + (0x400 * i)) +#define RDMA_SRC_O_P_G3E(addr, i) (addr ##_reg + 0xD8704000 + (0x400 * i)) + +#define RDMA_CMD_O_N_G3E(addr, i) (addr ##_reg + 0x00018000 + (0x400 * i)) +#define RDMA_CMD_O_P_G3E(addr, i) (addr ##_reg + 0xD8708000 + (0x400 * i)) + +/* R-Car DMA address macros */ +#define RDMA_SSI_I_N_RCAR(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) = + 0x8) +#define RDMA_SSI_O_N_RCAR(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) = + 0xc) =20 -#define RDMA_SSIU_I_P(addr, i, j) (addr ##_reg - 0x00141000 + (0x1000 * (i= )) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) * ((j= ) / 4))) -#define RDMA_SSIU_O_P(addr, i, j) RDMA_SSIU_I_P(addr, i, j) +#define RDMA_SSIU_I_N_RCAR(addr, i, j) (addr ##_reg - 0x00441000 + (0x1000= * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) = * ((j) / 4))) +#define RDMA_SSIU_O_N_RCAR(addr, i, j) RDMA_SSIU_I_N_RCAR(addr, i, j) =20 -#define RDMA_SRC_I_N(addr, i) (addr ##_reg - 0x00500000 + (0x400 * i)) -#define RDMA_SRC_O_N(addr, i) (addr ##_reg - 0x004fc000 + (0x400 * i)) +#define RDMA_SSIU_I_P_RCAR(addr, i, j) (addr ##_reg - 0x00141000 + (0x1000= * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) = * ((j) / 4))) +#define RDMA_SSIU_O_P_RCAR(addr, i, j) RDMA_SSIU_I_N_RCAR(addr, i, j) =20 -#define RDMA_SRC_I_P(addr, i) (addr ##_reg - 0x00200000 + (0x400 * i)) -#define RDMA_SRC_O_P(addr, i) (addr ##_reg - 0x001fc000 + (0x400 * i)) +#define RDMA_SRC_I_N_RCAR(addr, i) (addr ##_reg - 0x00500000 + (0x400 * i)) +#define RDMA_SRC_O_N_RCAR(addr, i) (addr ##_reg - 0x004fc000 + (0x400 * i)) =20 -#define RDMA_CMD_O_N(addr, i) (addr ##_reg - 0x004f8000 + (0x400 * i)) -#define RDMA_CMD_O_P(addr, i) (addr ##_reg - 0x001f8000 + (0x400 * i)) +#define RDMA_SRC_I_P_RCAR(addr, i) (addr ##_reg - 0x00200000 + (0x400 * i)) +#define RDMA_SRC_O_P_RCAR(addr, i) (addr ##_reg - 0x001fc000 + (0x400 * i)) + +#define RDMA_CMD_O_N_RCAR(addr, i) (addr ##_reg - 0x004f8000 + (0x400 * i)) +#define RDMA_CMD_O_P_RCAR(addr, i) (addr ##_reg - 0x001f8000 + (0x400 * i)) + +/* Platform-agnostic address macros */ +#define RDMA_SSI_I_N(p, addr, i) rsnd_is_rzg3e(p) ? RDMA_SSI_I_N_G3E(addr,= i) : RDMA_SSI_I_N_RCAR(addr, i) +#define RDMA_SSI_O_N(p, addr, i) rsnd_is_rzg3e(p) ? RDMA_SSI_O_N_G3E(addr,= i) : RDMA_SSI_O_N_RCAR(addr, i) + +#define RDMA_SSIU_I_N(p, addr, i, j) rsnd_is_rzg3e(p) ? RDMA_SSIU_I_N_G3E(= addr, i, j) : RDMA_SSIU_I_N_RCAR(addr, i, j) +#define RDMA_SSIU_O_N(p, addr, i, j) rsnd_is_rzg3e(p) ? RDMA_SSIU_O_N_G3E(= addr, i, j) : RDMA_SSIU_O_N_RCAR(addr, i, j) + +#define RDMA_SSIU_I_P(p, addr, i, j) rsnd_is_rzg3e(p) ? RDMA_SSIU_I_P_G3E(= addr, i, j) : RDMA_SSIU_I_P_RCAR(addr, i, j) +#define RDMA_SSIU_O_P(p, addr, i, j) rsnd_is_rzg3e(p) ? RDMA_SSIU_O_P_G3E(= addr, i, j) : RDMA_SSIU_O_P_RCAR(addr, i, j) + +#define RDMA_SRC_I_N(p, addr, i) rsnd_is_rzg3e(p) ? RDMA_SRC_I_N_G3E(addr,= i) : RDMA_SRC_I_N_RCAR(addr, i) +#define RDMA_SRC_O_N(p, addr, i) rsnd_is_rzg3e(p) ? RDMA_SRC_O_N_G3E(addr,= i) : RDMA_SRC_O_N_RCAR(addr, i) + +#define RDMA_SRC_I_P(p, addr, i) rsnd_is_rzg3e(p) ? RDMA_SRC_I_P_G3E(addr,= i) : RDMA_SRC_I_P_RCAR(addr, i) +#define RDMA_SRC_O_P(p, addr, i) rsnd_is_rzg3e(p) ? RDMA_SRC_O_P_G3E(addr,= i) : RDMA_SRC_O_P_RCAR(addr, i) + +#define RDMA_CMD_O_N(p, addr, i) rsnd_is_rzg3e(p) ? RDMA_CMD_O_N_G3E(addr,= i) : RDMA_CMD_O_N_RCAR(addr, i) +#define RDMA_CMD_O_P(p, addr, i) rsnd_is_rzg3e(p) ? RDMA_CMD_O_P_G3E(addr,= i) : RDMA_CMD_O_P_RCAR(addr, i) =20 static dma_addr_t rsnd_gen2_dma_addr(struct rsnd_dai_stream *io, @@ -522,8 +569,8 @@ rsnd_gen2_dma_addr(struct rsnd_dai_stream *io, { struct rsnd_priv *priv =3D rsnd_io_to_priv(io); struct device *dev =3D rsnd_priv_to_dev(priv); - phys_addr_t ssi_reg =3D rsnd_gen_get_phy_addr(priv, RSND_BASE_SSI); - phys_addr_t src_reg =3D rsnd_gen_get_phy_addr(priv, RSND_BASE_SCU); + phys_addr_t ssi_reg =3D rsnd_gen_get_phy_addr(priv, rsnd_is_rzg3e(priv) ?= RSND_RZG3E_SSI : RSND_BASE_SSI); + phys_addr_t src_reg =3D rsnd_gen_get_phy_addr(priv, rsnd_is_rzg3e(priv) ?= RSND_RZG3E_SCU : RSND_BASE_SCU); int is_ssi =3D !!(rsnd_io_to_mod_ssi(io) =3D=3D mod) || !!(rsnd_io_to_mod_ssiu(io) =3D=3D mod); int use_src =3D !!rsnd_io_to_mod_src(io); @@ -539,32 +586,32 @@ rsnd_gen2_dma_addr(struct rsnd_dai_stream *io, /* SRC */ /* Capture */ {{{ 0, 0 }, - { RDMA_SRC_O_N(src, id), RDMA_SRC_I_P(src, id) }, - { RDMA_CMD_O_N(src, id), RDMA_SRC_I_P(src, id) } }, + { RDMA_SRC_O_N(priv, src, id), RDMA_SRC_I_P(priv, src, id) }, + { RDMA_CMD_O_N(priv, src, id), RDMA_SRC_I_P(priv, src, id) } }, /* Playback */ {{ 0, 0, }, - { RDMA_SRC_O_P(src, id), RDMA_SRC_I_N(src, id) }, - { RDMA_CMD_O_P(src, id), RDMA_SRC_I_N(src, id) } } + { RDMA_SRC_O_P(priv, src, id), RDMA_SRC_I_N(priv, src, id) }, + { RDMA_CMD_O_P(priv, src, id), RDMA_SRC_I_N(priv, src, id) } } }, /* SSI */ /* Capture */ - {{{ RDMA_SSI_O_N(ssi, id), 0 }, - { RDMA_SSIU_O_P(ssi, id, busif), 0 }, - { RDMA_SSIU_O_P(ssi, id, busif), 0 } }, + {{{ RDMA_SSI_O_N(priv, ssi, id), 0 }, + { RDMA_SSIU_O_P(priv, ssi, id, busif), 0 }, + { RDMA_SSIU_O_P(priv, ssi, id, busif), 0 } }, /* Playback */ - {{ 0, RDMA_SSI_I_N(ssi, id) }, - { 0, RDMA_SSIU_I_P(ssi, id, busif) }, - { 0, RDMA_SSIU_I_P(ssi, id, busif) } } + {{ 0, RDMA_SSI_I_N(priv, ssi, id) }, + { 0, RDMA_SSIU_I_P(priv, ssi, id, busif) }, + { 0, RDMA_SSIU_I_P(priv, ssi, id, busif) } } }, /* SSIU */ /* Capture */ - {{{ RDMA_SSIU_O_N(ssi, id, busif), 0 }, - { RDMA_SSIU_O_P(ssi, id, busif), 0 }, - { RDMA_SSIU_O_P(ssi, id, busif), 0 } }, + {{{ RDMA_SSIU_O_N(priv, ssi, id, busif), 0 }, + { RDMA_SSIU_O_P(priv, ssi, id, busif), 0 }, + { RDMA_SSIU_O_P(priv, ssi, id, busif), 0 } }, /* Playback */ - {{ 0, RDMA_SSIU_I_N(ssi, id, busif) }, - { 0, RDMA_SSIU_I_P(ssi, id, busif) }, - { 0, RDMA_SSIU_I_P(ssi, id, busif) } } }, + {{ 0, RDMA_SSIU_I_N(priv, ssi, id, busif) }, + { 0, RDMA_SSIU_I_P(priv, ssi, id, busif) }, + { 0, RDMA_SSIU_I_P(priv, ssi, id, busif) } } }, }; =20 /* @@ -803,8 +850,12 @@ static int rsnd_dma_alloc(struct rsnd_dai_stream *io, = struct rsnd_mod *mod, =20 *dma_mod =3D rsnd_mod_get(dma); =20 - ret =3D rsnd_mod_init(priv, *dma_mod, ops, NULL, NULL, - type, dma_id); + /* + * Pass NULL for clock/reset - audmac_pp is managed globally in + * rsnd_dma_probe() and core.c suspend/resume, not per-DMA-module. + * See detailed explanation in rsnd_dma_probe(). + */ + ret =3D rsnd_mod_init(priv, *dma_mod, ops, NULL, NULL, type, dma_id); if (ret < 0) return ret; =20 @@ -838,6 +889,12 @@ int rsnd_dma_attach(struct rsnd_dai_stream *io, struct= rsnd_mod *mod, return rsnd_dai_connect(*dma_mod, io, (*dma_mod)->type); } =20 +void rsnd_dma_detach(struct rsnd_dai_stream *io, struct rsnd_mod *mod, + struct rsnd_mod **dma_mod) +{ + rsnd_dai_disconnect(*dma_mod, io, (*dma_mod)->type); +} + int rsnd_dma_probe(struct rsnd_priv *priv) { struct platform_device *pdev =3D rsnd_priv_to_pdev(priv); @@ -860,6 +917,56 @@ int rsnd_dma_probe(struct rsnd_priv *priv) return 0; /* it will be PIO mode */ } =20 + /* + * audmac_pp clock/reset management strategy: + * + * Unlike other modules (SSI, SRC, etc.) which have their own dedicated + * clocks, all DMA modules share the single audmac_pp clock/reset. + * Managing it per-stream or per-DMA-module causes + * reference count imbalances: + * + * - rsnd_mod_init() does clk_prepare_enable() then clk_disable(), + * leaving prepare_count=3D1 per module + * - With N DMA modules sharing the same clock handle, prepare_count=3DN + * - suspend does single clk_disable_unprepare() (-1) + * - resume does single clk_prepare_enable() (+1) + * - Result: prepare_count leaks on each suspend/resume cycle + * + * Per-stream management (iterating DMA modules in suspend/resume) is + * not worth the complexity: + * + * - No power benefit: audmac_pp is needed whenever ANY stream is + * active, and every stream uses DMA, so it's essentially always on + * - Architecture mismatch: DMA modules live in io->dma, not in a + * priv array -- no clean way to iterate like SSI/SRC/DVC + * - Shared handle problem: all DMA modules point to the same clock, + * so iterating would call clk_unprepare() N times on one clock + * - Would require manual refcounting ("enable on first stream, + * disable on last") -- reimplementing what clk framework does + * + * The correct approach is to treat audmac_pp as always-on infrastructure + * (same pattern as clk_adg), managed globally: + * - Probe: acquire + enable (via devm_clk_get_optional_enabled) + * - Suspend/Resume: toggle in core.c rsnd_suspend/rsnd_resume + * - Remove: devm cleanup + * - DMA modules: pass NULL clock/reset to rsnd_mod_init() + * + * Use devm variants that handle deassert/enable automatically. + * Order: reset deasserted first, then clock enabled. + */ + priv->rstc_audmac_pp =3D + devm_reset_control_get_optional_exclusive_deasserted(dev, "audmac_pp"); + if (IS_ERR(priv->rstc_audmac_pp)) { + return dev_err_probe(dev, PTR_ERR(priv->rstc_audmac_pp), + "failed to get audmac_pp reset\n"); + } + + priv->clk_audmac_pp =3D devm_clk_get_optional_enabled(dev, "audmac_pp"); + if (IS_ERR(priv->clk_audmac_pp)) { + return dev_err_probe(dev, PTR_ERR(priv->clk_audmac_pp), + "failed to get audmac_pp clock\n"); + } + /* for Gen4 doesn't have DMA-pp */ if (rsnd_is_gen4(priv)) goto audmapp_end; diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h index 173fe475b7f8..8f3637904884 100644 --- a/sound/soc/renesas/rcar/rsnd.h +++ b/sound/soc/renesas/rcar/rsnd.h @@ -271,6 +271,8 @@ u32 rsnd_get_busif_shift(struct rsnd_dai_stream *io, st= ruct rsnd_mod *mod); */ int rsnd_dma_attach(struct rsnd_dai_stream *io, struct rsnd_mod *mod, struct rsnd_mod **dma_mod); +void rsnd_dma_detach(struct rsnd_dai_stream *io, + struct rsnd_mod *mod, struct rsnd_mod **dma_mod); int rsnd_dma_probe(struct rsnd_priv *priv); struct dma_chan *rsnd_dma_request_channel(struct device_node *of_node, cha= r *name, struct rsnd_mod *mod, char *x); @@ -590,6 +592,9 @@ int rsnd_rdai_width_ctrl(struct rsnd_dai *rdai, int wid= th); int rsnd_dai_connect(struct rsnd_mod *mod, struct rsnd_dai_stream *io, enum rsnd_mod_type type); +void rsnd_dai_disconnect(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + enum rsnd_mod_type type); =20 /* * R-Car Gen1/Gen2 @@ -628,6 +633,13 @@ void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, str= uct seq_file *m); struct rsnd_priv { =20 struct platform_device *pdev; + + /* + * below value will be filled on rsnd_dma_probe() + */ + struct clk *clk_audmac_pp; + struct reset_control *rstc_audmac_pp; + spinlock_t lock; unsigned long flags; #define RSND_GEN_MASK (0xF << 0) --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7C3F13E9595; Thu, 19 Mar 2026 15:56:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935790; cv=none; b=RnYLk86SvUezRSn8SeJiXR4AvEg8+j2PwdKU/XMAI+ZYHlNkw7Jh2xkv0fukvS4WIcLUMUKvA4M2bLwEObwMOhyFOOmsS3Qzz7YSJiSs/TRyDut6g0yQd8wM5aVkC7bdUeruGiWjtErEs53lBxiv3O0PwumiQ/0hJoXNY+CfUbo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935790; c=relaxed/simple; bh=pxmwXqdfheRNmyRz29WVb8GdRzN1F9luVbETBgPCG8U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nIfe3x/Olnumq9crmcf3aXjkxFqJcIIBJjijzLqMIRVUeBe3HAaONq4NtcApjeyiXA3eM9zCyrBAXR2HliN/kjLdjE+pRZQnLp6ZbQHpcuF5BmC+N4eFWVpVosmzwrVIYGqTQkLaVPGc99jlmnc7NA9Dvbg1w6q6CTEUNnTrTiM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: zYrras1FTlOYwkS2lZaAYw== X-CSE-MsgGUID: 6utN6feGTsezMK4VWju+sA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:56:27 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E665F401B641; Fri, 20 Mar 2026 00:56:18 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 11/22] ASoC: rsnd: ssui: Add RZ/G3E SSIU BUSIF support Date: Thu, 19 Mar 2026 16:53:23 +0100 Message-ID: <20260319155334.51278-12-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the SSIU found on the Renesas RZ/G3E SoC, which provides a different BUSIF layout compared to earlier generations: - SSI0-SSI4: 4 BUSIF instances each (BUSIF0-3) - SSI5-SSI8: 1 BUSIF instance each (BUSIF0 only) - SSI9: 4 BUSIF instances (BUSIF0-3) - Total: 28 BUSIFs RZ/G3E also differs from Gen2/Gen3 implementations in that only two pairs of BUSIF error-status registers are available instead of four, and the SSI always operates in BUSIF mode with no PIO fallback. Rather than scattering SoC-specific checks across functional code, introduce two capability flags in the match data: - RSND_SSI_ALWAYS_BUSIF: the SSI has no PIO mode and always uses BUSIF. Used in rsnd_ssi_use_busif() and rsnd_ssiu_init() to skip SSI_MODE0 configuration. - RSND_SSIU_BUSIF_STATUS_COUNT_2: only two BUSIF error-status register pairs are present. Used in rsnd_ssiu_busif_err_irq_ctrl() and rsnd_ssiu_busif_err_status_clear() to limit register iteration. Future SoCs sharing these constraints can set the flags without requiring code changes. Signed-off-by: John Madieu --- sound/soc/renesas/rcar/core.c | 5 +++- sound/soc/renesas/rcar/rsnd.h | 3 +++ sound/soc/renesas/rcar/ssiu.c | 47 +++++++++++++++++++++-------------- 3 files changed, 36 insertions(+), 19 deletions(-) diff --git a/sound/soc/renesas/rcar/core.c b/sound/soc/renesas/rcar/core.c index 2f9c32c647a6..6a25580b9c6a 100644 --- a/sound/soc/renesas/rcar/core.c +++ b/sound/soc/renesas/rcar/core.c @@ -107,7 +107,9 @@ static const struct of_device_id rsnd_of_match[] =3D { { .compatible =3D "renesas,rcar_sound-gen4", .data =3D (void *)RSND_GEN4 = }, /* Special Handling */ { .compatible =3D "renesas,rcar_sound-r8a77990", .data =3D (void *)(RSND_= GEN3 | RSND_SOC_E) }, - { .compatible =3D "renesas,rcar_sound-r9a09g047", .data =3D (void *)RSND_= RZG3E }, + { .compatible =3D "renesas,rcar_sound-r9a09g047", .data =3D (void *)(RSND= _RZG3E | + RSND_SSI_ALWAYS_BUSIF | + RSND_SSIU_BUSIF_STATUS_COUNT_2) }, {}, }; MODULE_DEVICE_TABLE(of, rsnd_of_match); @@ -1960,6 +1962,7 @@ static int rsnd_probe(struct platform_device *pdev) =20 priv->pdev =3D pdev; priv->flags =3D (unsigned long)of_device_get_match_data(dev); + priv->ssiu_busif_count =3D rsnd_flags_has(priv, RSND_SSIU_BUSIF_STATUS_CO= UNT_2) ? 2 : 4; spin_lock_init(&priv->lock); =20 /* diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h index 8f3637904884..da377bca45a9 100644 --- a/sound/soc/renesas/rcar/rsnd.h +++ b/sound/soc/renesas/rcar/rsnd.h @@ -641,6 +641,7 @@ struct rsnd_priv { struct reset_control *rstc_audmac_pp; =20 spinlock_t lock; + unsigned int ssiu_busif_count; unsigned long flags; #define RSND_GEN_MASK (0xF << 0) #define RSND_GEN1 (1 << 0) @@ -650,6 +651,8 @@ struct rsnd_priv { #define RSND_RZG3E (5 << 0) #define RSND_SOC_MASK (0xFF << 4) #define RSND_SOC_E (1 << 4) /* E1/E2/E3 */ +#define RSND_SSI_ALWAYS_BUSIF BIT(12) /* SSI has no PIO mode, always uses = BUSIF */ +#define RSND_SSIU_BUSIF_STATUS_COUNT_2 BIT(13) /* Only 2 BUSIF error-statu= s register pairs */ =20 /* * below value will be filled on rsnd_gen_probe() diff --git a/sound/soc/renesas/rcar/ssiu.c b/sound/soc/renesas/rcar/ssiu.c index 0cfa84fe5ea8..f377d9414633 100644 --- a/sound/soc/renesas/rcar/ssiu.c +++ b/sound/soc/renesas/rcar/ssiu.c @@ -29,31 +29,32 @@ struct rsnd_ssiu { i++) =20 /* - * SSI Gen2 Gen3 Gen4 - * 0 BUSIF0-3 BUSIF0-7 BUSIF0-7 - * 1 BUSIF0-3 BUSIF0-7 - * 2 BUSIF0-3 BUSIF0-7 - * 3 BUSIF0 BUSIF0-7 - * 4 BUSIF0 BUSIF0-7 - * 5 BUSIF0 BUSIF0 - * 6 BUSIF0 BUSIF0 - * 7 BUSIF0 BUSIF0 - * 8 BUSIF0 BUSIF0 - * 9 BUSIF0-3 BUSIF0-7 - * total 22 52 8 + * SSI Gen2 Gen3 Gen4 RZ/G3E + * 0 BUSIF0-3 BUSIF0-7 BUSIF0-7 BUSIF0-3 + * 1 BUSIF0-3 BUSIF0-7 BUSIF0-3 + * 2 BUSIF0-3 BUSIF0-7 BUSIF0-3 + * 3 BUSIF0 BUSIF0-7 BUSIF0-3 + * 4 BUSIF0 BUSIF0-7 BUSIF0-3 + * 5 BUSIF0 BUSIF0 BUSIF0 + * 6 BUSIF0 BUSIF0 BUSIF0 + * 7 BUSIF0 BUSIF0 BUSIF0 + * 8 BUSIF0 BUSIF0 BUSIF0 + * 9 BUSIF0-3 BUSIF0-7 BUSIF0-3 + * total 22 52 8 28 */ static const int gen2_id[] =3D { 0, 4, 8, 12, 13, 14, 15, 16, 17, 18 }; static const int gen3_id[] =3D { 0, 8, 16, 24, 32, 40, 41, 42, 43, 44 }; static const int gen4_id[] =3D { 0 }; +static const int rzg3e_id[] =3D { 0, 4, 8, 12, 16, 20, 21, 22, 23, 24 }; =20 /* enable busif buffer over/under run interrupt. */ #define rsnd_ssiu_busif_err_irq_enable(mod) rsnd_ssiu_busif_err_irq_ctrl(= mod, 1) #define rsnd_ssiu_busif_err_irq_disable(mod) rsnd_ssiu_busif_err_irq_ctrl(= mod, 0) static void rsnd_ssiu_busif_err_irq_ctrl(struct rsnd_mod *mod, int enable) { + struct rsnd_priv *priv =3D rsnd_mod_to_priv(mod); int id =3D rsnd_mod_id(mod); int shift, offset; - int i; =20 switch (id) { case 0: @@ -72,7 +73,7 @@ static void rsnd_ssiu_busif_err_irq_ctrl(struct rsnd_mod = *mod, int enable) return; } =20 - for (i =3D 0; i < 4; i++) { + for (unsigned int i =3D 0; i < priv->ssiu_busif_count; i++) { enum rsnd_reg reg =3D SSI_SYS_INT_ENABLE((i * 2) + offset); u32 val =3D 0xf << (shift * 4); u32 sys_int_enable =3D rsnd_mod_read(mod, reg); @@ -87,10 +88,10 @@ static void rsnd_ssiu_busif_err_irq_ctrl(struct rsnd_mo= d *mod, int enable) =20 bool rsnd_ssiu_busif_err_status_clear(struct rsnd_mod *mod) { + struct rsnd_priv *priv =3D rsnd_mod_to_priv(mod); bool error =3D false; int id =3D rsnd_mod_id(mod); int shift, offset; - int i; =20 switch (id) { case 0: @@ -109,7 +110,7 @@ bool rsnd_ssiu_busif_err_status_clear(struct rsnd_mod *= mod) goto out; } =20 - for (i =3D 0; i < 4; i++) { + for (unsigned int i =3D 0; i < priv->ssiu_busif_count; i++) { u32 reg =3D SSI_SYS_STATUS(i * 2) + offset; u32 status =3D rsnd_mod_read(mod, reg); u32 val =3D 0xf << (shift * 4); @@ -160,7 +161,8 @@ static int rsnd_ssiu_init(struct rsnd_mod *mod, /* * SSI_MODE0 */ - rsnd_mod_bset(mod, SSI_MODE0, (1 << id), !use_busif << id); + if (!rsnd_is_rzg3e(priv)) + rsnd_mod_bset(mod, SSI_MODE0, (1 << id), !use_busif << id); =20 /* * SSI_MODE1 / SSI_MODE2 @@ -510,6 +512,7 @@ int rsnd_ssiu_probe(struct rsnd_priv *priv) { struct device *dev =3D rsnd_priv_to_dev(priv); struct device_node *node __free(device_node) =3D rsnd_ssiu_of_node(priv); + struct reset_control *rstc; struct rsnd_ssiu *ssiu; struct rsnd_mod_ops *ops; const int *list =3D NULL; @@ -558,12 +561,20 @@ int rsnd_ssiu_probe(struct rsnd_priv *priv) } else if (rsnd_is_gen4(priv)) { list =3D gen4_id; nr =3D ARRAY_SIZE(gen4_id); + } else if (rsnd_is_rzg3e(priv)) { + list =3D rzg3e_id; + nr =3D ARRAY_SIZE(rzg3e_id); } else { dev_err(dev, "unknown SSIU\n"); return -ENODEV; } } =20 + /* Acquire shared reset once for all SSIU modules */ + rstc =3D devm_reset_control_get_optional_shared(dev, "ssi-all"); + if (IS_ERR(rstc)) + rstc =3D NULL; + for_each_rsnd_ssiu(ssiu, priv, i) { int ret; =20 @@ -586,7 +597,7 @@ int rsnd_ssiu_probe(struct rsnd_priv *priv) } =20 ret =3D rsnd_mod_init(priv, rsnd_mod_get(ssiu), - ops, NULL, NULL, RSND_MOD_SSIU, i); + ops, NULL, rstc, RSND_MOD_SSIU, i); if (ret) return ret; } --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 373003E8C60; Thu, 19 Mar 2026 15:56:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935800; cv=none; b=JSNdUWiuRY6d2Xkbg373Xph3nrUzQga0tJ3M+sx3lq1U3mHHWki5K0Jn1VIFFrUxo9hJ6fYX9h+yfk9B1v0qcMXTTzdO1KqpuZXjB3Nxc9ZytgXwiJUgjeRenbjbN3JPKHmAWGW+orqgzCZF5tKenK2Mrbq79h7cFCubk6qtaMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935800; c=relaxed/simple; bh=UBOnLwm3GZOOJiBwqs7ZpyYoqYu152qMXe2ZhHRsgxc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GlPZGM4EuJ8iAmlzzcmqw/vN2b8BIvkR8xkCHAbkiQa0Qabs2+6skoTcwNzfzKRyIX5NAqmaFOD/zRQNuXQ4UbGZrUXWPk4wEu1irKO1HbhOpl8YOqSBQrrEj8ZjorxDMyraBMMfmqfUZx+gMRkrrDE2D3N/5ddZH6Exw12IBbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 0WIbw9C5QUujz3gxKdxtSQ== X-CSE-MsgGUID: yqDSHeGMQ0ybsMGFn8Ur0Q== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:56:37 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6B70D401B641; Fri, 20 Mar 2026 00:56:28 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 12/22] ASoC: rsnd: Update SSI for RZ/G3E support Date: Thu, 19 Mar 2026 16:53:24 +0100 Message-ID: <20260319155334.51278-13-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SSI support for the Renesas RZ/G3E SoC, which differs from earlier generations in several ways: - The SSI block always operates in BUSIF mode; RZ/G3E does not implement the SSITDR/SSIRDR registers used by R-Car Gen2/Gen3/Gen4 for direct SSI DMA. Consequently, all audio data must pass through BUSIF. - Each SSI instance has its own reset line, exposed using per-SSI names such as "ssi0", "ssi1", etc., rather than a single shared reset. To support these differences, update rsnd_ssi_use_busif() to always return 1 on RZ/G3E, ensuring that the driver consistently selects the BUSIF DMA path. Also update the reset acquisition logic to request the appropriate per-SSI reset controller based on the SSI instance name. Signed-off-by: John Madieu --- sound/soc/renesas/rcar/ssi.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/sound/soc/renesas/rcar/ssi.c b/sound/soc/renesas/rcar/ssi.c index c06cebb36170..e25a4dfae90c 100644 --- a/sound/soc/renesas/rcar/ssi.c +++ b/sound/soc/renesas/rcar/ssi.c @@ -123,8 +123,15 @@ int rsnd_ssi_use_busif(struct rsnd_dai_stream *io) { struct rsnd_mod *mod =3D rsnd_io_to_mod_ssi(io); struct rsnd_ssi *ssi =3D rsnd_mod_to_ssi(mod); + struct rsnd_priv *priv =3D rsnd_mod_to_priv(mod); int use_busif =3D 0; =20 + /* + * RZ/G3E does not support PIO mode. Always use BUSIF. + */ + if (rsnd_flags_has(priv, RSND_SSI_ALWAYS_BUSIF)) + return 1; + if (!rsnd_ssi_is_dma_mode(mod)) return 0; =20 @@ -865,6 +872,8 @@ static int rsnd_ssi_common_remove(struct rsnd_mod *mod, rsnd_flags_del(ssi, RSND_SSI_PROBED); } =20 + rsnd_dma_detach(io, mod, &io->dma); + return 0; } =20 @@ -1158,6 +1167,7 @@ int __rsnd_ssi_is_pin_sharing(struct rsnd_mod *mod) =20 int rsnd_ssi_probe(struct rsnd_priv *priv) { + struct reset_control *rstc; struct device_node *node; struct device *dev =3D rsnd_priv_to_dev(priv); struct rsnd_mod_ops *ops; @@ -1207,6 +1217,16 @@ int rsnd_ssi_probe(struct rsnd_priv *priv) goto rsnd_ssi_probe_done; } =20 + /* + * RZ/G3E uses per-SSI reset controllers. + * R-Car platforms typically don't have SSI reset controls. + */ + rstc =3D devm_reset_control_get_optional(dev, name); + if (IS_ERR(rstc)) { + ret =3D PTR_ERR(rstc); + goto rsnd_ssi_probe_done; + } + if (of_property_read_bool(np, "shared-pin")) rsnd_flags_set(ssi, RSND_SSI_CLK_PIN_SHARE); =20 @@ -1225,7 +1245,7 @@ int rsnd_ssi_probe(struct rsnd_priv *priv) ops =3D &rsnd_ssi_dma_ops; =20 ret =3D rsnd_mod_init(priv, rsnd_mod_get(ssi), ops, clk, - NULL, RSND_MOD_SSI, i); + rstc, RSND_MOD_SSI, i); if (ret) goto rsnd_ssi_probe_done; =20 --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AE5B03E8C60; Thu, 19 Mar 2026 15:56:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935809; cv=none; b=HyN6iOVLrTKovob4nycfiebLS3Zo6VR2X0vx42HUxpOXE7KV6TUh/gDpsfJBZKQo6wD7Ux9o6SndzJq2ZuAYc2tTAw93EXTOwAxfOSg0AtVhnmdQ0lSQvWdVxRp39gNM96kLfoyk4V6uijddYogxP26NjoCQrnmDquNeSA54lxU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935809; c=relaxed/simple; bh=978rvv5RyDO4c6uSVUDf09DjXhUxKQgKHDcwAqwip4k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gZdSaTwy+2nx/MEXpWiBouymwN+euW/rHQSHQwFmcHCNgpPGWMtTZcik0p24p3K0KJ8IDOEpwBrvLVZkExbbthVnMG7nt1WVuNNflPeVCnUpQW0/7i5bpP3YlsuWobmgeX42+/yi1hvSR084GuWtexVRt10wx+ai2w8KGMG3css= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: AM4xPiU7QlqJXXIjp/293w== X-CSE-MsgGUID: OBOzu5uPTVuFPZedGTBsOA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:56:46 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 0BB7A401B652; Fri, 20 Mar 2026 00:56:37 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 13/22] ASoC: rsnd: Add ADG reset support for RZ/G3E Date: Thu, 19 Mar 2026 16:53:25 +0100 Message-ID: <20260319155334.51278-14-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RZ/G3E requires the ADG reset line to be deasserted for the audio subsystem to operate. The ADG module clock is already managed via rsnd_adg_clk_enable/disable() through adg->adg, so no additional clock handling is needed. Add support for the optional "adg" reset control on Renesas RZ/G3E SoC. Signed-off-by: John Madieu --- sound/soc/renesas/rcar/adg.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/sound/soc/renesas/rcar/adg.c b/sound/soc/renesas/rcar/adg.c index 0105c60a144e..cbb5c4432a2d 100644 --- a/sound/soc/renesas/rcar/adg.c +++ b/sound/soc/renesas/rcar/adg.c @@ -771,6 +771,7 @@ void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, stru= ct seq_file *m) =20 int rsnd_adg_probe(struct rsnd_priv *priv) { + struct reset_control *rstc; struct rsnd_adg *adg; struct device *dev =3D rsnd_priv_to_dev(priv); int ret; @@ -779,8 +780,13 @@ int rsnd_adg_probe(struct rsnd_priv *priv) if (!adg) return -ENOMEM; =20 + rstc =3D devm_reset_control_get_optional_exclusive(dev, "adg"); + if (IS_ERR(rstc)) + return dev_err_probe(dev, PTR_ERR(rstc), + "failed to get adg reset\n"); + ret =3D rsnd_mod_init(priv, &adg->mod, &adg_ops, - NULL, NULL, 0, 0); + NULL, rstc, 0, 0); if (ret) return ret; =20 --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2E7303E9F74; Thu, 19 Mar 2026 15:56:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935819; cv=none; b=esp+XveCVs/uOUXPjKzU9MXuqJi0GNqnpwOsHaWdmIQqWfY9gMoGaSWqFKZYWVRWkBzg4/MdTLADsjJedCN7u4KWvBas1dzcf5LMcnLvYPf3LMMUhNBDgq7Avnm+mqJLUlOm0JfaBTRhh5CKD2WH8CTBIXDV9kVCRAzsLAcwg9c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935819; c=relaxed/simple; bh=2Wvth+RGf0sg0d4hqdYZcOVdrFi7Z1lhYjWoaex/b+Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E3/3xlbse/1fi8wlhm8IdI11Mhrw3p+g1d7akmUw3Y/v+9uDLXyOoF7Hz7K+iaciXxLTNyi1FgJ9oS1ulxtmDuPMlg4EHhd9clGEQchh2Fo77LKHqodIGN3EPHYCVWwvnKBle/TmebnU30WL0YGFS+CBBW4BWmlBG6ngsLKpCJo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 3ZYjQHbzQ+CWg7hLYihZZg== X-CSE-MsgGUID: AaV1zVqnR4Wiuy8BYv3H9g== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:56:56 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7E26E401B641; Fri, 20 Mar 2026 00:56:47 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 14/22] ASoC: rsnd: adg: Add per-SSI ADG and SSIF supply clock management Date: Thu, 19 Mar 2026 16:53:26 +0100 Message-ID: <20260319155334.51278-15-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RZ/G3E's ADG module requires explicit clock management for SSI audio interfaces that differs from R-Car Gen2/Gen3/Gen4: - Per-SSI ADG clocks (adg.ssi.N) for each SSI module - A shared SSIF supply clock for the SSI subsystem These clocks are acquired using optional APIs, making them transparent to platforms that do not require them. Additionally, since rsnd_adg_ssi_clk_try_start() is called from the trigger path (atomic context), clk_prepare_enable() cannot be used directly as clk_prepare() may sleep. Split clock handling into: - hw_params: clk_prepare() - sleepable context - trigger (start): clk_enable() - atomic safe - trigger (stop): clk_disable() - atomic safe - hw_free: clk_unprepare() - sleepable context Signed-off-by: John Madieu --- sound/soc/renesas/rcar/adg.c | 99 ++++++++++++++++++++++++++++++++++- sound/soc/renesas/rcar/rsnd.h | 2 + sound/soc/renesas/rcar/ssi.c | 18 +++++++ 3 files changed, 118 insertions(+), 1 deletion(-) diff --git a/sound/soc/renesas/rcar/adg.c b/sound/soc/renesas/rcar/adg.c index cbb5c4432a2d..131a60689f6d 100644 --- a/sound/soc/renesas/rcar/adg.c +++ b/sound/soc/renesas/rcar/adg.c @@ -19,6 +19,9 @@ #define CLKOUT3 3 #define CLKOUTMAX 4 =20 +/* Maximum SSI count for per-SSI clocks */ +#define ADG_SSI_MAX 10 + #define BRGCKR_31 (1 << 31) #define BRRx_MASK(x) (0x3FF & x) =20 @@ -34,6 +37,9 @@ struct rsnd_adg { struct clk *adg; struct clk *clkin[CLKINMAX]; struct clk *clkout[CLKOUTMAX]; + /* RZ/G3E: per-SSI ADG clocks (adg.ssi.0 through adg.ssi.9) */ + struct clk *clk_adg_ssi[ADG_SSI_MAX]; + struct clk *clk_ssif_supply; struct clk *null_clk; struct clk_onecell_data onecell; struct rsnd_mod mod; @@ -341,10 +347,58 @@ int rsnd_adg_clk_query(struct rsnd_priv *priv, unsign= ed int rate) return -EIO; } =20 +/* + * RZ/G3E: Prepare SSI clocks - call from hw_params (can sleep) + */ +int rsnd_adg_ssi_clk_prepare(struct rsnd_mod *ssi_mod) +{ + struct rsnd_priv *priv =3D rsnd_mod_to_priv(ssi_mod); + struct rsnd_adg *adg =3D rsnd_priv_to_adg(priv); + struct device *dev =3D rsnd_priv_to_dev(priv); + int id =3D rsnd_mod_id(ssi_mod); + int ret; + + ret =3D clk_prepare(adg->clk_adg_ssi[id]); + if (ret) { + dev_err(dev, "Cannot prepare adg.ssi.%d ADG clock\n", id); + return ret; + } + + ret =3D clk_prepare(adg->clk_ssif_supply); + if (ret) { + dev_err(dev, "Cannot prepare SSIF supply clock\n"); + clk_unprepare(adg->clk_adg_ssi[id]); + return ret; + } + + return 0; +} + +/* + * RZ/G3E: Unprepare SSI clocks - call from hw_free (can sleep) + */ +void rsnd_adg_ssi_clk_unprepare(struct rsnd_mod *ssi_mod) +{ + struct rsnd_priv *priv =3D rsnd_mod_to_priv(ssi_mod); + struct rsnd_adg *adg =3D rsnd_priv_to_adg(priv); + int id =3D rsnd_mod_id(ssi_mod); + + clk_unprepare(adg->clk_adg_ssi[id]); + clk_unprepare(adg->clk_ssif_supply); +} + int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod) { + struct rsnd_priv *priv =3D rsnd_mod_to_priv(ssi_mod); + struct rsnd_adg *adg =3D rsnd_priv_to_adg(priv); + int id =3D rsnd_mod_id(ssi_mod); + rsnd_adg_set_ssi_clk(ssi_mod, 0); =20 + /* RZ/G3E: only disable here, unprepare is done in hw_free */ + clk_disable(adg->clk_adg_ssi[id]); + clk_disable(adg->clk_ssif_supply); + return 0; } =20 @@ -354,7 +408,8 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod= , unsigned int rate) struct rsnd_adg *adg =3D rsnd_priv_to_adg(priv); struct device *dev =3D rsnd_priv_to_dev(priv); struct rsnd_mod *adg_mod =3D rsnd_mod_get(adg); - int data; + int id =3D rsnd_mod_id(ssi_mod); + int ret, data; u32 ckr =3D 0; =20 data =3D rsnd_adg_clk_query(priv, rate); @@ -376,6 +431,18 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mo= d, unsigned int rate) (ckr) ? adg->brg_rate[ADG_HZ_48] : adg->brg_rate[ADG_HZ_441]); =20 + /* + * RZ/G3E: enable per-SSI and supply clocks + * Prepare was done in hw_params + */ + ret =3D clk_enable(adg->clk_adg_ssi[id]); + if (ret) + dev_warn(dev, "Cannot enable adg.ssi.%d ADG clock\n", id); + + ret =3D clk_enable(adg->clk_ssif_supply); + if (ret) + dev_warn(dev, "Cannot enable SSIF supply clock\n"); + return 0; } =20 @@ -769,6 +836,31 @@ void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, str= uct seq_file *m) #define rsnd_adg_clk_dbg_info(priv, m) #endif =20 +static int rsnd_adg_get_ssi_clks(struct rsnd_priv *priv) +{ + struct rsnd_adg *adg =3D rsnd_priv_to_adg(priv); + struct device *dev =3D rsnd_priv_to_dev(priv); + char name[16]; + int i; + + /* SSIF supply clock */ + adg->clk_ssif_supply =3D devm_clk_get_optional(dev, "ssif_supply"); + if (IS_ERR(adg->clk_ssif_supply)) + return dev_err_probe(dev, PTR_ERR(adg->clk_ssif_supply), + "failed to get ssif_supply clock\n"); + + /* Per-SSI ADG clocks */ + for (i =3D 0; i < ADG_SSI_MAX; i++) { + snprintf(name, sizeof(name), "adg.ssi.%d", i); + adg->clk_adg_ssi[i] =3D devm_clk_get_optional(dev, name); + if (IS_ERR(adg->clk_adg_ssi[i])) + return dev_err_probe(dev, PTR_ERR(adg->clk_adg_ssi[i]), + "failed to get %s clock\n", name); + } + + return 0; +} + int rsnd_adg_probe(struct rsnd_priv *priv) { struct reset_control *rstc; @@ -800,6 +892,11 @@ int rsnd_adg_probe(struct rsnd_priv *priv) if (ret) return ret; =20 + /* RZ/G3E-specific: per-SSI ADG and SSIF supply clocks */ + ret =3D rsnd_adg_get_ssi_clks(priv); + if (ret) + return ret; + ret =3D rsnd_adg_clk_enable(priv); if (ret) return ret; diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h index da377bca45a9..6bde304f93a8 100644 --- a/sound/soc/renesas/rcar/rsnd.h +++ b/sound/soc/renesas/rcar/rsnd.h @@ -612,6 +612,8 @@ void __iomem *rsnd_gen_get_base_addr(struct rsnd_priv *= priv, int reg_id); * R-Car ADG */ int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate); +int rsnd_adg_ssi_clk_prepare(struct rsnd_mod *ssi_mod); +void rsnd_adg_ssi_clk_unprepare(struct rsnd_mod *ssi_mod); int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod); int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate= ); int rsnd_adg_probe(struct rsnd_priv *priv); diff --git a/sound/soc/renesas/rcar/ssi.c b/sound/soc/renesas/rcar/ssi.c index e25a4dfae90c..e0eb48f8977b 100644 --- a/sound/soc/renesas/rcar/ssi.c +++ b/sound/soc/renesas/rcar/ssi.c @@ -544,6 +544,7 @@ static int rsnd_ssi_hw_params(struct rsnd_mod *mod, { struct rsnd_dai *rdai =3D rsnd_io_to_rdai(io); unsigned int fmt_width =3D snd_pcm_format_width(params_format(params)); + int ret; =20 if (fmt_width > rdai->chan_width) { struct rsnd_priv *priv =3D rsnd_io_to_priv(io); @@ -553,6 +554,21 @@ static int rsnd_ssi_hw_params(struct rsnd_mod *mod, return -EINVAL; } =20 + /* RZ/G3E: prepare clocks here (can sleep) */ + ret =3D rsnd_adg_ssi_clk_prepare(mod); + if (ret < 0) + return ret; + + return 0; +} + +static int rsnd_ssi_hw_free(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + struct snd_pcm_substream *substream) +{ + /* RZ/G3E: unprepare clocks here (can sleep) */ + rsnd_adg_ssi_clk_unprepare(mod); + return 0; } =20 @@ -965,6 +981,7 @@ static struct rsnd_mod_ops rsnd_ssi_pio_ops =3D { .pointer =3D rsnd_ssi_pio_pointer, .pcm_new =3D rsnd_ssi_pcm_new, .hw_params =3D rsnd_ssi_hw_params, + .hw_free =3D rsnd_ssi_hw_free, .get_status =3D rsnd_ssi_get_status, }; =20 @@ -1079,6 +1096,7 @@ static struct rsnd_mod_ops rsnd_ssi_dma_ops =3D { .pcm_new =3D rsnd_ssi_pcm_new, .fallback =3D rsnd_ssi_fallback, .hw_params =3D rsnd_ssi_hw_params, + .hw_free =3D rsnd_ssi_hw_free, .get_status =3D rsnd_ssi_get_status, DEBUG_INFO }; --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 31AB83DD50C; Thu, 19 Mar 2026 15:57:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935828; cv=none; b=NMKSwSSfI0ulccgwGJG4Rye0pQNt5ec0nQTpSMFlpnIH3CI1wx/PAVhhIqbingWQJjFzZzSBlHubcSdOO+Mhl8Zz/Gp/utsvLmgsdHKcYKFkyqbkLfthum9Or8KsqJ3BWGmeHBEVU0dnuxCQtHs/2WLREOQ9K09TkUMEOCroNI0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935828; c=relaxed/simple; bh=BiFjNbYTzxnk6ALKdyDPQZUoxOq+1KLiy6vWkM//XsQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HtfxRMWw6CrRSJFTGkfAI1rqV25SDcogvOpRquLSg2nS5aw+egpHynHfbvV7qQ+oqYeSF369ARttM/9Qv8ZhpL2A4Pvdu/gyjxMnDf1w5HiQSCOANg3r8rIBSgtwxrrv0qk7jQjOZ4OrZazF7ZXzh/InyG3FyJ22hwwOGLkXSvA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: hxGmEF+LTbGWgg0WNz9hbw== X-CSE-MsgGUID: TPrQGtIwSSqzP0avKxzA9w== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:57:05 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C88B4401B647; Fri, 20 Mar 2026 00:56:56 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 15/22] ASoC: rsnd: src: Add SRC reset and clock support for RZ/G3E Date: Thu, 19 Mar 2026 16:53:27 +0100 Message-ID: <20260319155334.51278-16-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RZ/G3E SoC requires explicit SCU (Sampling Rate Converter Unit) reset and clock management unlike previous R-Car generations: - scu_clk: SCU module clock - scu_clkx2: SCU double-rate clock - scu_supply_clk: SCU supply clock Without these clocks enabled, the SRC module cannot operate on RZ/G3E. Add support for the shared SCU reset controller used by the SRC modules on the Renesas RZ/G3E SoC. All SRC instances are gated by the same "scu" reset line. Signed-off-by: John Madieu --- sound/soc/renesas/rcar/rsnd.h | 7 ++++++ sound/soc/renesas/rcar/src.c | 45 +++++++++++++++++++++++++++++++++-- 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h index 6bde304f93a8..a803c0f03665 100644 --- a/sound/soc/renesas/rcar/rsnd.h +++ b/sound/soc/renesas/rcar/rsnd.h @@ -642,6 +642,13 @@ struct rsnd_priv { struct clk *clk_audmac_pp; struct reset_control *rstc_audmac_pp; =20 + /* + * Below values will be filled in rsnd_src_probe() + */ + struct clk *clk_scu; + struct clk *clk_scu_x2; + struct clk *clk_scu_supply; + spinlock_t lock; unsigned int ssiu_busif_count; unsigned long flags; diff --git a/sound/soc/renesas/rcar/src.c b/sound/soc/renesas/rcar/src.c index 8b58cc20e7a8..e1f609589406 100644 --- a/sound/soc/renesas/rcar/src.c +++ b/sound/soc/renesas/rcar/src.c @@ -516,6 +516,7 @@ static int rsnd_src_init(struct rsnd_mod *mod, struct rsnd_priv *priv) { struct rsnd_src *src =3D rsnd_mod_to_src(mod); + struct device *dev =3D rsnd_priv_to_dev(priv); int ret; =20 /* reset sync convert_rate */ @@ -526,6 +527,12 @@ static int rsnd_src_init(struct rsnd_mod *mod, if (ret < 0) return ret; =20 + ret =3D clk_prepare_enable(priv->clk_scu_supply); + if (ret) { + dev_err(dev, "Cannot enable scu_supply_clk\n"); + return ret; + } + rsnd_src_activation(mod); =20 rsnd_src_init_convert_rate(io, mod); @@ -549,6 +556,8 @@ static int rsnd_src_quit(struct rsnd_mod *mod, src->sync.val =3D src->current_sync_rate =3D 0; =20 + clk_disable_unprepare(priv->clk_scu_supply); + return 0; } =20 @@ -711,8 +720,9 @@ struct rsnd_mod *rsnd_src_mod_get(struct rsnd_priv *pri= v, int id) =20 int rsnd_src_probe(struct rsnd_priv *priv) { - struct device_node *node; struct device *dev =3D rsnd_priv_to_dev(priv); + struct reset_control *rstc; + struct device_node *node; struct rsnd_src *src; struct clk *clk; char name[RSND_SRC_NAME_SIZE]; @@ -737,6 +747,27 @@ int rsnd_src_probe(struct rsnd_priv *priv) priv->src_nr =3D nr; priv->src =3D src; =20 + priv->clk_scu =3D devm_clk_get_optional_enabled(dev, "scu"); + if (IS_ERR(priv->clk_scu)) { + ret =3D dev_err_probe(dev, PTR_ERR(priv->clk_scu), + "failed to get scu clock\n"); + goto rsnd_src_probe_done; + } + + priv->clk_scu_x2 =3D devm_clk_get_optional_enabled(dev, "scu_x2"); + if (IS_ERR(priv->clk_scu_x2)) { + ret =3D dev_err_probe(dev, PTR_ERR(priv->clk_scu_x2), + "failed to get scu_x2 clock\n"); + goto rsnd_src_probe_done; + } + + priv->clk_scu_supply =3D devm_clk_get_optional(dev, "scu_supply"); + if (IS_ERR(priv->clk_scu_supply)) { + ret =3D dev_err_probe(dev, PTR_ERR(priv->clk_scu_supply), + "failed to get scu_supply clock\n"); + goto rsnd_src_probe_done; + } + i =3D 0; for_each_child_of_node_scoped(node, np) { if (!of_device_is_available(np)) @@ -759,6 +790,16 @@ int rsnd_src_probe(struct rsnd_priv *priv) goto rsnd_src_probe_done; } =20 + /* + * RZ/G3E uses a shared SCU reset controller for all SRC modules. + * R-Car platforms typically don't have SRC reset controls. + */ + rstc =3D devm_reset_control_get_optional_shared(dev, "scu"); + if (IS_ERR(rstc)) { + ret =3D PTR_ERR(rstc); + goto rsnd_src_probe_done; + } + clk =3D devm_clk_get(dev, name); if (IS_ERR(clk)) { ret =3D PTR_ERR(clk); @@ -766,7 +807,7 @@ int rsnd_src_probe(struct rsnd_priv *priv) } =20 ret =3D rsnd_mod_init(priv, rsnd_mod_get(src), - &rsnd_src_ops, clk, NULL, RSND_MOD_SRC, i); + &rsnd_src_ops, clk, rstc, RSND_MOD_SRC, i); if (ret) goto rsnd_src_probe_done; =20 --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7D9013DD50C; Thu, 19 Mar 2026 15:57:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935837; cv=none; b=Xa2ulCvjv72kUYxxi7wkGDl2+rBJUSvSFDPAc1nGlIPQu/egYHdsINhDcOmxZBIq6NaUsTNHmkYtIMeAIbFA53CJceCQgKkHzBntLLybsZOSul5/m7p1Ncn8unsD05VbVVH3FHvcmGgq/OuVD5DBbRScbYbibeRiNFy0e2gYad8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935837; c=relaxed/simple; bh=oC3zyeBxhmAjtLYxKjJSz5zaw0Nnjo0hvRlG4CCzvxU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LjNrVEfXXve2kfJ7D4cAv0j29EPYEwWuzkfH6XDGIBZ6JAvdSiftkz5Dk+Rn+EmpaWkvNPQmUlN1d8tiCnm3I2+TQGTYGrvbaxeHCvtnJS0krrRcFuOr1VbLAg/lUs/N6VmYIsATkfu2SokPfG1gQPk/Xcxj5oP9SLziAqNPCI0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: a1j2HT1ZTRG6zlBKKFVOeg== X-CSE-MsgGUID: doTmm7BPS42rZVj1ZggEdQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:57:14 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 01DFE401BC51; Fri, 20 Mar 2026 00:57:05 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 16/22] ASoC: rsnd: Export module getters for PM support Date: Thu, 19 Mar 2026 16:53:28 +0100 Message-ID: <20260319155334.51278-17-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Export rsnd_adg_mod_get() and rsnd_ssiu_mod_get() to make them accessible from core.c. This is preparation for system suspend/resume support, where the PM callbacks need to iterate over all modules to save and restore their clock and reset state. Other modules (SSI, SRC, CTU, MIX, DVC) already have their getters exported. Signed-off-by: John Madieu --- sound/soc/renesas/rcar/adg.c | 10 ++++++++++ sound/soc/renesas/rcar/rsnd.h | 2 ++ sound/soc/renesas/rcar/ssiu.c | 2 +- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/sound/soc/renesas/rcar/adg.c b/sound/soc/renesas/rcar/adg.c index 131a60689f6d..d73f29bc9de7 100644 --- a/sound/soc/renesas/rcar/adg.c +++ b/sound/soc/renesas/rcar/adg.c @@ -906,6 +906,16 @@ int rsnd_adg_probe(struct rsnd_priv *priv) return 0; } =20 +struct rsnd_mod *rsnd_adg_mod_get(struct rsnd_priv *priv) +{ + struct rsnd_adg *adg =3D rsnd_priv_to_adg(priv); + + if (!adg) + return NULL; + + return rsnd_mod_get(adg); +} + void rsnd_adg_remove(struct rsnd_priv *priv) { struct device *dev =3D rsnd_priv_to_dev(priv); diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h index a803c0f03665..2cee5c2aa7d7 100644 --- a/sound/soc/renesas/rcar/rsnd.h +++ b/sound/soc/renesas/rcar/rsnd.h @@ -628,6 +628,7 @@ int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_m= od, #define rsnd_adg_clk_disable(priv) rsnd_adg_clk_control(priv, 0) int rsnd_adg_clk_control(struct rsnd_priv *priv, int enable); void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m); +struct rsnd_mod *rsnd_adg_mod_get(struct rsnd_priv *priv); =20 /* * R-Car sound priv @@ -824,6 +825,7 @@ int rsnd_ssi_is_dma_mode(struct rsnd_mod *mod); int __rsnd_ssi_is_pin_sharing(struct rsnd_mod *mod); =20 #define rsnd_ssi_of_node(priv) rsnd_parse_of_node(priv, RSND_NODE_SSI) +struct rsnd_mod *rsnd_ssiu_mod_get(struct rsnd_priv *priv, int id); void rsnd_parse_connect_ssi(struct rsnd_dai *rdai, struct device_node *playback, struct device_node *capture); diff --git a/sound/soc/renesas/rcar/ssiu.c b/sound/soc/renesas/rcar/ssiu.c index f377d9414633..1462f02c2a7f 100644 --- a/sound/soc/renesas/rcar/ssiu.c +++ b/sound/soc/renesas/rcar/ssiu.c @@ -434,7 +434,7 @@ static struct rsnd_mod_ops rsnd_ssiu_ops_gen2 =3D { DEBUG_INFO }; =20 -static struct rsnd_mod *rsnd_ssiu_mod_get(struct rsnd_priv *priv, int id) +struct rsnd_mod *rsnd_ssiu_mod_get(struct rsnd_priv *priv, int id) { if (WARN_ON(id < 0 || id >=3D rsnd_ssiu_nr(priv))) id =3D 0; --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6F1CE3DD50C; Thu, 19 Mar 2026 15:57:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935847; cv=none; b=HUq8LRjS6I9VUW9UFNwxu2pP8Or2mHU5/AYlHV94WFyoUUpfBST0kJ6rNI9qHv4t713J/JZ9gpUz2wevoyNOr4dB85WF9zLE7reM6ejfKg/JZJQyMPwKRfj1Eee1p18G5kxO5DDaPFgtVY7qU3CBmPt22s3LxQCKzKduDXtYLhc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935847; c=relaxed/simple; bh=+zrwIyAAi1BvsO0DwGr5+Q2OiR2vGMzMUDIUztidatU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R7/MDvCoX71NdZwU0azsNxddvKYuyOz0DMmE/j8WfLHGjWlAdrdthTFfRiONmVxo2QC0aB9Dbps0vtvGSNkKARMm6kTjmvnrmSd8K6ZF6DxcfIuyeaApcaXj8mI1ObTsSEx87HNd4pQwocHhkdQl7Kc6cB5VUdsUoL3JbOyzWQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 30WpKlxkTHexIAunFk5UOA== X-CSE-MsgGUID: lMvSfJQwQRKVsTdYO2QxrA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:57:24 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id A10EB401BC51; Fri, 20 Mar 2026 00:57:15 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 17/22] ASoC: rsnd: Add system suspend/resume support Date: Thu, 19 Mar 2026 16:53:29 +0100 Message-ID: <20260319155334.51278-18-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On RZ/G3E and similar SoCs, the audio subsystem loses its state during deep sleep, due to lacking of proper clock and reset management in the PM path. Implement suspend/resume callbacks that save and restore the hardware state by managing clocks and reset controls in the correct order: - Suspend follows reverse probe order - Resume follows probe order Note that module clocks (mod->clk) are left in "prepared but disabled" state after rsnd_mod_init(), so suspend only needs to unprepare them and resume only needs to prepare them. Signed-off-by: John Madieu --- sound/soc/renesas/rcar/core.c | 108 +++++++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 2 deletions(-) diff --git a/sound/soc/renesas/rcar/core.c b/sound/soc/renesas/rcar/core.c index 6a25580b9c6a..eb504551e410 100644 --- a/sound/soc/renesas/rcar/core.c +++ b/sound/soc/renesas/rcar/core.c @@ -962,7 +962,8 @@ static int rsnd_soc_hw_rule_channels(struct snd_pcm_hw_= params *params, static const struct snd_pcm_hardware rsnd_pcm_hardware =3D { .info =3D SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP | - SNDRV_PCM_INFO_MMAP_VALID, + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_RESUME, .buffer_bytes_max =3D 64 * 1024, .period_bytes_min =3D 32, .period_bytes_max =3D 8192, @@ -2059,11 +2060,70 @@ static void rsnd_remove(struct platform_device *pde= v) remove_func[i](priv); } =20 +static void rsnd_suspend_mod(struct rsnd_mod *mod) +{ + if (!mod) + return; + + clk_unprepare(mod->clk); + reset_control_assert(mod->rstc); +} + +static void rsnd_resume_mod(struct rsnd_mod *mod) +{ + if (!mod) + return; + + reset_control_deassert(mod->rstc); + clk_prepare(mod->clk); +} + static int rsnd_suspend(struct device *dev) { struct rsnd_priv *priv =3D dev_get_drvdata(dev); + int i; + + /* + * Reverse order of probe: + * ADG -> DVC -> MIX -> CTU -> SRC -> SSIU -> SSI -> DMA + */ =20 + /* ADG */ + /* ADG clock disabled via rsnd_adg_clk_disable() -> adg->adg */ rsnd_adg_clk_disable(priv); + rsnd_suspend_mod(rsnd_adg_mod_get(priv)); + + /* DVC */ + for (i =3D priv->dvc_nr - 1; i >=3D 0; i--) + rsnd_suspend_mod(rsnd_dvc_mod_get(priv, i)); + + /* MIX */ + for (i =3D priv->mix_nr - 1; i >=3D 0; i--) + rsnd_suspend_mod(rsnd_mix_mod_get(priv, i)); + + /* CTU */ + for (i =3D priv->ctu_nr - 1; i >=3D 0; i--) + rsnd_suspend_mod(rsnd_ctu_mod_get(priv, i)); + + /* SRC */ + for (i =3D priv->src_nr - 1; i >=3D 0; i--) + rsnd_suspend_mod(rsnd_src_mod_get(priv, i)); + + clk_disable_unprepare(priv->clk_scu_x2); + clk_disable_unprepare(priv->clk_scu); + + /* SSIU */ + for (i =3D priv->ssiu_nr - 1; i >=3D 0; i--) + rsnd_suspend_mod(rsnd_ssiu_mod_get(priv, i)); + + /* SSI */ + for (i =3D priv->ssi_nr - 1; i >=3D 0; i--) + rsnd_suspend_mod(rsnd_ssi_mod_get(priv, i)); + + /* DMA */ + clk_disable_unprepare(priv->clk_audmac_pp); + if (priv->rstc_audmac_pp) + reset_control_assert(priv->rstc_audmac_pp); =20 return 0; } @@ -2071,8 +2131,52 @@ static int rsnd_suspend(struct device *dev) static int rsnd_resume(struct device *dev) { struct rsnd_priv *priv =3D dev_get_drvdata(dev); + int i; + + /* + * Same order as probe: + * DMA -> SSI -> SSIU -> SRC -> CTU -> MIX -> DVC -> ADG + */ + + /* DMA */ + if (priv->rstc_audmac_pp) + reset_control_deassert(priv->rstc_audmac_pp); =20 - return rsnd_adg_clk_enable(priv); + clk_prepare_enable(priv->clk_audmac_pp); + + /* SSI */ + for (i =3D 0; i < priv->ssi_nr; i++) + rsnd_resume_mod(rsnd_ssi_mod_get(priv, i)); + + /* SSIU */ + for (i =3D 0; i < priv->ssiu_nr; i++) + rsnd_resume_mod(rsnd_ssiu_mod_get(priv, i)); + + /* SRC */ + clk_prepare_enable(priv->clk_scu); + clk_prepare_enable(priv->clk_scu_x2); + + for (i =3D 0; i < priv->src_nr; i++) + rsnd_resume_mod(rsnd_src_mod_get(priv, i)); + + /* CTU */ + for (i =3D 0; i < priv->ctu_nr; i++) + rsnd_resume_mod(rsnd_ctu_mod_get(priv, i)); + + /* MIX */ + for (i =3D 0; i < priv->mix_nr; i++) + rsnd_resume_mod(rsnd_mix_mod_get(priv, i)); + + /* DVC */ + for (i =3D 0; i < priv->dvc_nr; i++) + rsnd_resume_mod(rsnd_dvc_mod_get(priv, i)); + + /* ADG */ + rsnd_resume_mod(rsnd_adg_mod_get(priv)); + /* ADG clock enabled via rsnd_adg_clk_enable() -> adg->adg */ + rsnd_adg_clk_enable(priv); + + return 0; } =20 static const struct dev_pm_ops rsnd_pm_ops =3D { --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3644B3E92B6; Thu, 19 Mar 2026 15:57:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935857; cv=none; b=QKNTRArx/Qm1jkeRNZPDxj4ZKI8snVrmGmlsLaQMYI/JQaAlAPUDG2G0BQ7lGhf/hLGbPmXa1xyzYC02hzLQJ1nzQuiw8Xwayhz90P/OahpEFN1tK3BJlRbUuYi9zTRmc/qJO4jU2T9CxSwQ/qEEhWX95K1IsTu0CHAyAQQDJRo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935857; c=relaxed/simple; bh=HD4ub3oiMZjVGLfKPj58IDNXwT2pisneCi2Nx3lhf1I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CI0e64/9HRGU98OR4aQ7bA4xaxs/mXSXGW+WMzv3JP90WpCO5hdQfMU4LUsPEVQyF85clG5ojKaf2f4mmkfQ89uOSwQdebhm0klHIA/B30TaChmHoT2KolknK37dL8HFdjwzOyxk8AjrWtHLjH3urnWneHTY2nFuS0A6RIO7Stc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: rAmKXkMAQV6z+fC3wdD5tg== X-CSE-MsgGUID: EpIKdKTYQ4mDVyEbExiVfA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2026 00:57:34 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6CD18401BC51; Fri, 20 Mar 2026 00:57:25 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 18/22] arm64: dts: renesas: r9a09g047: Add R-Car Sound support Date: Thu, 19 Mar 2026 16:53:30 +0100 Message-ID: <20260319155334.51278-19-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the rzg3e_sound node for the RZ/G3E SoC with all sub-components: - SSI (Serial Sound Interface) units 0-9 - SSIU (Serial Sound Interface Unit) units 0-27 - SRC (Sample Rate Converter) units 0-9 - CTU (Channel Transfer Unit) units 0-7 - DVC (Digital Volume Control) units 0-1 - MIX (Mixer) units 0-1 Wire up all 5 DMA controllers (dmac0-dmac4) for each audio sub-node with repeated channel names, so that the DMA core can pick the first available controller. Update all DMA controllers' #dma-cells to 2 to support the ACK signal routing required by audio peripherals through the ICU. Signed-off-by: John Madieu --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 516 ++++++++++++++++++++- 1 file changed, 511 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index 2787d316ea04..2eb9a6312281 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -357,7 +357,7 @@ dmac0: dma-controller@11400000 { clocks =3D <&cpg CPG_MOD 0x0>; power-domains =3D <&cpg>; resets =3D <&cpg 0x31>; - #dma-cells =3D <1>; + #dma-cells =3D <2>; dma-channels =3D <16>; renesas,icu =3D <&icu 4>; }; @@ -391,7 +391,7 @@ dmac1: dma-controller@14830000 { clocks =3D <&cpg CPG_MOD 0x1>; power-domains =3D <&cpg>; resets =3D <&cpg 0x32>; - #dma-cells =3D <1>; + #dma-cells =3D <2>; dma-channels =3D <16>; renesas,icu =3D <&icu 0>; }; @@ -425,7 +425,7 @@ dmac2: dma-controller@14840000 { clocks =3D <&cpg CPG_MOD 0x2>; power-domains =3D <&cpg>; resets =3D <&cpg 0x33>; - #dma-cells =3D <1>; + #dma-cells =3D <2>; dma-channels =3D <16>; renesas,icu =3D <&icu 1>; }; @@ -459,7 +459,7 @@ dmac3: dma-controller@12000000 { clocks =3D <&cpg CPG_MOD 0x3>; power-domains =3D <&cpg>; resets =3D <&cpg 0x34>; - #dma-cells =3D <1>; + #dma-cells =3D <2>; dma-channels =3D <16>; renesas,icu =3D <&icu 2>; }; @@ -493,7 +493,7 @@ dmac4: dma-controller@12010000 { clocks =3D <&cpg CPG_MOD 0x4>; power-domains =3D <&cpg>; resets =3D <&cpg 0x35>; - #dma-cells =3D <1>; + #dma-cells =3D <2>; dma-channels =3D <16>; renesas,icu =3D <&icu 3>; }; @@ -834,6 +834,512 @@ rsci9: serial@12803000 { status =3D "disabled"; }; =20 + snd_rzg3e: sound@13c00000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells =3D <0>; <&snd_rzg3e>; + * Multi DAI : #sound-dai-cells =3D <1>; <&snd_rzg3e N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells =3D <0>; <&snd_rzg3e>; + * clkout0/1/2/3: #clock-cells =3D <1>; <&snd_rzg3e N>; + */ + compatible =3D "renesas,rcar_sound-r9a09g047"; + reg =3D <0 0x13c00000 0 0x10000>, /* SCU */ + <0 0x13c20000 0 0x10000>, /* ADG */ + <0 0x13c30000 0 0x1000>, /* SSIU */ + <0 0x13c31000 0 0x1F000>, /* SSI */ + <0 0x13c50000 0 0x10000>; /* Audio DMAC peri peri */ + reg-names =3D "scu", "adg", "ssiu", "ssi", "audmapp"; + clocks =3D <&cpg CPG_MOD 245>, + <&cpg CPG_MOD 394>, + <&cpg CPG_MOD 393>, + <&cpg CPG_MOD 392>, + <&cpg CPG_MOD 391>, + <&cpg CPG_MOD 390>, + <&cpg CPG_MOD 389>, + <&cpg CPG_MOD 388>, + <&cpg CPG_MOD 387>, + <&cpg CPG_MOD 386>, + <&cpg CPG_MOD 385>, + <&cpg CPG_MOD 381>, + <&cpg CPG_MOD 380>, + <&cpg CPG_MOD 379>, + <&cpg CPG_MOD 378>, + <&cpg CPG_MOD 377>, + <&cpg CPG_MOD 376>, + <&cpg CPG_MOD 375>, + <&cpg CPG_MOD 374>, + <&cpg CPG_MOD 373>, + <&cpg CPG_MOD 372>, + <&cpg CPG_MOD 371>, + <&cpg CPG_MOD 370>, + <&cpg CPG_MOD 371>, + <&cpg CPG_MOD 370>, + <&cpg CPG_MOD 368>, + <&cpg CPG_MOD 369>, + <&cpg CPG_MOD 251>, + <&cpg CPG_MOD 252>, + <&cpg CPG_MOD 253>, + <&cpg CPG_MOD 250>, + <&cpg CPG_MOD 384>, + <&cpg CPG_MOD 246>, + <&cpg CPG_MOD 247>, + <&cpg CPG_MOD 382>, + <&cpg CPG_MOD 361>, + <&cpg CPG_MOD 360>, + <&cpg CPG_MOD 359>, + <&cpg CPG_MOD 358>, + <&cpg CPG_MOD 357>, + <&cpg CPG_MOD 356>, + <&cpg CPG_MOD 355>, + <&cpg CPG_MOD 354>, + <&cpg CPG_MOD 353>, + <&cpg CPG_MOD 352>, + <&cpg CPG_MOD 248>, + <&cpg CPG_MOD 249>; + clock-names =3D "ssi-all", + "ssi.9", "ssi.8", + "ssi.7", "ssi.6", + "ssi.5", "ssi.4", + "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", + "src.7", "src.6", + "src.5", "src.4", + "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", + "clk_c", "clk_i", + "ssif_supply", + "scu", "scu_x2", + "scu_supply", + "adg.ssi.9", "adg.ssi.8", + "adg.ssi.7", "adg.ssi.6", + "adg.ssi.5", "adg.ssi.4", + "adg.ssi.3", "adg.ssi.2", + "adg.ssi.1", "adg.ssi.0", + "audmac_pp", "adg"; + power-domains =3D <&cpg>; + resets =3D <&cpg 225>, + <&cpg 235>, + <&cpg 234>, + <&cpg 233>, + <&cpg 232>, + <&cpg 231>, + <&cpg 230>, + <&cpg 229>, + <&cpg 228>, + <&cpg 227>, + <&cpg 226>, + <&cpg 236>, + <&cpg 238>, + <&cpg 237>; + reset-names =3D "ssi-all", + "ssi.9", "ssi.8", + "ssi.7", "ssi.6", + "ssi.5", "ssi.4", + "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "scu", "adg", + "audmac_pp"; + status =3D "disabled"; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas =3D <&dmac0 0x1db3 0x1a>, + <&dmac1 0x1db3 0x1a>, + <&dmac2 0x1db3 0x1a>, + <&dmac3 0x1db3 0x1a>, + <&dmac4 0x1db3 0x1a>; + dma-names =3D "tx", "tx", "tx", "tx", "tx"; + }; + dvc1: dvc-1 { + dmas =3D <&dmac0 0x1db4 0x1b>, + <&dmac1 0x1db4 0x1b>, + <&dmac2 0x1db4 0x1b>, + <&dmac3 0x1db4 0x1b>, + <&dmac4 0x1db4 0x1b>; + dma-names =3D "tx", "tx", "tx", "tx", "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts =3D ; + dmas =3D <&dmac0 0x1d9f 0x6>, <&dmac0 0x1da9 0x10>, + <&dmac1 0x1d9f 0x6>, <&dmac1 0x1da9 0x10>, + <&dmac2 0x1d9f 0x6>, <&dmac2 0x1da9 0x10>, + <&dmac3 0x1d9f 0x6>, <&dmac3 0x1da9 0x10>, + <&dmac4 0x1d9f 0x6>, <&dmac4 0x1da9 0x10>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src1: src-1 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da0 0x7>, <&dmac0 0x1daa 0x11>, + <&dmac1 0x1da0 0x7>, <&dmac1 0x1daa 0x11>, + <&dmac2 0x1da0 0x7>, <&dmac2 0x1daa 0x11>, + <&dmac3 0x1da0 0x7>, <&dmac3 0x1daa 0x11>, + <&dmac4 0x1da0 0x7>, <&dmac4 0x1daa 0x11>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src2: src-2 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da1 0x8>, <&dmac0 0x1dab 0x12>, + <&dmac1 0x1da1 0x8>, <&dmac1 0x1dab 0x12>, + <&dmac2 0x1da1 0x8>, <&dmac2 0x1dab 0x12>, + <&dmac3 0x1da1 0x8>, <&dmac3 0x1dab 0x12>, + <&dmac4 0x1da1 0x8>, <&dmac4 0x1dab 0x12>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src3: src-3 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da2 0x9>, <&dmac0 0x1dac 0x13>, + <&dmac1 0x1da2 0x9>, <&dmac1 0x1dac 0x13>, + <&dmac2 0x1da2 0x9>, <&dmac2 0x1dac 0x13>, + <&dmac3 0x1da2 0x9>, <&dmac3 0x1dac 0x13>, + <&dmac4 0x1da2 0x9>, <&dmac4 0x1dac 0x13>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src4: src-4 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da3 0xa>, <&dmac0 0x1dad 0x14>, + <&dmac1 0x1da3 0xa>, <&dmac1 0x1dad 0x14>, + <&dmac2 0x1da3 0xa>, <&dmac2 0x1dad 0x14>, + <&dmac3 0x1da3 0xa>, <&dmac3 0x1dad 0x14>, + <&dmac4 0x1da3 0xa>, <&dmac4 0x1dad 0x14>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src5: src-5 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da4 0xb>, <&dmac0 0x1dae 0x15>, + <&dmac1 0x1da4 0xb>, <&dmac1 0x1dae 0x15>, + <&dmac2 0x1da4 0xb>, <&dmac2 0x1dae 0x15>, + <&dmac3 0x1da4 0xb>, <&dmac3 0x1dae 0x15>, + <&dmac4 0x1da4 0xb>, <&dmac4 0x1dae 0x15>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src6: src-6 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da5 0xc>, <&dmac0 0x1daf 0x16>, + <&dmac1 0x1da5 0xc>, <&dmac1 0x1daf 0x16>, + <&dmac2 0x1da5 0xc>, <&dmac2 0x1daf 0x16>, + <&dmac3 0x1da5 0xc>, <&dmac3 0x1daf 0x16>, + <&dmac4 0x1da5 0xc>, <&dmac4 0x1daf 0x16>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src7: src-7 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da6 0xd>, <&dmac0 0x1db0 0x17>, + <&dmac1 0x1da6 0xd>, <&dmac1 0x1db0 0x17>, + <&dmac2 0x1da6 0xd>, <&dmac2 0x1db0 0x17>, + <&dmac3 0x1da6 0xd>, <&dmac3 0x1db0 0x17>, + <&dmac4 0x1da6 0xd>, <&dmac4 0x1db0 0x17>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src8: src-8 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da7 0xe>, <&dmac0 0x1db1 0x18>, + <&dmac1 0x1da7 0xe>, <&dmac1 0x1db1 0x18>, + <&dmac2 0x1da7 0xe>, <&dmac2 0x1db1 0x18>, + <&dmac3 0x1da7 0xe>, <&dmac3 0x1db1 0x18>, + <&dmac4 0x1da7 0xe>, <&dmac4 0x1db1 0x18>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src9: src-9 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da8 0xf>, <&dmac0 0x1db2 0x19>, + <&dmac1 0x1da8 0xf>, <&dmac1 0x1db2 0x19>, + <&dmac2 0x1da8 0xf>, <&dmac2 0x1db2 0x19>, + <&dmac3 0x1da8 0xf>, <&dmac3 0x1db2 0x19>, + <&dmac4 0x1da8 0xf>, <&dmac4 0x1db2 0x19>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts =3D ; + }; + ssi1: ssi-1 { + interrupts =3D ; + }; + ssi2: ssi-2 { + interrupts =3D ; + }; + ssi3: ssi-3 { + interrupts =3D ; + }; + ssi4: ssi-4 { + interrupts =3D ; + }; + ssi5: ssi-5 { + interrupts =3D ; + }; + ssi6: ssi-6 { + interrupts =3D ; + }; + ssi7: ssi-7 { + interrupts =3D ; + }; + ssi8: ssi-8 { + interrupts =3D ; + }; + ssi9: ssi-9 { + interrupts =3D ; + }; + }; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas =3D <&dmac0 0x1d61 0x1c>, <&dmac0 0x1d62 0x1d>, + <&dmac1 0x1d61 0x1c>, <&dmac1 0x1d62 0x1d>, + <&dmac2 0x1d61 0x1c>, <&dmac2 0x1d62 0x1d>, + <&dmac3 0x1d61 0x1c>, <&dmac3 0x1d62 0x1d>, + <&dmac4 0x1d61 0x1c>, <&dmac4 0x1d62 0x1d>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu01: ssiu-1 { + dmas =3D <&dmac0 0x1d63 0x1e>, <&dmac0 0x1d64 0x1f>, + <&dmac1 0x1d63 0x1e>, <&dmac1 0x1d64 0x1f>, + <&dmac2 0x1d63 0x1e>, <&dmac2 0x1d64 0x1f>, + <&dmac3 0x1d63 0x1e>, <&dmac3 0x1d64 0x1f>, + <&dmac4 0x1d63 0x1e>, <&dmac4 0x1d64 0x1f>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu02: ssiu-2 { + dmas =3D <&dmac0 0x1d65 0x20>, <&dmac0 0x1d66 0x21>, + <&dmac1 0x1d65 0x20>, <&dmac1 0x1d66 0x21>, + <&dmac2 0x1d65 0x20>, <&dmac2 0x1d66 0x21>, + <&dmac3 0x1d65 0x20>, <&dmac3 0x1d66 0x21>, + <&dmac4 0x1d65 0x20>, <&dmac4 0x1d66 0x21>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu03: ssiu-3 { + dmas =3D <&dmac0 0x1d67 0x22>, <&dmac0 0x1d68 0x23>, + <&dmac1 0x1d67 0x22>, <&dmac1 0x1d68 0x23>, + <&dmac2 0x1d67 0x22>, <&dmac2 0x1d68 0x23>, + <&dmac3 0x1d67 0x22>, <&dmac3 0x1d68 0x23>, + <&dmac4 0x1d67 0x22>, <&dmac4 0x1d68 0x23>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu10: ssiu-4 { + dmas =3D <&dmac0 0x1d69 0x24>, <&dmac0 0x1d6a 0x25>, + <&dmac1 0x1d69 0x24>, <&dmac1 0x1d6a 0x25>, + <&dmac2 0x1d69 0x24>, <&dmac2 0x1d6a 0x25>, + <&dmac3 0x1d69 0x24>, <&dmac3 0x1d6a 0x25>, + <&dmac4 0x1d69 0x24>, <&dmac4 0x1d6a 0x25>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu11: ssiu-5 { + dmas =3D <&dmac0 0x1d6b 0x26>, <&dmac0 0x1d6c 0x27>, + <&dmac1 0x1d6b 0x26>, <&dmac1 0x1d6c 0x27>, + <&dmac2 0x1d6b 0x26>, <&dmac2 0x1d6c 0x27>, + <&dmac3 0x1d6b 0x26>, <&dmac3 0x1d6c 0x27>, + <&dmac4 0x1d6b 0x26>, <&dmac4 0x1d6c 0x27>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu12: ssiu-6 { + dmas =3D <&dmac0 0x1d6d 0x28>, <&dmac0 0x1d6e 0x29>, + <&dmac1 0x1d6d 0x28>, <&dmac1 0x1d6e 0x29>, + <&dmac2 0x1d6d 0x28>, <&dmac2 0x1d6e 0x29>, + <&dmac3 0x1d6d 0x28>, <&dmac3 0x1d6e 0x29>, + <&dmac4 0x1d6d 0x28>, <&dmac4 0x1d6e 0x29>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu13: ssiu-7 { + dmas =3D <&dmac0 0x1d6f 0x2a>, <&dmac0 0x1d70 0x2b>, + <&dmac1 0x1d6f 0x2a>, <&dmac1 0x1d70 0x2b>, + <&dmac2 0x1d6f 0x2a>, <&dmac2 0x1d70 0x2b>, + <&dmac3 0x1d6f 0x2a>, <&dmac3 0x1d70 0x2b>, + <&dmac4 0x1d6f 0x2a>, <&dmac4 0x1d70 0x2b>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu20: ssiu-8 { + dmas =3D <&dmac0 0x1d71 0x2c>, <&dmac0 0x1d72 0x2d>, + <&dmac1 0x1d71 0x2c>, <&dmac1 0x1d72 0x2d>, + <&dmac2 0x1d71 0x2c>, <&dmac2 0x1d72 0x2d>, + <&dmac3 0x1d71 0x2c>, <&dmac3 0x1d72 0x2d>, + <&dmac4 0x1d71 0x2c>, <&dmac4 0x1d72 0x2d>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu21: ssiu-9 { + dmas =3D <&dmac0 0x1d73 0x2e>, <&dmac0 0x1d74 0x2f>, + <&dmac1 0x1d73 0x2e>, <&dmac1 0x1d74 0x2f>, + <&dmac2 0x1d73 0x2e>, <&dmac2 0x1d74 0x2f>, + <&dmac3 0x1d73 0x2e>, <&dmac3 0x1d74 0x2f>, + <&dmac4 0x1d73 0x2e>, <&dmac4 0x1d74 0x2f>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu22: ssiu-10 { + dmas =3D <&dmac0 0x1d75 0x30>, <&dmac0 0x1d76 0x31>, + <&dmac1 0x1d75 0x30>, <&dmac1 0x1d76 0x31>, + <&dmac2 0x1d75 0x30>, <&dmac2 0x1d76 0x31>, + <&dmac3 0x1d75 0x30>, <&dmac3 0x1d76 0x31>, + <&dmac4 0x1d75 0x30>, <&dmac4 0x1d76 0x31>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu23: ssiu-11 { + dmas =3D <&dmac0 0x1d77 0x32>, <&dmac0 0x1d78 0x33>, + <&dmac1 0x1d77 0x32>, <&dmac1 0x1d78 0x33>, + <&dmac2 0x1d77 0x32>, <&dmac2 0x1d78 0x33>, + <&dmac3 0x1d77 0x32>, <&dmac3 0x1d78 0x33>, + <&dmac4 0x1d77 0x32>, <&dmac4 0x1d78 0x33>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu30: ssiu-12 { + dmas =3D <&dmac0 0x1d79 0x34>, <&dmac0 0x1d7a 0x35>, + <&dmac1 0x1d79 0x34>, <&dmac1 0x1d7a 0x35>, + <&dmac2 0x1d79 0x34>, <&dmac2 0x1d7a 0x35>, + <&dmac3 0x1d79 0x34>, <&dmac3 0x1d7a 0x35>, + <&dmac4 0x1d79 0x34>, <&dmac4 0x1d7a 0x35>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu31: ssiu-13 { + dmas =3D <&dmac0 0x1d7b 0x36>, <&dmac0 0x1d7c 0x37>, + <&dmac1 0x1d7b 0x36>, <&dmac1 0x1d7c 0x37>, + <&dmac2 0x1d7b 0x36>, <&dmac2 0x1d7c 0x37>, + <&dmac3 0x1d7b 0x36>, <&dmac3 0x1d7c 0x37>, + <&dmac4 0x1d7b 0x36>, <&dmac4 0x1d7c 0x37>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu32: ssiu-14 { + dmas =3D <&dmac0 0x1d7d 0x38>, <&dmac0 0x1d7e 0x39>, + <&dmac1 0x1d7d 0x38>, <&dmac1 0x1d7e 0x39>, + <&dmac2 0x1d7d 0x38>, <&dmac2 0x1d7e 0x39>, + <&dmac3 0x1d7d 0x38>, <&dmac3 0x1d7e 0x39>, + <&dmac4 0x1d7d 0x38>, <&dmac4 0x1d7e 0x39>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu33: ssiu-15 { + dmas =3D <&dmac0 0x1d7f 0x3a>, <&dmac0 0x1d80 0x3b>, + <&dmac1 0x1d7f 0x3a>, <&dmac1 0x1d80 0x3b>, + <&dmac2 0x1d7f 0x3a>, <&dmac2 0x1d80 0x3b>, + <&dmac3 0x1d7f 0x3a>, <&dmac3 0x1d80 0x3b>, + <&dmac4 0x1d7f 0x3a>, <&dmac4 0x1d80 0x3b>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu40: ssiu-16 { + dmas =3D <&dmac0 0x1d81 0x3c>, <&dmac0 0x1d82 0x3d>, + <&dmac1 0x1d81 0x3c>, <&dmac1 0x1d82 0x3d>, + <&dmac2 0x1d81 0x3c>, <&dmac2 0x1d82 0x3d>, + <&dmac3 0x1d81 0x3c>, <&dmac3 0x1d82 0x3d>, + <&dmac4 0x1d81 0x3c>, <&dmac4 0x1d82 0x3d>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu41: ssiu-17 { + dmas =3D <&dmac0 0x1d83 0x3e>, <&dmac0 0x1d84 0x3f>, + <&dmac1 0x1d83 0x3e>, <&dmac1 0x1d84 0x3f>, + <&dmac2 0x1d83 0x3e>, <&dmac2 0x1d84 0x3f>, + <&dmac3 0x1d83 0x3e>, <&dmac3 0x1d84 0x3f>, + <&dmac4 0x1d83 0x3e>, <&dmac4 0x1d84 0x3f>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu42: ssiu-18 { + dmas =3D <&dmac0 0x1d85 0x40>, <&dmac0 0x1d86 0x41>, + <&dmac1 0x1d85 0x40>, <&dmac1 0x1d86 0x41>, + <&dmac2 0x1d85 0x40>, <&dmac2 0x1d86 0x41>, + <&dmac3 0x1d85 0x40>, <&dmac3 0x1d86 0x41>, + <&dmac4 0x1d85 0x40>, <&dmac4 0x1d86 0x41>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu43: ssiu-19 { + dmas =3D <&dmac0 0x1d87 0x42>, <&dmac0 0x1d88 0x43>, + <&dmac1 0x1d87 0x42>, <&dmac1 0x1d88 0x43>, + <&dmac2 0x1d87 0x42>, <&dmac2 0x1d88 0x43>, + <&dmac3 0x1d87 0x42>, <&dmac3 0x1d88 0x43>, + <&dmac4 0x1d87 0x42>, <&dmac4 0x1d88 0x43>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu50: ssiu-20 { + dmas =3D <&dmac0 0x1d89 0x44>, <&dmac0 0x1d8a 0x45>, + <&dmac1 0x1d89 0x44>, <&dmac1 0x1d8a 0x45>, + <&dmac2 0x1d89 0x44>, <&dmac2 0x1d8a 0x45>, + <&dmac3 0x1d89 0x44>, <&dmac3 0x1d8a 0x45>, + <&dmac4 0x1d89 0x44>, <&dmac4 0x1d8a 0x45>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu60: ssiu-21 { + dmas =3D <&dmac0 0x1d8b 0x46>, <&dmac0 0x1d8c 0x47>, + <&dmac1 0x1d8b 0x46>, <&dmac1 0x1d8c 0x47>, + <&dmac2 0x1d8b 0x46>, <&dmac2 0x1d8c 0x47>, + <&dmac3 0x1d8b 0x46>, <&dmac3 0x1d8c 0x47>, + <&dmac4 0x1d8b 0x46>, <&dmac4 0x1d8c 0x47>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu70: ssiu-22 { + dmas =3D <&dmac0 0x1d8d 0x48>, <&dmac0 0x1d8e 0x49>, + <&dmac1 0x1d8d 0x48>, <&dmac1 0x1d8e 0x49>, + <&dmac2 0x1d8d 0x48>, <&dmac2 0x1d8e 0x49>, + <&dmac3 0x1d8d 0x48>, <&dmac3 0x1d8e 0x49>, + <&dmac4 0x1d8d 0x48>, <&dmac4 0x1d8e 0x49>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu80: ssiu-23 { + dmas =3D <&dmac0 0x1d8f 0x4a>, <&dmac0 0x1d90 0x4b>, + <&dmac1 0x1d8f 0x4a>, <&dmac1 0x1d90 0x4b>, + <&dmac2 0x1d8f 0x4a>, <&dmac2 0x1d90 0x4b>, + <&dmac3 0x1d8f 0x4a>, <&dmac3 0x1d90 0x4b>, + <&dmac4 0x1d8f 0x4a>, <&dmac4 0x1d90 0x4b>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu90: ssiu-24 { + dmas =3D <&dmac0 0x1d91 0x4c>, <&dmac0 0x1d92 0x4d>, + <&dmac1 0x1d91 0x4c>, <&dmac1 0x1d92 0x4d>, + <&dmac2 0x1d91 0x4c>, <&dmac2 0x1d92 0x4d>, + <&dmac3 0x1d91 0x4c>, <&dmac3 0x1d92 0x4d>, + <&dmac4 0x1d91 0x4c>, <&dmac4 0x1d92 0x4d>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu91: ssiu-25 { + dmas =3D <&dmac0 0x1d93 0x4e>, <&dmac0 0x1d94 0x4f>, + <&dmac1 0x1d93 0x4e>, <&dmac1 0x1d94 0x4f>, + <&dmac2 0x1d93 0x4e>, <&dmac2 0x1d94 0x4f>, + <&dmac3 0x1d93 0x4e>, <&dmac3 0x1d94 0x4f>, + <&dmac4 0x1d93 0x4e>, <&dmac4 0x1d94 0x4f>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu92: ssiu-26 { + dmas =3D <&dmac0 0x1d95 0x50>, <&dmac0 0x1d96 0x51>, + <&dmac1 0x1d95 0x50>, <&dmac1 0x1d96 0x51>, + <&dmac2 0x1d95 0x50>, <&dmac2 0x1d96 0x51>, + <&dmac3 0x1d95 0x50>, <&dmac3 0x1d96 0x51>, + <&dmac4 0x1d95 0x50>, <&dmac4 0x1d96 0x51>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu93: ssiu-27 { + dmas =3D <&dmac0 0x1d97 0x52>, <&dmac0 0x1d98 0x53>, + <&dmac1 0x1d97 0x52>, <&dmac1 0x1d98 0x53>, + <&dmac2 0x1d97 0x52>, <&dmac2 0x1d98 0x53>, + <&dmac3 0x1d97 0x52>, <&dmac3 0x1d98 0x53>, + <&dmac4 0x1d97 0x52>, <&dmac4 0x1d98 0x53>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + }; + }; + wdt1: watchdog@14400000 { compatible =3D "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; reg =3D <0 0x14400000 0 0x400>; --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6ACB53ED13C; Thu, 19 Mar 2026 15:57:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935867; cv=none; b=CI0HN47st45k9tvHKUMDoFTY6hrliZkZ1P6k4vHmEUTHD8hjsz4NK/87A57RoqvuRSvZpbQIqr2CyKrb1TjKsvrVfz498QcYbbQNtGprhQwDtdKCMY7VMF/82utcwoTHVBLO+OROd6nLjmWAEgaaj/Wz77WLTJEprBYmImlgMQ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935867; c=relaxed/simple; bh=ZWNA9uavhP8FrqatXX9iuu73+hNnRk30MT/RFhXnJ7M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kYz7zoMe0T1w3p5mmLl+hYi7rTV5gCbhHwK8Zp5DluIuGgcjWAEcFmaq/fl/7Esp2mtIJBdAK+7jwAUwfDSp7i2UtWzjIc19VR6XVaPxBZ3V5zvGpIOLQ4//1AgIzOIYsT4dKcmssMCiRFlM+88W8Gx9Ad4LxRlLxIVOzFN0QNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: bK8mxX0GQ0iDeaLJAx0Vnw== X-CSE-MsgGUID: B9Xz0Yt3Qb+xxlN3XP0S9A== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:57:44 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 09A28401BC72; Fri, 20 Mar 2026 00:57:34 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 19/22] arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator Date: Thu, 19 Mar 2026 16:53:31 +0100 Message-ID: <20260319155334.51278-20-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the Renesas 5P35023 (Versa3) programmable clock generator on the I2C2 bus along with its 24MHz input clock (x2 oscillator) to feed the audio subsystem. The Versa3 provides the following audio-related clock outputs: - Output 0: 24MHz (reference) - Output 1: 12.288MHz (audio, 48kHz family) - Output 2: 11.2896MHz (audio, 44.1kHz family) - Output 3: 12.288MHz (audio) These clocks are required for the audio codec found on the RZ/G3E SMARC EVK. Signed-off-by: John Madieu --- .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index 3b571c096752..2f1548d78c2c 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -71,6 +71,12 @@ reg_vdd0p8v_others: regulator-vdd0p8v-others { regulator-always-on; }; =20 + x2: x2-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + /* 32.768kHz crystal */ x3: x3-clock { compatible =3D "fixed-clock"; @@ -124,6 +130,20 @@ raa215300: pmic@12 { =20 interrupts-extended =3D <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING= >; }; + + versa3: clock-generator@68 { + compatible =3D "renesas,5p35023"; + reg =3D <0x68>; + #clock-cells =3D <1>; + clocks =3D <&x2>; + + assigned-clocks =3D <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates =3D <24000000>, <12288000>, + <11289600>, <12288000>, + <25000000>, <25000000>; + }; }; =20 &i3c { --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9F4823F075A; Thu, 19 Mar 2026 15:57:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935876; cv=none; b=itP57RlWHvUgnklJ2XbWUB/2razMQDU0cugCzIWux/iTgmcBqiNdFV5TDkHWtDWVmQnzfXmgwUlf6U8yPFi7aVqAVml4NfJkWbx5wAuoOfy3NVdTgyRIDDSvu1zHj36XQ3aM6FwQfJy+FS++ZS4/NMtGeoYjMP8eQRUByJjaWlA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935876; c=relaxed/simple; bh=FDO0KhtbWTyzjQ7kQYEbbIB1sDBMg1RGeyaucjcHzHo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TskdAYeLIeyAGnORdX1uIFz8l/v2hodGy69tieH/vZMDoKyuHStJTCOR8HS1O3UAv43tD2Lxh7eJQAvzM1dV1BPZfil3jJ+A+XTmGndn+k94Ia7T6f2Zfo+eAgKim6BlcrLxX8FgECrpb57e2GN6eGbS2Vb3IABIWKXAqgHeC6c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 5JWdIweaSACC21HosvVOPA== X-CSE-MsgGUID: ERo1TbVaR8qHLveBOXzg2g== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:57:53 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1A093401BC72; Fri, 20 Mar 2026 00:57:44 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 20/22] arm64: dts: renesas: rzg3e-smarc-som: Add I2C1 support Date: Thu, 19 Mar 2026 16:53:32 +0100 Message-ID: <20260319155334.51278-21-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add and enable I2C1 controller support with pin configuration. The I2C1 bus is routed to the carrier board and used for peripherals such as the audio codec. Signed-off-by: John Madieu --- arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index 2f1548d78c2c..6fc6d5283eae 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -32,6 +32,7 @@ / { aliases { ethernet0 =3D ð0; ethernet1 =3D ð1; + i2c1 =3D &i2c1; i2c2 =3D &i2c2; mmc0 =3D &sdhi0; mmc2 =3D &sdhi2; @@ -112,6 +113,12 @@ &gpu { mali-supply =3D <®_vdd0p8v_others>; }; =20 +&i2c1 { + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + &i2c2 { pinctrl-0 =3D <&i2c2_pins>; pinctrl-names =3D "default"; @@ -246,6 +253,11 @@ ctrl { }; }; =20 + i2c1_pins: i2c1 { + pinmux =3D , /* SCL1 */ + ; /* SDA1 */ + }; + i2c2_pins: i2c { pinmux =3D , /* SCL2 */ ; /* SDA2 */ --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DF3633F1640; Thu, 19 Mar 2026 15:58:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935886; cv=none; b=XNDkvZaSVxuvby4c0cUZTrr1t8HDlP+xkssoib0evxi/TV6fnVty/tfkPfJ+2T8vHnXQkMnubNPCNRRJvyN+yvke+voIfM12urffS/P0ryFrzYJkHJje9hRXGsuFmhnLR7F2w6x30wIFTFZChpSCVX1c5y6RAPTFHJCYgEXlUmM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935886; c=relaxed/simple; bh=Ah49vEhMl7rAN9N1QGV+BlvsQ9aXxNRotog7gzbnPmg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZeR2/eIiq7zD5oN1x+h2OzkuIx30gY/yedC7623wcA+8mP/L2AbIvLRkklgAzX9bGCg8UlDzSIqXYFtZNOqyu8s6kqNCwQreLxLlEtFpmZqkoSBLczwdpYzgd1IWATt97h/egVIqA+MlddFgexFwdNsCxOaXdcaTnrxp5YGYRt8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: Dc3v/KmrQpKgNvwItauG0Q== X-CSE-MsgGUID: 0E+jKJjITYKu4nAY9hjBQw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:58:04 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6C04F401BC51; Fri, 20 Mar 2026 00:57:54 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 21/22] arm64: dts: renesas: rzg3e-smarc-som: add audio pinmux definitions Date: Thu, 19 Mar 2026 16:53:33 +0100 Message-ID: <20260319155334.51278-22-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pinmux definitions for SSI3/SSI4 audio interface on RZ/G3E SMARC SoM: - sound_clk_pins: AUDIO_CLKB and AUDIO_CLKC clock outputs - sound_pins: SSI3_SCK, SSI3_WS, SSI3_SDATA (playback) and SSI4_SDATA (capture) Signed-off-by: John Madieu --- arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index 6fc6d5283eae..d740e993a7d3 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -344,6 +344,18 @@ sd2-pwen { }; }; =20 + sound_clk_pins: sound_clk { + pinmux =3D , /* AUDIO_CLKB */ + ; /* AUDIO_CLKC */ + }; + + sound_pins: sound { + pinmux =3D , /* SSI3_SCK */ + , /* SSI3_WS */ + , /* SSI3_SDATA */ + ; /* SSI4_SDATA */ + }; + xspi_pins: xspi0 { pinmux =3D , /* XSPI0_IO0 */ , /* XSPI0_IO1 */ --=20 2.25.1 From nobody Mon Apr 6 10:44:15 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5E5073EC2C2; Thu, 19 Mar 2026 15:58:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935896; cv=none; b=WpAR+IG0kBgAO5OZh3ozLHZgTRDcBGzoIYVoLDL3Iaq6WwsdBWrKqdDSICQcg2zNVPhWdzIWwf3iNAe9Ih8xjaZLpRqKFRKOUEaDSbEzM6JQtQ4O4YqPjAgm3PTRw6r9bhKn+Lyucs0Eb68okNf2FybtMGwy8fw1EQbk7010Okk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773935896; c=relaxed/simple; bh=uduAbXx87Jb0f2ifVp148BdHVKrVEd7tXV03EPjNuAU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZgCqV6yIWCSjLCuTLwKPmX5imbvjFQL9N5wjyW5EDSoG6NheeMf60lT+enLcqMwNKW3ogsOWkVIrYCLzVYUVHACrhpfdt24PFkg4+OnN2xUXVtYhj/1ioGoIz2gsxQD/aF12lgEsDOw3+NKh+lxUpCujFfWk2e0hLQwq6pOxVsU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: zPZ+kk9pS+a8dOmMTwAFPA== X-CSE-MsgGUID: pRnLTKOCToKUWKyKadyiXQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 20 Mar 2026 00:58:13 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.35]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id ABB26401BC51; Fri, 20 Mar 2026 00:58:04 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH 22/22] arm64: dts: renesas: r9a09g047e57-smarc: add DA7212 audio codec support Date: Thu, 19 Mar 2026 16:53:34 +0100 Message-ID: <20260319155334.51278-23-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> References: <20260319155334.51278-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RZ/G3E SMARC board has a DA7212 audio codec connected via I2C1 for sound input/output using SSI3/SSI4 where: - The codec receives its master clock from the Versa3 clock generator present on the SoM - SSI4 shares clock pins with SSI3 to provide a separate data line for full-duplex audio capture. Enable audio support on RZ/G3E SMARC2 EVK boards with a DA7212 audio codec. Signed-off-by: John Madieu --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a09g047e57-smarc.dts index 696903dc7a63..62bc8e2a178a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -32,6 +32,37 @@ #include "rzg3e-smarc-som.dtsi" #include "renesas-smarc2.dtsi" =20 +/* + * SSI-DA7212 + * + * These commands are required when Playback/Capture + * + * amixer -q cset name=3D'Aux Switch' on + * amixer -q cset name=3D'Mixin Left Aux Left Switch' on + * amixer -q cset name=3D'Mixin Right Aux Right Switch' on + * amixer -q cset name=3D'ADC Switch' on + * amixer -q cset name=3D'Mixout Right Mixin Right Switch' off + * amixer -q cset name=3D'Mixout Left Mixin Left Switch' off + * amixer -q cset name=3D'Headphone Volume' 70% + * amixer -q cset name=3D'Headphone Switch' on + * amixer -q cset name=3D'Mixout Left DAC Left Switch' on + * amixer -q cset name=3D'Mixout Right DAC Right Switch' on + * amixer -q cset name=3D'DAC Left Source MUX' 'DAI Input Left' + * amixer -q cset name=3D'DAC Right Source MUX' 'DAI Input Right' + * amixer -q sset 'Mic 1 Amp Source MUX' 'MIC_P' + * amixer -q sset 'Mic 2 Amp Source MUX' 'MIC_P' + * amixer -q sset 'Mixin Left Mic 1' on + * amixer -q sset 'Mixin Right Mic 2' on + * amixer -q sset 'Mic 1' 90% on + * amixer -q sset 'Mic 2' 90% on + * amixer -q sset 'Lineout' 80% on + * amixer -q set "Headphone" 100% on + * + * When Capture chained with DVC, use this command to amplify sound + * amixer set 'DVC In',0 80% + * For playback, use: amixer set 'DVC Out',0 80% + */ + / { model =3D "Renesas SMARC EVK version 2 based on r9a09g047e57"; compatible =3D "renesas,smarc2-evk", "renesas,rzg3e-smarcm", @@ -55,6 +86,22 @@ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { gpios-states =3D <0>; states =3D <3300000 0>, <1800000 1>; }; + + sound_card: sound { + compatible =3D "audio-graph-card"; + + label =3D "snd-rzg3e"; + + dais =3D <&rsnd_port0>; /* DA7212 */ + }; +}; + +&audio_clkb { + clock-frequency =3D <11289600>; +}; + +&audio_clkc { + clock-frequency =3D <12288000>; }; =20 &canfd { @@ -99,6 +146,37 @@ &i2c0 { pinctrl-names =3D "default"; }; =20 +&i2c1 { + da7212: codec@1a { + compatible =3D "dlg,da7212"; + #sound-dai-cells =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x1a>; + + clocks =3D <&versa3 1>; + clock-names =3D "mclk"; + + dlg,micbias1-lvl =3D <2500>; + dlg,micbias2-lvl =3D <2500>; + dlg,dmic-data-sel =3D "lrise_rfall"; + dlg,dmic-samplephase =3D "between_clkedge"; + dlg,dmic-clkrate =3D <3000000>; + + VDDA-supply =3D <®_1p8v>; + VDDSP-supply =3D <®_3p3v>; + VDDMIC-supply =3D <®_3p3v>; + VDDIO-supply =3D <®_1p8v>; + + port { + da7212_endpoint: endpoint { + remote-endpoint =3D <&rsnd_endpoint0>; + mclk-fs =3D <256>; + }; + }; + }; +}; + &keys { pinctrl-0 =3D <&nmi_pins>; pinctrl-names =3D "default"; @@ -248,6 +326,42 @@ &sdhi1 { vqmmc-supply =3D <&vqmmc_sd1_pvdd>; }; =20 +&snd_rzg3e { + pinctrl-0 =3D <&sound_clk_pins &sound_pins>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + /* audio_clkout */ + #clock-cells =3D <0>; + clock-frequency =3D <11289600>; + + /* Multi DAI */ + #sound-dai-cells =3D <1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + rsnd_port0: port@0 { + reg =3D <0>; + rsnd_endpoint0: endpoint { + remote-endpoint =3D <&da7212_endpoint>; + + dai-format =3D "i2s"; + bitclock-master =3D <&rsnd_endpoint0>; + frame-master =3D <&rsnd_endpoint0>; + + playback =3D <&ssi3>, <&src1>, <&dvc1>; + capture =3D <&ssi4>, <&src0>, <&dvc0>; + }; + }; + }; +}; + +&ssi4 { + shared-pin; +}; + &xhci { pinctrl-0 =3D <&usb3_pins>; pinctrl-names =3D "default"; --=20 2.25.1