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Thu, 19 Mar 2026 07:15:18 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties Date: Thu, 19 Mar 2026 14:15:14 +0000 Message-ID: <20260319141515.2053556-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260319141515.2053556-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260319141515.2053556-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Document the pin configuration properties supported by the RZ/T2H pinctrl driver. The RZ/T2H SoC allows configuring several electrical characteristics through the DRCTLm (I/O Buffer Function Switching) registers. These registers control drive strength, bias configuration, Schmitt trigger input, and output slew rate. Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Reviewed-by: Linus Walleij --- v1->v2: - Updated commit description - Switched to using the standard drive-strength-microamp property name instead of a custom one - Added a description for slew-rate property --- .../pinctrl/renesas,r9a09g077-pinctrl.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pi= nctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pi= nctrl.yaml index f049013a4e0c..63993b20524f 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.y= aml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.y= aml @@ -83,6 +83,23 @@ definitions: input: true input-enable: true output-enable: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + slew-rate: + description: 0 is slow slew rate, 1 is fast slew rate + enum: [0, 1] + drive-strength-microamp: + description: | + Four discrete levels are supported (via registers DRCTLm), corre= sponding + to the following nominal values: + - 2500 (Low strength) + - 5000 (Middle strength) + - 9000 (High strength) + - 11800 (Ultra High strength) + enum: [2500, 5000, 9000, 11800] oneOf: - required: [pinmux] - required: [pins] --=20 2.53.0 From nobody Mon Apr 6 10:46:21 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EF2733A9DB for ; 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Thu, 19 Mar 2026 07:15:19 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:f7c0:c444:6359:4c21]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b5184957bsm17824618f8f.5.2026.03.19.07.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2026 07:15:19 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/2] pinctrl: renesas: rzt2h: Add pin configuration support Date: Thu, 19 Mar 2026 14:15:15 +0000 Message-ID: <20260319141515.2053556-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260319141515.2053556-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260319141515.2053556-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add pin configuration support for the Renesas RZ/T2H SoC. The RZ/T2H SoC allows configuring several electrical characteristics through the DRCTLm (I/O Buffer Function Switching) registers. These registers control bias configuration, Schmitt trigger input, output slew rate, and drive strength. Implement pinconf_ops to allow reading and updating these properties through the generic pin configuration framework. The implementation supports bias-disable, bias-pull-up, bias-pull-down, input-schmitt-enable, slew-rate, and drive-strength-microamp. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Reviewed-by: Linus Walleij --- v1->v2: - Updated commit description - Dropped 32 bit reg access for DRCTLm registers - Switched using to guard for locking in rzt2h_pinctrl_drctl_rmwq helper function - Dropped using RENESAS_RZT2H_PIN_CONFIG_DRIVE_STRENGTH instead switched to using the standard PIN_CONFIG_DRIVE_STRENGTH_UA --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 259 ++++++++++++++++++++++++ 1 file changed, 259 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index 5927744c7a96..6e60d1bb0c8b 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -7,6 +7,7 @@ * Copyright (C) 2025 Renesas Electronics Corporation. */ =20 +#include #include #include #include @@ -43,6 +44,7 @@ #define PMC(m) (0x400 + (m)) #define PFC(m) (0x600 + 8 * (m)) #define PIN(m) (0x800 + (m)) +#define DRCTL(n) (0xa00 + 8 * (n)) #define RSELP(m) (0xc00 + (m)) =20 #define PM_MASK GENMASK(1, 0) @@ -54,6 +56,16 @@ #define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8)) #define PFC_FUNC_INTERRUPT 0 =20 +#define DRCTL_PIN_SHIFT(pin) ((pin) << 3) +#define DRCTL_DRV_PIN_MASK(pin) (GENMASK_ULL(1, 0) << DRCTL_PIN_SHIFT(pin)) +#define DRCTL_PUD_PIN_MASK(pin) (GENMASK_ULL(3, 2) << DRCTL_PIN_SHIFT(pin)) +#define DRCTL_SMT_PIN_MASK(pin) (BIT_ULL(4) << DRCTL_PIN_SHIFT(pin)) +#define DRCTL_SR_PIN_MASK(pin) (BIT_ULL(5) << DRCTL_PIN_SHIFT(pin)) + +#define DRCTL_PUD_NONE 0 +#define DRCTL_PUD_PULL_UP 1 +#define DRCTL_PUD_PULL_DOWN 2 + /* * Use 16 lower bits [15:0] for pin identifier * Use 8 higher bits [23:16] for pin mux function @@ -91,6 +103,8 @@ struct rzt2h_pinctrl { atomic_t wakeup_path; }; =20 +static const unsigned int rzt2h_drive_strength_ua[] =3D { 2500, 5000, 9000= , 11800 }; + #define RZT2H_GET_BASE(pctrl, port) \ ((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1) =20 @@ -110,6 +124,37 @@ RZT2H_PINCTRL_REG_ACCESS(b, u8) RZT2H_PINCTRL_REG_ACCESS(w, u16) RZT2H_PINCTRL_REG_ACCESS(q, u64) =20 +static int rzt2h_drive_strength_ua_to_idx(unsigned int ua) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(rzt2h_drive_strength_ua); i++) { + if (rzt2h_drive_strength_ua[i] =3D=3D ua) + return i; + } + + return -EINVAL; +} + +static int rzt2h_drive_strength_idx_to_ua(unsigned int idx) +{ + if (idx >=3D ARRAY_SIZE(rzt2h_drive_strength_ua)) + return -EINVAL; + + return rzt2h_drive_strength_ua[idx]; +} + +static void rzt2h_pinctrl_drctl_rmwq(struct rzt2h_pinctrl *pctrl, + u32 port, u64 mask, u64 val) +{ + u32 offset =3D DRCTL(port); + u64 drctl; + + guard(raw_spinlock_irqsave)(&pctrl->lock); + drctl =3D rzt2h_pinctrl_readq(pctrl, port, offset) & ~mask; + rzt2h_pinctrl_writeq(pctrl, port, drctl | val, offset); +} + static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int of= fset) { u8 port =3D RZT2H_PIN_ID_TO_PORT(offset); @@ -443,6 +488,210 @@ static int rzt2h_dt_node_to_map(struct pinctrl_dev *p= ctldev, return ret; } =20 +static int rzt2h_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + struct rzt2h_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); + u32 port, param =3D pinconf_to_config_param(*config); + unsigned int arg; + u8 port_pin; + u64 drctl; + int ret; + + ret =3D rzt2h_validate_pin(pctrl, pin); + if (ret) + return ret; + + port =3D RZT2H_PIN_ID_TO_PORT(pin); + port_pin =3D RZT2H_PIN_ID_TO_PIN(pin); + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + drctl =3D rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); + arg =3D field_get(DRCTL_SR_PIN_MASK(port_pin), drctl); + break; + + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + drctl =3D rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); + arg =3D field_get(DRCTL_PUD_PIN_MASK(port_pin), drctl); + /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ + switch (arg) { + case DRCTL_PUD_NONE: + if (param !=3D PIN_CONFIG_BIAS_DISABLE) + return -EINVAL; + break; + case DRCTL_PUD_PULL_UP: + if (param !=3D PIN_CONFIG_BIAS_PULL_UP) + return -EINVAL; + arg =3D 1; + break; + case DRCTL_PUD_PULL_DOWN: + if (param !=3D PIN_CONFIG_BIAS_PULL_DOWN) + return -EINVAL; + arg =3D 1; + break; + default: + return -EINVAL; + } + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + drctl =3D rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); + arg =3D field_get(DRCTL_SMT_PIN_MASK(port_pin), drctl); + if (!arg) + return -EINVAL; + break; + + case PIN_CONFIG_DRIVE_STRENGTH_UA: { + int idx_drv; + + drctl =3D rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); + arg =3D field_get(DRCTL_DRV_PIN_MASK(port_pin), drctl); + idx_drv =3D rzt2h_drive_strength_idx_to_ua(arg); + if (idx_drv < 0) + return idx_drv; + arg =3D idx_drv; + break; + } + + default: + return -ENOTSUPP; + } + + *config =3D pinconf_to_config_packed(param, arg); + return 0; +} + +static int rzt2h_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct rzt2h_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); + unsigned int i; + u8 port_pin; + int ret; + + ret =3D rzt2h_validate_pin(pctrl, pin); + if (ret) + return ret; + + port_pin =3D RZT2H_PIN_ID_TO_PIN(pin); + + for (i =3D 0; i < num_configs; i++) { + u32 arg =3D pinconf_to_config_argument(configs[i]); + u32 param =3D pinconf_to_config_param(configs[i]); + u64 mask, val; + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + mask =3D DRCTL_SR_PIN_MASK(port_pin); + val =3D field_prep(mask, !!arg); + break; + + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: { + u32 bias; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + bias =3D DRCTL_PUD_NONE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + bias =3D DRCTL_PUD_PULL_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + bias =3D DRCTL_PUD_PULL_DOWN; + break; + } + + mask =3D DRCTL_PUD_PIN_MASK(port_pin); + val =3D field_prep(mask, bias); + break; + } + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask =3D DRCTL_SMT_PIN_MASK(port_pin); + val =3D field_prep(mask, !!arg); + break; + + case PIN_CONFIG_DRIVE_STRENGTH_UA: { + int drv_idx; + + drv_idx =3D rzt2h_drive_strength_ua_to_idx(arg); + if (drv_idx < 0) + return drv_idx; + + mask =3D DRCTL_DRV_PIN_MASK(port_pin); + val =3D field_prep(mask, drv_idx); + break; + } + + default: + return -ENOTSUPP; + } + + rzt2h_pinctrl_drctl_rmwq(pctrl, RZT2H_PIN_ID_TO_PORT(pin), mask, val); + } + + return 0; +} + +static int rzt2h_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + unsigned long prev_config =3D 0; + const unsigned int *pins; + unsigned int i, npins; + int ret; + + ret =3D pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i =3D 0; i < npins; i++) { + ret =3D rzt2h_pinctrl_pinconf_get(pctldev, pins[i], config); + if (ret) + return ret; + + /* Check config matches previous pins */ + if (i && prev_config !=3D *config) + return -ENOTSUPP; + + prev_config =3D *config; + } + + return 0; +} + +static int rzt2h_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int i, npins; + int ret; + + ret =3D pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i =3D 0; i < npins; i++) { + ret =3D rzt2h_pinctrl_pinconf_set(pctldev, pins[i], configs, + num_configs); + if (ret) + return ret; + } + + return 0; +} + static const struct pinctrl_ops rzt2h_pinctrl_pctlops =3D { .get_groups_count =3D pinctrl_generic_get_group_count, .get_group_name =3D pinctrl_generic_get_group_name, @@ -459,6 +708,15 @@ static const struct pinmux_ops rzt2h_pinctrl_pmxops = =3D { .strict =3D true, }; =20 +static const struct pinconf_ops rzt2h_pinctrl_confops =3D { + .is_generic =3D true, + .pin_config_get =3D rzt2h_pinctrl_pinconf_get, + .pin_config_set =3D rzt2h_pinctrl_pinconf_set, + .pin_config_group_set =3D rzt2h_pinctrl_pinconf_group_set, + .pin_config_group_get =3D rzt2h_pinctrl_pinconf_group_get, + .pin_config_config_dbg_show =3D pinconf_generic_dump_config, +}; + static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct rzt2h_pinctrl *pctrl =3D gpiochip_get_data(chip); @@ -890,6 +1148,7 @@ static int rzt2h_pinctrl_register(struct rzt2h_pinctrl= *pctrl) desc->npins =3D pctrl->data->n_port_pins; desc->pctlops =3D &rzt2h_pinctrl_pctlops; desc->pmxops =3D &rzt2h_pinctrl_pmxops; + desc->confops =3D &rzt2h_pinctrl_confops; desc->owner =3D THIS_MODULE; =20 pins =3D devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL); --=20 2.53.0