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charset="utf-8" From: Martin Schmiedel Adds support for the MBa93xxLA-MINI SBC. https://www.tq-group.com/en/products/tq-embedded/arm-architecture/mba93xxla= -mini/ Signed-off-by: Martin Schmiedel Signed-off-by: Alexander Stein Reviewed-by: Daniel Baluta Acked-by: Conor Dooley --- Changes in v2: * Collected Daniel's R-b Documentation/devicetree/bindings/arm/fsl.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index da2be7114f641..2c86d2381d95a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1558,11 +1558,14 @@ properties: soldered on an adapter board or for the connector variant MBa93xxLA mainboard is a single board computer using the soldera= ble SOM variant + MBa93xxLA-MINI mainboard is a single board computer using the so= lderable + SOM variant items: - enum: - tq,imx93-tqma9352-mba91xxca # TQ-Systems GmbH i.MX93 TQMa9= 3xxCA/LA SOM on MBa91xxCA - tq,imx93-tqma9352-mba93xxca # TQ-Systems GmbH i.MX93 TQMa9= 3xxCA/LA SOM on MBa93xxCA - tq,imx93-tqma9352-mba93xxla # TQ-Systems GmbH i.MX93 TQMa9= 3xxLA SOM on MBa93xxLA SBC + - tq,imx93-tqma9352-mba93xxla-mini # TQ-Systems GmbH i.MX93 = TQMa93xxLA SOM on MBa93xxLA-MINI SBC - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa9= 3xxCA/LA SOM - const: fsl,imx93 =20 --=20 2.43.0 From nobody Mon Apr 6 10:45:12 2026 Received: from www537.your-server.de (www537.your-server.de [188.40.3.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C63A3C3C01; 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charset="utf-8" From: Martin Schmiedel Add support for TQMa93xx module attached to MBa93xxLA-MINI board. TQMa93xx is a SOM series using i.MX93 SOC. The MBa93xxLA-MINI has a small form factor and is designed with WLAN, Bluetooth and WWAN applications in mind. Signed-off-by: Martin Schmiedel Signed-off-by: Alexander Stein Reviewed-by: Andrew Lunn --- Changes in v2: * Changed commit message to imperative form * Remove (currently unused) display and backlight nodes * Fix Ethernet PHY IRQ type to level low arch/arm64/boot/dts/freescale/Makefile | 1 + .../imx93-tqma9352-mba93xxla-mini.dts | 597 ++++++++++++++++++ 2 files changed, 598 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-= mini.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 31bc80586c682..db536522600ac 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -461,6 +461,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx93-phycore-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla-mini.dtb =20 imx93-tqma9352-mba91xxca-lvds-tm070jvhg33-dtbs :=3D imx93-tqma9352-mba91xx= ca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs :=3D imx93-tqma9352-mba91xxc= a.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dt= s b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts new file mode 100644 index 0000000000000..a27421d891c74 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Martin Schmiedel + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include "imx93-tqma9352.dtsi" + +/{ + model =3D "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA-MINI SBC"; + compatible =3D "tq,imx93-tqma9352-mba93xxla-mini", + "tq,imx93-tqma9352", "fsl,imx93"; + chassis-type =3D "embedded"; + + chosen { + stdout-path =3D &lpuart1; + }; + + aliases { + eeprom0 =3D &eeprom0; + ethernet0 =3D &eqos; + ethernet1 =3D &fec; + gpio0 =3D &gpio1; + gpio1 =3D &gpio2; + gpio2 =3D &gpio3; + gpio3 =3D &gpio4; + i2c0 =3D &lpi2c1; + i2c1 =3D &lpi2c2; + i2c2 =3D &lpi2c3; + i2c3 =3D &lpi2c4; + i2c4 =3D &lpi2c5; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + mmc2 =3D &usdhc3; + rtc0 =3D &pcf85063; + rtc1 =3D &bbnsm_rtc; + serial0 =3D &lpuart1; + serial1 =3D &lpuart2; + serial2 =3D &lpuart3; + serial3 =3D &lpuart4; + serial4 =3D &lpuart5; + serial5 =3D &lpuart6; + serial6 =3D &lpuart7; + serial7 =3D &lpuart8; + spi0 =3D &lpspi1; + spi1 =3D &lpspi2; + spi2 =3D &lpspi3; + spi3 =3D &lpspi4; + spi4 =3D &lpspi5; + spi5 =3D &lpspi6; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_MB"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_5v0_usb: regulator-5v0-usb { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_5V0_HUB"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&expander1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_12v0: regulator-12v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_12V"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + gpio =3D <&expander0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + status =3D "okay"; +}; + +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy_eqos>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos_phy>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <26 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&expander0 0 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <500000>; + reset-deassert-us =3D <50000>; + enet-phy-lane-no-swap; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel =3D ; + }; + }; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy_fec>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec_phy>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <27 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&expander0 1 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <500000>; + reset-deassert-us =3D <50000>; + enet-phy-lane-no-swap; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel =3D ; + }; + }; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + status =3D "okay"; +}; + +/* deactivated because pins are used for SDIO */ +&flexspi1 { + status =3D "disabled"; +}; + +&gpio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_m2_key_b>, <&pinctrl_m2_key_e>; + + gpio-line-names =3D + /* 00 */ "", "", "M2_KEYE_ALERT#", "", + /* 04 */ "", "", "M2_KEYE_UART_WAKE#", "BM1_M2_KEYE_SDIO_WAKE#", + /* 08 */ "", "", "", "BM2_M2_KEYE_SDIO_RST#", + /* 12 */ "M2_KEYB_WOWWAN#", "BM3_M2_KEYB_PEWAKE#", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio2>; + + gpio-line-names =3D + /* 00 */ "", "", "", "", + /* 04 */ "LVDS_RESET#", "LVDS_BLT_EN", "", "LVDS_PWR_EN", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "X1_9", "X1_19", "X1_15", "X1_11", + /* 20 */ "X1_13", "X1_7", "", "CAM_TRIGGER", + /* 24 */ "CAM_SYNC", "", "X1_5", "", + /* 28 */ "", "", "", ""; +}; + +&gpio4 { + gpio-line-names =3D + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "DSI_GPIO", "", ""; +}; + +&lpi2c3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_lpi2c3>; + pinctrl-1 =3D <&pinctrl_lpi2c3_gpio>; + scl-gpios =3D <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + expander0: gpio@70 { + compatible =3D "nxp,pca9538"; + reg =3D <0x70>; + gpio-controller; + #gpio-cells =3D <2>; + vcc-supply =3D <®_3v3>; + gpio-line-names =3D "ENET1_RESET#", "ENET2_RESET#", + "M2_KEYE_PERST#", "M2_KEYB_PERST#", + "M2_KEYE_W_DISABLE1#", "M2_KEYE_W_DISABLE2#", + "M2_KEYA_W_DISABLE1#", "12V_EN"; + }; + + expander1: gpio@71 { + compatible =3D "nxp,pca9538"; + reg =3D <0x71>; + gpio-controller; + #gpio-cells =3D <2>; + vcc-supply =3D <®_3v3>; + gpio-line-names =3D "USB_HUB_PWR", "DSI_RST#", + "CAM_PWR#", "CAMRST#", + "M2_KEYB_FULL_CARD_PWR_OFF#", "M2_KEYB_W_DISABLE2#", + "M2_KEYB_RST#", "M2_KEYB_DPR"; + + /* + * Controls the LTE card FULL_CARD_PWR_OFF pin which is low active + * as power down signal. The output-low states, the signal + * is inactive, e.g. not power down + */ + full-card-power-off-hog { + gpio-hog; + gpios =3D <4 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "M2_KEYB_FULL_CARD_PWR_OFF#"; + }; + + /* + * Controls the LTE card reset pin which is low active + * as reset signal. The output-low states, the signal + * is inactive, e.g. not in reset + */ + wlan-perst-hog { + gpio-hog; + gpios =3D <6 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "M2_KEYB_RST#"; + }; + }; +}; + +&lpspi6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpspi6>, <&pinctrl_lpspi6_cs>; + cs-gpios =3D <&gpio2 0 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&lpuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +/* disabled per default, console for M33 */ +&lpuart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart3>; + status =3D "disabled"; +}; + +/* disabled per default, used for bluetooth on M.2 slot */ +&lpuart7 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart7>; + uart-has-rtscts; + status =3D "disabled"; +}; + +&lpuart8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart8>; + status =3D "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# from SoM is connected on mainboard */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcf85063>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&tpm5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tpm5>; +}; + +&usbotg1 { + disable-over-current; + dr_mode =3D "peripheral"; + samsung,picophy-pre-emp-curr-control =3D <3>; + samsung,picophy-dc-vol-level-adjust =3D <7>; + status =3D "okay"; +}; + +&usbotg2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usbhub>; + #address-cells =3D <1>; + #size-cells =3D <0>; + disable-over-current; + dr_mode =3D "host"; + vbus-supply =3D <®_5v0_usb>; + samsung,picophy-pre-emp-curr-control =3D <3>; + samsung,picophy-dc-vol-level-adjust =3D <7>; + status =3D "okay"; + + hub_2_0: usb-hub@1 { + compatible =3D "usb424,2517"; + reg =3D <1>; + reset-gpios =3D <&gpio2 22 GPIO_ACTIVE_LOW>; + vdd-supply =3D <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + bus-width =3D <4>; + cd-gpios =3D <&gpio3 0 GPIO_ACTIVE_LOW>; + disable-wp; + no-sdio; + no-mmc; + vmmc-supply =3D <®_usdhc2_vmmc>; + status =3D "okay"; +}; + +&usdhc3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + bus-width =3D <4>; + non-removable; + vmmc-supply =3D <®_3v3>; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins =3D /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X5 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins =3D /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X5 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins =3D /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D /* HYS | PU | FSEL_0 | DSE no drive */ + , + /* PU | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D /* HYS | PU | FSEL_0 | DSE no drive */ + , + /* PU | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins =3D /* HYS | PD | FSEL_2 | DSE X4 */ + , + , + , + , + , + , + ; + }; + + pinctrl_jtag: jtaggrp { + fsl,pins =3D , + , + , + ; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins =3D /* SION | HYS | OD | FSEL_3 | DSE X4 */ + , + ; + }; + + pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp { + fsl,pins =3D /* SION | HYS | OD | FSEL_3 | DSE X4 */ + , + ; + }; + + pinctrl_lpspi6: lpspi6grp { + fsl,pins =3D /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X4 */ + , + ; + }; + + pinctrl_lpspi6_cs: lpspi6csgrp { + fsl,pins =3D /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_m2_key_b: m2keybgrp { + fsl,pins =3D , + ; + }; + + pinctrl_m2_key_e: m2keyegrp { + fsl,pins =3D , + , + , + ; + }; + + /*CAM_MCLK, DSI_GPIO, CAM_TRIGGER, CAM_SYNC*/ + pinctrl_mipi_csi_dsi: mipi_csi_dsigrp { + fsl,pins =3D , + , + , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_tpm5: tpm5grp { + fsl,pins =3D ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_uart7: uart7grp { + fsl,pins =3D , + , + , + ; + }; + + pinctrl_uart8: uart8grp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_usbhub: usbhubgrp { + fsl,pins =3D /* HYS | PD | FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins =3D /* PD | FSEL_3 | DSE X5 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + /* HYS | PU | FSEL_3 | DSE X3 */ + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; 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Thu, 19 Mar 2026 13:50:22 +0100 From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Shawn Guo Cc: Martin Schmiedel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com, Alexander Stein Subject: [PATCH v2 3/3] arm64: dts: freescale: imx93-tqma9352-mba93xxla-mini: Add WLAN/BT overlay Date: Thu, 19 Mar 2026 13:50:10 +0100 Message-ID: <20260319125013.2421621-4-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260319125013.2421621-1-alexander.stein@ew.tq-group.com> References: <20260319125013.2421621-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: Clear (ClamAV 1.4.3/27945/Thu Mar 19 07:24:38 2026) Content-Type: text/plain; charset="utf-8" From: Martin Schmiedel This overlay enables the LWB5+ M.2 wlan module from ezurio. Signed-off-by: Martin Schmiedel Signed-off-by: Alexander Stein --- Changes in v2: * None arch/arm64/boot/dts/freescale/Makefile | 4 +++ ...3-tqma9352-mba93xxla-mini-ezurio-wlan.dtso | 35 +++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-= mini-ezurio-wlan.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index db536522600ac..9a55a86ad385b 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -495,6 +495,10 @@ imx8mm-kontron-bl-lte-dtbs :=3D imx8mm-kontron-bl.dtb= imx8mm-kontron-bl-lte.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-dl.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-bl-lte.dtb =20 +imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs +=3D imx93-tqma9352-mba93xx= la-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo + +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb + imx8mm-venice-gw72xx-0x-imx219-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-rpidsi.dtbo imx8mm-venice-gw72xx-0x-rs232-rts-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb im= x8mm-venice-gw72xx-0x-rs232-rts.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini-ez= urio-wlan.dtso b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-min= i-ezurio-wlan.dtso new file mode 100644 index 0000000000000..12a14d8711035 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini-ezurio-wl= an.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Martin Schmiedel + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&lpuart7 { + status =3D "okay"; + + bluetooth { + compatible =3D "brcm,bcm4329-bt"; + vbat-supply =3D <®_3v3>; + vddio-supply =3D <®_3v3>; + shutdown-gpios =3D <&expander0 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + brcmf_sdio: wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + reset-gpios =3D <&gpio1 11 GPIO_ACTIVE_LOW>; + }; +}; --=20 2.43.0