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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 724464126F85; Thu, 19 Mar 2026 18:17:25 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, robin.murphy@arm.com, Frank.Li@kernel.org Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, Jun Guo Subject: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies Date: Thu, 19 Mar 2026 18:17:21 +0800 Message-Id: <20260319101723.246539-2-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260319101723.246539-1-jun.guo@cixtech.com> References: <20260319101723.246539-1-jun.guo@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C6:EE_|TY2PPFCC803ADFE:EE_ X-MS-Office365-Filtering-Correlation-Id: 25c7da9d-f5a3-4e83-cf54-08de85a0b858 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700016|921020|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: LoRNgA1FTMn+qTWBbK+C6xWBscNl2VnNw92dj6clCv3zyj3qSnnNujJ+WGa1/LMGuAQ4mZ1VQI4p2V2Dtqk4HPW8gZ0jx1GTyelh7Ny4WcJ3UVioYxQn1m82zixmV9VWwQfUqXvsiL/pIUAcsthFPYkyf3E6U5ckJHNT8hsOk0gdgNAfydt/5gZ347IocalNK4tjQqYWegRFm0CXeyDFI0HWQ+UEI+fytjmE/c1neeHvwz5kngp5+yUTyR7XuLGeco+IfTNUhZJdvyG4puxWvrt6Js5+uCmGT42OHWm33KPeHI1AsseJIqpV6So75GAFij+WWlMxacEkJLU9v4/h1bVjncqYA+KkO9KraSjrQdBrL20nMH0CrYpkPRjva6V04HCKzDS1ld/Q5eecYiC4LN14XEU4zWBVtm7D8K7VK8uyRXZrvKhIPjxmgbm+5BaE58PhDtWxCII0fGfARMQCM2aLqiv71jtyviFcdHI37WIQj5t3OxSBzIA2807C/Eg/wHShj6h29DP7671KtG3oZ0QoipwxHM+wasGKh7yGNaqVBO0TfnHRsYNOWn5lVX78riZ/0L9QGZAzzYPft5ql26LMVREI+UtaxVZGZVUokXxXMN8mdGM/ZBFuP1CG83Li1ASR7Kk5AfoU8lrhgXD7XX3N6VouMifvJyVVsDEJiuLI428FD9RapOe4zeC4D1AKww3Y8MQumasfUQ6BIfcETr7LTCxtpgCRTcICN8AkrmWABt/s2Yitkr9jrluIDByVvdDHfSJQO3cu/X84B9E9WGinM/CsSrumxcSZLx4xig/rOIpbO4w/EdYNczLl5cvC X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700016)(921020)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5aKMEUoSa0zK+C7JfecXm/ii5iR/IqnTwijmtbfr9l4X5/8g5zSsMppqOf2+vdFnzyaGUreAyZvoeqv30P5aNNJxJbvPhYjI6eVwAplAeLrJPzPquDOmS53/645/L8O891u2WJ/UGHcGG+DjfRzg0ezszW41m7uZRpBk1erld28twJVsLdQZFU1AFt2y3AaeLmQjPtCctMEpNaGt9DJa79VAfoknolQWvQKsPOb2iutyo3QXmT4CztCILmci09jgXBxdFSZL7g/cVCpDRdrn4w4eSkPg/taAsULaP5Ajr1NUNveUWZUaDmSfRZ2UMC9wz/v5vmGlP7oqSmXhfQ53jSEq8bQPmTwj6UJ+6/OTJhWiK+4VaI0KeTR46tpnoJA5ZeCZceQheTsFyc5Z6Kv7+cqe29isQBENpRchLQmxdTn/DfqxN9T8L5cOOq8I56/C X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2026 10:17:26.5173 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25c7da9d-f5a3-4e83-cf54-08de85a0b858 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C6.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY2PPFCC803ADFE Content-Type: text/plain; charset="utf-8" Update the DMA-350 DT binding to match the current driver behavior. Allow both: - "arm,dma-350" as the generic compatible, and - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage. Also document interrupt topology variants supported by hardware integration: - one combined interrupt for all channels, or - one interrupt per channel (up to 8 channels). This patch is Assisted-by: Cursor: GPT-5.3 Codex. Signed-off-by: Jun Guo Link: https://lore.kernel.org/r/20251216123026.3519923-2-jun.guo@cixtech.com --- .../devicetree/bindings/dma/arm,dma-350.yaml | 31 +++++++++++++------ 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Docum= entation/devicetree/bindings/dma/arm,dma-350.yaml index 429f682f15d8..3639ce0d5054 100644 --- a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml +++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml @@ -14,7 +14,11 @@ allOf: =20 properties: compatible: - const: arm,dma-350 + oneOf: + - const: arm,dma-350 + - items: + - const: cix,sky1-dma-350 + - const: arm,dma-350 =20 reg: items: @@ -22,15 +26,22 @@ properties: =20 interrupts: minItems: 1 - items: - - description: Channel 0 interrupt - - description: Channel 1 interrupt - - description: Channel 2 interrupt - - description: Channel 3 interrupt - - description: Channel 4 interrupt - - description: Channel 5 interrupt - - description: Channel 6 interrupt - - description: Channel 7 interrupt + maxItems: 8 + description: | + The DMA controller may be configured with separate interrupts for ea= ch channel, + or with a single combined interrupt for all channels, depending on t= he SoC integration. + oneOf: + - items: + - description: Channel 0 interrupt + - description: Channel 1 interrupt + - description: Channel 2 interrupt + - description: Channel 3 interrupt + - description: Channel 4 interrupt + - description: Channel 5 interrupt + - description: Channel 6 interrupt + - description: Channel 7 interrupt + - items: + - description: Combined interrupt shared by all channels =20 "#dma-cells": const: 1 --=20 2.34.1 From nobody Mon Apr 6 10:31:53 2026 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023091.outbound.protection.outlook.com [40.107.44.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF6593B2FE6; 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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id D55BA4126F90; Thu, 19 Mar 2026 18:17:25 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, robin.murphy@arm.com, Frank.Li@kernel.org Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, Jun Guo Subject: [PATCH v3 2/3] dma: arm-dma350: support combined IRQ mode with runtime IRQ topology detection Date: Thu, 19 Mar 2026 18:17:22 +0800 Message-Id: <20260319101723.246539-3-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260319101723.246539-1-jun.guo@cixtech.com> References: <20260319101723.246539-1-jun.guo@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CB:EE_|TYPPR06MB8242:EE_ X-MS-Office365-Filtering-Correlation-Id: 83a5272c-f57b-4a46-e01d-08de85a0b8bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|7416014|82310400026|22082099003|56012099003|18002099003|921020; X-Microsoft-Antispam-Message-Info: l7J4t25awIjdC53/K2ehs9OK2gFXLGxxpaLwCNdZDef/BufoWSOpp4GYMeG6hEv+YDGQV85OOp/v+mo1lWSF3Miaa/wsn0pJIhoRaVzaKY3SA/+t0njupzKVCAAFK5WzQZJUobLFliTsCJIbClcXCh82z/Fp7wP5JEePV5M/4zpIsJOd43whsJWxelELG0+jTtvtbD50qJJEUSu9kdIYILqtjFhx8SczY1a4dKh18BcAcFaEWB+LD5m9gIZmcMRsuwoNPWsWpKwGnWccugSbBAonjaU8Qe2Hp62/bq2PtxDb0W31b2CMvXaTTpHc1L9CS2rjWTAcZS7hj9u2rsccGmknuN5BNSbAdbJHxEfjwn529ppC3WgizuvhsenZM7UQkGuN52CGHKnV+YkHAigXATSZ1NMQMDLBHBkWxVj5RLX8Xmz7HCLBIZoWMmjZdvh2OGuV16vVvLNHgbgNEE9mxb7K7+tLfIGzttSvcXQOn8d+BxlB/PmGcV0EeIB8A+LsgMtXcRmM8MphMM+sRNewT5OjJPlgIXZtVKeSfd7YlkabsxaQq7p7ijRSTBldKt7D2X56XQUmez3bO+RV6TxZvYF9JesXT5eR2lGP7HecUT+m7SgQpGrW3wZA+9dHWY3f90yowtpPtkrhzX5HuVc9Hhx3CshIxXioBee45plcEm4MMlUGQLNOk+Pdkk/rZNgfeafj1z0Ztpr53hdkpJdPc/3gHSgPBUhCamlkyyXoT7rbCydlHTBiFje2q4mbs3synOE7iPxeH2V8VvkwC1SHQkp+nzlRI0M41JlvHijUw+k4FdLlReP5oXgox1KoFtOo X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(7416014)(82310400026)(22082099003)(56012099003)(18002099003)(921020);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vv5Kt8ebs3wVfads/AybMJJph5BK9pTN+72A8N7jYJGR1maIRJqWJu2GgDGh5D2Ku1BFSvVZEPVRQN4pYwyEKMZwc/Cn94Xc3z75JeFzTIEmUXOlGNeo+zvi45hXDa+Mqd3jt+VqNqtAgNJMgPy8grwflqu554FNYyDo5yK3r8OOJKaxFjerTeP6P1WUKdfFRF+F3H3SE/K2GkEB+KfGL6kYXXKC6GnEGcZKm6Ffufs8EcusSFlPs8T5eLsFm6LRqkUwCaeb7TjqjfiqjxyLPCZg0Tc9K38Rn9rHegL20wtel2CvpQdFNtPlGnqAI1mlhpBjcXIBW1DU2yVLQG72g1QcutDUpvYCkuUy/8tFOOCjOYLuHRvrmFqM/SAPdoaxBPkV1xZI2YQgvdJigosRUcx9HHSUs6CkfzTwwVtKL5aulFUQwAZJRm3KY1ZHgZo+ X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2026 10:17:27.1173 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83a5272c-f57b-4a46-e01d-08de85a0b8bb X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CB.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYPPR06MB8242 Content-Type: text/plain; charset="utf-8" DMA-350 can be integrated with either per-channel IRQ lines or a single combined IRQ line. Add support for both layouts in a unified way. Detect IRQ topology at probe time via platform_irq_count(), then: - request one global IRQ and enable DMANSECCTRL.INTREN_ANYCHINTR for combined mode, or - request per-channel IRQs for channel mode. Refactor IRQ completion/error handling into a shared channel handler used by both global and per-channel IRQ paths, and guard against IRQs arriving without an active descriptor. This patch is Assisted-by: Cursor: GPT-5.3 Codex. Signed-off-by: Jun Guo Link: https://lore.kernel.org/r/20251216123026.3519923-3-jun.guo@cixtech.com --- drivers/dma/arm-dma350.c | 165 +++++++++++++++++++++++++++++++++------ 1 file changed, 139 insertions(+), 26 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 84220fa83029..2cf6f783b44f 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -14,6 +14,7 @@ #include "virt-dma.h" =20 #define DMAINFO 0x0f00 +#define DRIVER_NAME "arm-dma350" =20 #define DMA_BUILDCFG0 0xb0 #define DMA_CFG_DATA_WIDTH GENMASK(18, 16) @@ -142,6 +143,9 @@ #define LINK_LINKADDR BIT(30) #define LINK_LINKADDRHI BIT(31) =20 +/* DMA NONSECURE CONTROL REGISTER */ +#define DMANSECCTRL 0x20c +#define INTREN_ANYCHINTR_EN BIT(0) =20 enum ch_ctrl_donetype { CH_CTRL_DONETYPE_NONE =3D 0, @@ -192,6 +196,7 @@ struct d350_chan { =20 struct d350 { struct dma_device dma; + void __iomem *base; int nchan; int nreq; struct d350_chan channels[] __counted_by(nchan); @@ -461,18 +466,40 @@ static void d350_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&dch->vc.lock, flags); } =20 -static irqreturn_t d350_irq(int irq, void *data) +static void d350_handle_chan_irq(struct d350_chan *dch, struct device *dev, + int chan_id, u32 ch_status) { - struct d350_chan *dch =3D data; - struct device *dev =3D dch->vc.chan.device->dev; - struct virt_dma_desc *vd =3D &dch->desc->vd; - u32 ch_status; + struct virt_dma_desc *vd; + bool intr_done =3D ch_status & CH_STAT_INTR_DONE; + bool intr_err =3D ch_status & CH_STAT_INTR_ERR; =20 - ch_status =3D readl(dch->base + CH_STATUS); - if (!ch_status) - return IRQ_NONE; + if (!intr_done && !intr_err) { + if (chan_id >=3D 0) + dev_warn(dev, "Channel %d unexpected IRQ: 0x%08x\n", + chan_id, ch_status); + else + dev_warn(dev, "Unexpected IRQ source? 0x%08x\n", ch_status); + writel_relaxed(ch_status, dch->base + CH_STATUS); + return; + } + + writel_relaxed(ch_status, dch->base + CH_STATUS); + + spin_lock(&dch->vc.lock); + if (!dch->desc) { + if (chan_id >=3D 0) + dev_warn(dev, + "Channel %d IRQ without active descriptor: 0x%08x\n", + chan_id, ch_status); + else + dev_warn(dev, "IRQ without active descriptor: 0x%08x\n", + ch_status); + spin_unlock(&dch->vc.lock); + return; + } =20 - if (ch_status & CH_STAT_INTR_ERR) { + vd =3D &dch->desc->vd; + if (intr_err) { u32 errinfo =3D readl_relaxed(dch->base + CH_ERRINFO); =20 if (errinfo & (CH_ERRINFO_AXIRDPOISERR | CH_ERRINFO_AXIRDRESPERR)) @@ -483,14 +510,10 @@ static irqreturn_t d350_irq(int irq, void *data) vd->tx_result.result =3D DMA_TRANS_ABORTED; =20 vd->tx_result.residue =3D d350_get_residue(dch); - } else if (!(ch_status & CH_STAT_INTR_DONE)) { - dev_warn(dev, "Unexpected IRQ source? 0x%08x\n", ch_status); } - writel_relaxed(ch_status, dch->base + CH_STATUS); =20 - spin_lock(&dch->vc.lock); vchan_cookie_complete(vd); - if (ch_status & CH_STAT_INTR_DONE) { + if (intr_done) { dch->status =3D DMA_COMPLETE; dch->residue =3D 0; d350_start_next(dch); @@ -499,6 +522,44 @@ static irqreturn_t d350_irq(int irq, void *data) dch->residue =3D vd->tx_result.residue; } spin_unlock(&dch->vc.lock); +} + +static irqreturn_t d350_global_irq(int irq, void *data) +{ + struct d350 *dmac =3D (struct d350 *)data; + irqreturn_t ret =3D IRQ_NONE; + int i; + + (void)irq; + + for (i =3D 0; i < dmac->nchan; i++) { + struct d350_chan *dch =3D &dmac->channels[i]; + u32 ch_status; + + ch_status =3D readl(dch->base + CH_STATUS); + if (!ch_status) + continue; + + ret =3D IRQ_HANDLED; + d350_handle_chan_irq(dch, dmac->dma.dev, i, ch_status); + } + + return ret; +} + +static irqreturn_t d350_channel_irq(int irq, void *data) +{ + struct d350_chan *dch =3D data; + struct device *dev =3D dch->vc.chan.device->dev; + u32 ch_status; + + (void)irq; + + ch_status =3D readl(dch->base + CH_STATUS); + if (!ch_status) + return IRQ_NONE; + + d350_handle_chan_irq(dch, dev, -1, ch_status); =20 return IRQ_HANDLED; } @@ -506,10 +567,18 @@ static irqreturn_t d350_irq(int irq, void *data) static int d350_alloc_chan_resources(struct dma_chan *chan) { struct d350_chan *dch =3D to_d350_chan(chan); - int ret =3D request_irq(dch->irq, d350_irq, IRQF_SHARED, - dev_name(&dch->vc.chan.dev->device), dch); - if (!ret) - writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN); + int ret =3D 0; + + if (dch->irq >=3D 0) { + ret =3D request_irq(dch->irq, d350_channel_irq, IRQF_SHARED, + dev_name(&dch->vc.chan.dev->device), dch); + if (ret) { + dev_err(chan->device->dev, "Failed to request IRQ %d\n", dch->irq); + return ret; + } + } + + writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN); =20 return ret; } @@ -519,18 +588,21 @@ static void d350_free_chan_resources(struct dma_chan = *chan) struct d350_chan *dch =3D to_d350_chan(chan); =20 writel_relaxed(0, dch->base + CH_INTREN); - free_irq(dch->irq, dch); + if (dch->irq >=3D 0) { + free_irq(dch->irq, dch); + dch->irq =3D -EINVAL; + } vchan_free_chan_resources(&dch->vc); } =20 static int d350_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct d350 *dmac; + struct d350 *dmac =3D NULL; void __iomem *base; u32 reg; - int ret, nchan, dw, aw, r, p; - bool coherent, memset; + int ret, nchan, dw, aw, r, p, irq_count; + bool coherent, memset, combined_irq; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -556,6 +628,7 @@ static int d350_probe(struct platform_device *pdev) return -ENOMEM; =20 dmac->nchan =3D nchan; + dmac->base =3D base; =20 reg =3D readl_relaxed(base + DMAINFO + DMA_BUILDCFG1); dmac->nreq =3D FIELD_GET(DMA_CFG_NUM_TRIGGER_IN, reg); @@ -582,12 +655,46 @@ static int d350_probe(struct platform_device *pdev) dmac->dma.device_issue_pending =3D d350_issue_pending; INIT_LIST_HEAD(&dmac->dma.channels); =20 + irq_count =3D platform_irq_count(pdev); + if (irq_count < 0) + return dev_err_probe(dev, irq_count, + "Failed to count interrupts\n"); + + if (irq_count =3D=3D 1) { + combined_irq =3D true; + } else if (irq_count >=3D nchan) { + combined_irq =3D false; + } else { + return dev_err_probe(dev, -EINVAL, + "Invalid IRQ count %d for %d channels\n", + irq_count, nchan); + } + + if (combined_irq) { + int host_irq =3D platform_get_irq(pdev, 0); + + if (host_irq < 0) + return dev_err_probe(dev, host_irq, + "Failed to get IRQ\n"); + + ret =3D devm_request_irq(&pdev->dev, host_irq, d350_global_irq, + IRQF_SHARED, DRIVER_NAME, dmac); + if (ret) + return dev_err_probe( + dev, ret, + "Failed to request the combined IRQ %d\n", + host_irq); + /* Combined Non-Secure Channel Interrupt Enable */ + writel_relaxed(INTREN_ANYCHINTR_EN, dmac->base + DMANSECCTRL); + } + /* Would be nice to have per-channel caps for this... */ memset =3D true; for (int i =3D 0; i < nchan; i++) { struct d350_chan *dch =3D &dmac->channels[i]; =20 dch->base =3D base + DMACH(i); + dch->irq =3D -EINVAL; writel_relaxed(CH_CMD_CLEAR, dch->base + CH_CMD); =20 reg =3D readl_relaxed(dch->base + CH_BUILDCFG1); @@ -595,10 +702,15 @@ static int d350_probe(struct platform_device *pdev) dev_warn(dev, "No command link support on channel %d\n", i); continue; } - dch->irq =3D platform_get_irq(pdev, i); - if (dch->irq < 0) - return dev_err_probe(dev, dch->irq, - "Failed to get IRQ for channel %d\n", i); + + if (!combined_irq) { + dch->irq =3D platform_get_irq(pdev, i); + if (dch->irq < 0) + return dev_err_probe( + dev, dch->irq, + "Failed to get IRQ for channel %d\n", + i); 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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 45C674126F92; Thu, 19 Mar 2026 18:17:26 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, robin.murphy@arm.com, Frank.Li@kernel.org Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, Jun Guo Subject: [PATCH v3 3/3] arm64: dts: cix: add DT nodes for DMA Date: Thu, 19 Mar 2026 18:17:23 +0800 Message-Id: <20260319101723.246539-4-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260319101723.246539-1-jun.guo@cixtech.com> References: <20260319101723.246539-1-jun.guo@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CC:EE_|KUXPR06MB8008:EE_ X-MS-Office365-Filtering-Correlation-Id: f4610684-c8fd-498c-c963-08de85a0b8d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700016|7416014|22082099003|56012099003|18002099003|921020; X-Microsoft-Antispam-Message-Info: OC8VFPAwIy117ZjG5uqWzrqbKOpMFfI05hnz4bF6WXyzy+ZXidMbLwJdICe8WErYh0sXOTjNmHmFkf4eyKkBiimePZ9CVBS4yE+UrlbCV6FUiyw23kjpJjQ9t3wE5vmQNz7WFgbANO2I5BN0VZgs95E+gGweojsNazYczs0DdmKJxBUWNipC6yheduSk0EkJ1zAq4TNOAKJifLL7skYEGmbqMd0dXHTUo/gTU6/UIKahqxp4bDRAPysJ7whWILa3fnFgswlWgmFbFeugt7SH5fndY+j9sssBNqL/nNERJ7B52HFec+tA7FjnBvLIkq5ou0vH3kxXH1ZU68ZwcNmbltfMPt+e1xndhrE+FtD6edI8yLwdb5LL+kM4LZgzHTVrb9BAc1bQsFnQSAl5j5/JObEb5x8aprRMbv4Uvy+nn3H0/Ub1qCknbuZXJdvDZrOv0Yq3VmdSMvJNA8n7DrXROJgRn7V1tr3PZOUvelOCSh9usiytEQKCDWHMTsAf+E4nxGqwtORM2WMRG4+Cs/mvt9VVcaLBLWWND57D4RE1bPFOhsC8b9QvMV6/e/lWGXc/P7zSm7ixucYEZXBiDdR1Xok5Uo3IbSUCibqXj9t3TS2pxyBqt6fJEDvNPdM5uRucHuhFrHsGGzOzP2B7wzPV4+Q2ezi+89wuYfhFUX3MIUa+qlJ6mZJF8lLwXfgT9pM3v0EO/x6yOPqGlwbRpOHPvhQgoxEyBSI3p9W4F50UsN+RRipgct7hHSlmK19THlKOOABAbPCSlK99zuOxaOc1orGsMGpj7gXfxfafxkdcole4fvFniWb7i1ezlRpNPicy X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700016)(7416014)(22082099003)(56012099003)(18002099003)(921020);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Cgz2nTyihN7Pg2P6yluiLK3zcHTyd7/7JzEpK+BBXUqK3SPIMm4ssVsfuIZn/gRxU6yrw5VePBBR+RGlR8KA/dVHI9rTnodXbGn/xIhW5bLcHzk6fU8a380Mn9d0fyoZrQ6BsRHPAMK3Q/9aChDnliP3cq4nNV6HXOgpwZhbjVAminNZemjyOYS6NpyXb7LVHlqDxALueXVRrbvWI8VTmWFL/RWOQYg1HmGmPuoxkEPK00uaa97FXonggq3GhOkxwvoLkkuf1uhohGppnN5x6eyQEdNJPCFowd6BZ9xc5pXeWqKRTG41JoFRxSjAcXyGd/cZUNdWpYNxsWQbPhwb+Hk97MIwz6bop5enUrB4MXINU9uNkOvn8kbaq7br8IaXS/BSoZiQukYpy/Cs5n9LP6MQg3U2qUz3WkwxyCDHSrGRzqiJ3SgQlTIFUcTN4s7A X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2026 10:17:27.3475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4610684-c8fd-498c-c963-08de85a0b8d6 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CC.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KUXPR06MB8008 Content-Type: text/plain; charset="utf-8" Add the device tree node for the dma controller of the CIX SKY1 SoC. Signed-off-by: Jun Guo Link: https://lore.kernel.org/r/20251216123026.3519923-4-jun.guo@cixtech.com --- arch/arm64/boot/dts/cix/sky1.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 210739beac6d..1185c99d8d9d 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -480,6 +480,13 @@ iomuxc: pinctrl@4170000 { reg =3D <0x0 0x04170000 0x0 0x1000>; }; =20 + fch_dmac: dma-controller@4190000 { + compatible =3D "cix,sky1-dma-350", "arm,dma-350"; + reg =3D <0x0 0x4190000 0x0 0x10000>; + interrupts =3D ; + #dma-cells =3D <1>; + }; + mbox_ap2se: mailbox@5060000 { compatible =3D "cix,sky1-mbox"; reg =3D <0x0 0x05060000 0x0 0x10000>; --=20 2.34.1