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Thu, 19 Mar 2026 00:44:03 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea Subject: [PATCH net-next 1/3] net/mlx5e: Move RX MPWQE slowpath fields into a separate struct Date: Thu, 19 Mar 2026 09:43:36 +0200 Message-ID: <20260319074338.24265-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260319074338.24265-1-tariqt@nvidia.com> References: <20260319074338.24265-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC0:EE_|CY3PR12MB9678:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b1cf3cb-b23e-47be-ab45-08de858b581a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: DtZAfspX1WOC1Jb9PSsdS5LuAXjeG2I82nYDyg9wZox9tw8E5QfMelpgvaRE3qrJpWO+rkPIYBLkEasteVW/h921CfwUFholb4Pu9cPZoM+sqbciiIa2NvJYy2Xb/CpTxkaVupmgCpWQ1P/HgBmg5DlDoJrk/1riAjI9gO6ihz8uW8JhaTeaHadNOLVueEnzExcpT1KDtP/4gIBmnHTEw7ihI3oHDxwVxJd8mNm7l81ZObBG5zcfZiBl1DrPPutMBCGle8fsP6yilKdCSvBzDDOxjjlTRcgeif8gY8AQ5sFeK1AusCgAG/vtDTOvUMRNTQNedw9CCkrbvaCR8oblvc6DkoIPJpZN0WKdeg4zG63sgXJn4iLrpr84XhAskxY+EZqQrueZ9tIqw98vbobV0gV849e+4azi/SDRPHs7bSuhFNsxhmz4pgNOmU0mL0hR6xOGsyszl/MkgPPzFCtUHOZCQzfwx7BFw/wy/yQnTuK+LjgIlZCr98LpAzDSjvQ5n56rCeVBHV1CnCbzAT/Ke6t/wDQJJJteA1pkxQkvpJOsx3dqMJgUZR3X8My+k8+aP8y93S5dGA1iEeA3IMVJmB0cpg76CkIezgMZkIkrpPMQO9YDeJwMkzcLAGSjWQcSF+hhyGAIHCpwaOLt3VQl2adPoPUj/M2nlPaQHuFrAoi5fc2C9CNx+/kX3xkxD4G0taHY8a6jp828M7ha8mQ1rkmfgTxXM4r8JDpgYS412pKomuPf20Lngoj9VZ106gH+13ut+217MCvLmZvieGKOvQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /DjYDHSlB+xT5Z5bwM0y0TnkWS14wTtQOyNPDz83LS/shc8gH6eZ2P1286GoTbMbA3fvOkx7Wn8IvegAkplk8mE31OLkhHgc9kwui2c2j4KvSE1sXfWPtDhs9g8TkCKREwEA3aiDe8QA8qAM2J5bK2FDhOhXHuzdGpWrRNeLF3PLCCL5sNkZ2Ghzyvi6WWNYinaU/eUX30hIG7vldHLdB5p0Bq7tlr7r/hOX2LNmi3wKn0PBVcf9eHgZB+tg8CwfvizcM3YXdGANgYpMS4XJ4fn3yk9jzI8JoUpwSVPMtRB7x87FkCd3+sXdAtLnpLfgohk6CLWzCRiGoPizQMxV8gGA+XeDlnQFW6zsG9szCGXc5tf7eE2rhTLm1FjIECZ5z3RO7RHvV/1JieC3LdSmcHc0X0bbtM4/plbA6mZtvlo5IECgqGnxdNJUYsYGZkTS X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2026 07:44:25.7184 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b1cf3cb-b23e-47be-ab45-08de858b581a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9678 Content-Type: text/plain; charset="utf-8" Move fields that are not read/written in fast path to a different struct / cacheline in the RQ structure. Signed-off-by: Tariq Toukan Reviewed-by: Dragos Tatulea Reviewed-by: Joe Damato Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 4 +++- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 12 +++++++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index c7ac6ebe8290..d90be82a9019 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -676,7 +676,6 @@ struct mlx5e_rq { struct mlx5e_umr_wqe_hdr umr_wqe; struct mlx5e_mpw_info *info; mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; - __be32 umr_mkey_be; u16 num_strides; u16 actual_wq_head; u8 log_stride_sz; @@ -745,6 +744,9 @@ struct mlx5e_rq { struct mlx5_core_dev *mdev; struct mlx5e_channel *channel; struct mlx5e_dma_info wqe_overflow; + struct { + __be32 umr_mkey_be; + } mpwqe_sp; =20 /* XDP read-mostly */ struct xdp_rxq_info xdp_rxq; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index f7009da94f0b..20c24d829ee2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -332,7 +332,7 @@ static inline void mlx5e_build_umr_wqe(struct mlx5e_rq = *rq, =20 cseg->qpn_ds =3D cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | ds_cnt); - cseg->umr_mkey =3D rq->mpwqe.umr_mkey_be; + cseg->umr_mkey =3D rq->mpwqe_sp.umr_mkey_be; =20 ucseg->flags =3D MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; octowords =3D mlx5e_mpwrq_umr_octowords(rq->mpwqe.pages_per_wqe, rq->mpwq= e.umr_mode); @@ -513,7 +513,7 @@ static int mlx5e_create_rq_umr_mkey(struct mlx5_core_de= v *mdev, struct mlx5e_rq err =3D mlx5e_create_umr_mkey(mdev, num_entries, rq->mpwqe.page_shift, &umr_mkey, rq->wqe_overflow.addr, rq->mpwqe.umr_mode, xsk_chunk_size); - rq->mpwqe.umr_mkey_be =3D cpu_to_be32(umr_mkey); + rq->mpwqe_sp.umr_mkey_be =3D cpu_to_be32(umr_mkey); return err; } =20 @@ -1024,7 +1024,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, =20 wqe->data[0].addr =3D cpu_to_be64(dma_offset + headroom); wqe->data[0].byte_count =3D cpu_to_be32(byte_count); - wqe->data[0].lkey =3D rq->mpwqe.umr_mkey_be; + wqe->data[0].lkey =3D rq->mpwqe_sp.umr_mkey_be; } else { struct mlx5e_rx_wqe_cyc *wqe =3D mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i); @@ -1057,7 +1057,8 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, err_free_mpwqe_info: kvfree(rq->mpwqe.info); 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Use it to pre-calculate the padding value and save it on the RQ struct. Signed-off-by: Tariq Toukan Reviewed-by: Dragos Tatulea Reviewed-by: Joe Damato Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 14 ++++++++++++++ drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 8 ++------ 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index d90be82a9019..6c773a75b514 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -685,6 +685,7 @@ struct mlx5e_rq { u8 min_wqe_bulk; u8 page_shift; u8 pages_per_wqe; + u8 entries_pad; u8 umr_wqebbs; u8 mtts_per_wqe; u8 umr_mode; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 20c24d829ee2..5a31c79cec06 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -307,6 +307,17 @@ static void mlx5e_disable_blocking_events(struct mlx5e= _priv *priv) mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb); } =20 +static u8 mlx5e_mpwrq_umr_entries_pad(u32 entries, + enum mlx5e_mpwrq_umr_mode umr_mode) +{ + u8 umr_entry_size =3D mlx5e_mpwrq_umr_entry_size(umr_mode); + u32 sz; + + sz =3D entries * umr_entry_size; + + return ALIGN(sz, MLX5_UMR_FLEX_ALIGNMENT) - sz; +} + static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mod= e umr_mode) { u8 umr_entry_size =3D mlx5e_mpwrq_umr_entry_size(umr_mode); @@ -904,6 +915,9 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, rq->mpwqe.pages_per_wqe =3D mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift, rq->mpwqe.umr_mode); + rq->mpwqe.entries_pad =3D + mlx5e_mpwrq_umr_entries_pad(rq->mpwqe.pages_per_wqe, + rq->mpwqe.umr_mode); rq->mpwqe.umr_wqebbs =3D mlx5e_mpwrq_umr_wqebbs(mdev, rq->mpwqe.page_shift, rq->mpwqe.umr_mode); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index f5c0e2a0ada9..580bb51ad7ef 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -645,13 +645,9 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u= 16 ix) /* Pad if needed, in case the value set to ucseg->xlt_octowords * in mlx5e_build_umr_wqe() needed alignment. */ - if (rq->mpwqe.pages_per_wqe & (MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT - 1)) { - int pad =3D ALIGN(rq->mpwqe.pages_per_wqe, MLX5_UMR_MTT_NUM_ENTRIES_ALIG= NMENT) - - rq->mpwqe.pages_per_wqe; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea Subject: [PATCH net-next 3/3] net/mlx5e: Speed up channel creation by initializing MKEY entries via UMR WQE Date: Thu, 19 Mar 2026 09:43:38 +0200 Message-ID: <20260319074338.24265-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260319074338.24265-1-tariqt@nvidia.com> References: <20260319074338.24265-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC2:EE_|PH8PR12MB6938:EE_ X-MS-Office365-Filtering-Correlation-Id: 54d6f343-7d07-4c04-1ee3-08de858b5dbc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: vYQgGIU56CxAba9eY52VQDiQejBOYm9WLQFy5eDzJyqgPpRA8G4yska85nfUkSPB7Js7g1l2vIqmxxmNRIsuQozZWHaAWOKL9xlAoLfxJ1Jn5fjiGAaItcWw0O8QYGHvXuxvIhO+UuLa3/W4KuQG3NZ1X79+uukMEEBQZ7tQKZZwaKlh4TQcyLY0+rRnYcpW4gvFTOM4IUsQYclzStp9AcfqIuurjDYaa/LgXwwMAGFHaLul/jyOBr4EXDuKfYTb+vtgp7G1+ihBYnNjTohokot0m+Ud/D9WgLpih4Ggd5UWIjOqlbpgPbk5huaHIcLHCGrD6wWUmkYU5SN4O/00dtkriC391UxZNDgLnpvyfFwU0wdwHHNmcutBifkvQ5e6mZe+elTF/QmEMBAnvtUJnRPzDLoOqjk3lhQKVJjT0nNjsKz7TCVAREskLsL8APq228Ba/wjwu/yhOazcoylYhhQ+0j9q3gNkZyQRrM/uUppqeb99BNJkQMjx7jvVjCr1v3TOjWVWd0TgcPBbKa1vBRrklvA/OtLfJi5jygxi3wjAoCS5j84wI8oGGvNUgkukyTyc5YSu8Lg2hX17AiHXE9wt9QsLlYiGLcZrNkET6XWchBvXPpNgCos+NyJzExB7asetKbeuAHr/vEjNAwV6YZnn10PtqSb/P0g7W/5qRdYCRYw/gcsFBtHHH2Xn2wPUg3nA859iCWSYZ9SFPHfAB4+5kBuXfP/CSYdvL7ORxA//9qzb2fbR0OrnONqU+ozRQ/DNeLtCnQH4+xyZcObFCQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700016)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: yVobRqYMJPdt6Q5L1D08UnNTIEuMLK7hprz9f28F4YEI6G8nbjEXqGMriejzX9oPF9ILqdWhTsJWsPY8aLnN1hCDBbyThnNPwtjjLi6M0XizSLpGWftW92VhZRjHSZDHG0AOA7LG+h2CTgg7SKJqKtxhZyARczmvXZPbF4YrucptNjNRPi/UG6HPs+Wn/zrBOOqN3tTBsImkDQ0lIgQBRFcopT6TBGNNATpU1l8mNe57178jv+gNehend62qwrqqGbthQY+E+nCV2wVFVC6JW3pXNwydpnaWlB/GSFmNbCDalJJOdqgVscDe+Vvp8ZQK0mOgKbpJBDe1sPriaGKLpJMZzzw6Vi+8ByLCo05Jgdk2OV8JNDPzJjAQ69L6i7AdI5hooQxqDyox+DYx4K0tfGddJJQBAkoxJ+dx41gAlArpHVec3bscVUnZKZCG7C2l X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2026 07:44:35.1641 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54d6f343-7d07-4c04-1ee3-08de858b5dbc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6938 Content-Type: text/plain; charset="utf-8" Initializing all UMR MKEY entries as part of the CREATE_MKEY firmware command is relatively slow. Since this operation is performed per RQ, the cumulative latency becomes significant with a large number of queues. Move the entries initialization out of the CREATE_MKEY command and perform it in the fast path by posting an appropriate UMR WQE on the ICOSQ. The UMR WQE is prepared and written to the ICOSQ before activation, making it safe without additional locking, as it does not race with NOP postings or early NAPI refills. Performance results: Setup: 248 channels, MTU 9000, RX/TX ring size 8K. Interface up: Before: 5.618 secs After: 3.537 secs (2.081 secs faster) Saves ~8.4 msec per channel. Signed-off-by: Tariq Toukan Reviewed-by: Dragos Tatulea Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 6 + .../net/ethernet/mellanox/mlx5/core/en/txrx.h | 1 + .../net/ethernet/mellanox/mlx5/core/en_main.c | 237 +++++++++++++----- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 1 + 4 files changed, 185 insertions(+), 60 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 6c773a75b514..1a6c86b5919a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -247,6 +247,7 @@ struct mlx5e_umr_wqe { DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms); + DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, dseg); }; }; static_assert(offsetof(struct mlx5e_umr_wqe, inline_mtts) =3D=3D sizeof(st= ruct mlx5e_umr_wqe_hdr), @@ -747,6 +748,11 @@ struct mlx5e_rq { struct mlx5e_dma_info wqe_overflow; struct { __be32 umr_mkey_be; + struct { + void *p_unaligned; + int sz; + dma_addr_t addr; + } init_data; } mpwqe_sp; =20 /* XDP read-mostly */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/en/txrx.h index f2a8453d8dce..948d22f508b0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h @@ -64,6 +64,7 @@ ktime_t mlx5e_cqe_ts_to_ns(cqe_ts_to_ns func, struct mlx5= _clock *clock, u64 cqe_ =20 enum mlx5e_icosq_wqe_type { MLX5E_ICOSQ_WQE_NOP, + MLX5E_ICOSQ_WQE_UMR_RX_INIT, MLX5E_ICOSQ_WQE_UMR_RX, #ifdef CONFIG_MLX5_EN_TLS MLX5E_ICOSQ_WQE_UMR_TLS, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 5a31c79cec06..eaed05865042 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -348,7 +348,6 @@ static inline void mlx5e_build_umr_wqe(struct mlx5e_rq = *rq, ucseg->flags =3D MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; octowords =3D mlx5e_mpwrq_umr_octowords(rq->mpwqe.pages_per_wqe, rq->mpwq= e.umr_mode); ucseg->xlt_octowords =3D cpu_to_be16(octowords); - ucseg->mkey_mask =3D cpu_to_be64(MLX5_MKEY_MASK_FREE); } =20 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node) @@ -397,57 +396,61 @@ static u8 mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_um= r_mode umr_mode) return 0; } =20 -static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, - u32 npages, u8 page_shift, u32 *umr_mkey, - dma_addr_t filler_addr, - enum mlx5e_mpwrq_umr_mode umr_mode, - u32 xsk_chunk_size) +static void mlx5e_rq_umr_mkey_data_free(struct mlx5e_rq *rq) { - struct mlx5_mtt *mtt; - struct mlx5_ksm *ksm; - struct mlx5_klm *klm; - u32 octwords; - int inlen; - void *mkc; - u32 *in; - int err; - int i; + if (!rq->mpwqe_sp.init_data.p_unaligned) + return; =20 - if ((umr_mode =3D=3D MLX5E_MPWRQ_UMR_MODE_UNALIGNED || - umr_mode =3D=3D MLX5E_MPWRQ_UMR_MODE_TRIPLE) && - !MLX5_CAP_GEN(mdev, fixed_buffer_size)) { - mlx5_core_warn(mdev, "Unaligned AF_XDP requires fixed_buffer_size capabi= lity\n"); - return -EINVAL; - } + dma_unmap_single(rq->pdev, rq->mpwqe_sp.init_data.addr, + rq->mpwqe_sp.init_data.sz, DMA_TO_DEVICE); + kfree(rq->mpwqe_sp.init_data.p_unaligned); + rq->mpwqe_sp.init_data.p_unaligned =3D NULL; +} =20 - octwords =3D mlx5e_mpwrq_umr_octowords(npages, umr_mode); +static int mlx5e_rq_umr_mkey_data_alloc(struct mlx5e_rq *rq, u32 npages, + struct mlx5_wqe_data_seg *dseg) +{ + dma_addr_t data_addr; + int data_sz; + void *data; =20 - inlen =3D MLX5_FLEXIBLE_INLEN(mdev, MLX5_ST_SZ_BYTES(create_mkey_in), - MLX5_OCTWORD, octwords); - if (inlen < 0) - return inlen; + data_sz =3D mlx5e_mpwrq_umr_octowords(npages, rq->mpwqe.umr_mode) * + MLX5_OCTWORD; + rq->mpwqe_sp.init_data.p_unaligned =3D + kzalloc(data_sz + MLX5_UMR_ALIGN - 1, GFP_KERNEL); + if (!rq->mpwqe_sp.init_data.p_unaligned) + return -ENOMEM; =20 - in =3D kvzalloc(inlen, GFP_KERNEL); - if (!in) + data =3D PTR_ALIGN(rq->mpwqe_sp.init_data.p_unaligned, MLX5_UMR_ALIGN); + data_addr =3D dma_map_single(rq->pdev, data, data_sz, DMA_TO_DEVICE); + if (dma_mapping_error(rq->pdev, data_addr)) { + kfree(rq->mpwqe_sp.init_data.p_unaligned); + rq->mpwqe_sp.init_data.p_unaligned =3D NULL; return -ENOMEM; + } =20 - mkc =3D MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); + rq->mpwqe_sp.init_data.sz =3D data_sz; + rq->mpwqe_sp.init_data.addr =3D data_addr; =20 - MLX5_SET(mkc, mkc, free, 1); - MLX5_SET(mkc, mkc, umr_en, 1); - MLX5_SET(mkc, mkc, lw, 1); - MLX5_SET(mkc, mkc, lr, 1); - MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode)); - mlx5e_mkey_set_relaxed_ordering(mdev, mkc); - MLX5_SET(mkc, mkc, qpn, 0xffffff); - MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn); - MLX5_SET64(mkc, mkc, len, npages << page_shift); - MLX5_SET(mkc, mkc, translations_octword_size, octwords); - if (umr_mode =3D=3D MLX5E_MPWRQ_UMR_MODE_TRIPLE) - MLX5_SET(mkc, mkc, log_page_size, page_shift - 2); - else if (umr_mode !=3D MLX5E_MPWRQ_UMR_MODE_OVERSIZED) - MLX5_SET(mkc, mkc, log_page_size, page_shift); - MLX5_SET(create_mkey_in, in, translations_octword_actual_size, octwords); + dseg->addr =3D cpu_to_be64(data_addr); + dseg->byte_count =3D cpu_to_be32(data_sz); + dseg->lkey =3D rq->mkey_be; + + return 0; +} + +static void mlx5e_rq_umr_mkey_data_fill(struct mlx5e_rq *rq, u32 npages) +{ + struct mlx5_core_dev *mdev =3D rq->mdev; + u32 xsk_chunk_size, xsk_rem; + dma_addr_t filler_addr; + struct mlx5_mtt *mtt; + struct mlx5_ksm *ksm; + struct mlx5_klm *klm; + __be32 mkey_be; + void *data; + u8 pad; + int i; =20 /* Initialize the mkey with all MTTs pointing to a default * page (filler_addr). When the channels are activated, UMR @@ -455,48 +458,152 @@ static int mlx5e_create_umr_mkey(struct mlx5_core_de= v *mdev, * the RQ's pool, while the gaps (wqe_overflow) remain mapped * to the default page. */ - switch (umr_mode) { + filler_addr =3D rq->wqe_overflow.addr; + + mkey_be =3D cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey); + data =3D PTR_ALIGN(rq->mpwqe_sp.init_data.p_unaligned, MLX5_UMR_ALIGN); + + switch (rq->mpwqe.umr_mode) { case MLX5E_MPWRQ_UMR_MODE_OVERSIZED: - klm =3D MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); + /* Must have xsk_pool !=3D NULL at this point */ + xsk_chunk_size =3D rq->xsk_pool->chunk_size; + xsk_rem =3D (1 << rq->mpwqe.page_shift) - xsk_chunk_size; + klm =3D data; for (i =3D 0; i < npages; i++) { klm[i << 1] =3D (struct mlx5_klm) { .va =3D cpu_to_be64(filler_addr), .bcount =3D cpu_to_be32(xsk_chunk_size), - .key =3D cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), + .key =3D mkey_be, }; klm[(i << 1) + 1] =3D (struct mlx5_klm) { .va =3D cpu_to_be64(filler_addr), - .bcount =3D cpu_to_be32((1 << page_shift) - xsk_chunk_size), - .key =3D cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), + .bcount =3D cpu_to_be32(xsk_rem), + .key =3D mkey_be, }; } break; case MLX5E_MPWRQ_UMR_MODE_UNALIGNED: - ksm =3D MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); + ksm =3D data; for (i =3D 0; i < npages; i++) ksm[i] =3D (struct mlx5_ksm) { - .key =3D cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), + .key =3D mkey_be, .va =3D cpu_to_be64(filler_addr), }; break; case MLX5E_MPWRQ_UMR_MODE_ALIGNED: - mtt =3D MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); + mtt =3D data; for (i =3D 0; i < npages; i++) mtt[i] =3D (struct mlx5_mtt) { .ptag =3D cpu_to_be64(filler_addr), }; break; case MLX5E_MPWRQ_UMR_MODE_TRIPLE: - ksm =3D MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); - for (i =3D 0; i < npages * 4; i++) { + ksm =3D data; + for (i =3D 0; i < npages * 4; i++) ksm[i] =3D (struct mlx5_ksm) { - .key =3D cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), + .key =3D mkey_be, .va =3D cpu_to_be64(filler_addr), }; - } break; } =20 + /* Pad is not expected, as we init the whole MKEY here */ + pad =3D mlx5e_mpwrq_umr_entries_pad(npages, rq->mpwqe.umr_mode); + WARN_ONCE(pad, "MPWRQ pad is not expected! UMR mode %u npages %d pad %u\n= ", + rq->mpwqe.umr_mode, npages, pad); +} + +static int mlx5e_rq_umr_mkey_data_init(struct mlx5e_rq *rq, u32 npages) + +{ + struct mlx5_wqe_ctrl_seg *cseg; + struct mlx5_wqe_umr_ctrl_seg *ucseg; + struct mlx5e_icosq *sq =3D rq->icosq; + struct mlx5e_umr_wqe *umr_wqe; + u16 pi, num_wqebbs, octowords; + u8 ds_cnt; + int err; + + /* + 1 for the data segment */ + ds_cnt =3D 1 + DIV_ROUND_UP(offsetof(struct mlx5e_umr_wqe, dseg), + MLX5_SEND_WQE_DS); + num_wqebbs =3D DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS); + pi =3D mlx5e_icosq_get_next_pi(sq, num_wqebbs); + umr_wqe =3D mlx5_wq_cyc_get_wqe(&sq->wq, pi); + memset(umr_wqe, 0, num_wqebbs * MLX5_SEND_WQE_BB); + + cseg =3D &umr_wqe->hdr.ctrl; + ucseg =3D &umr_wqe->hdr.uctrl; + + cseg->opmod_idx_opcode =3D + cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | + MLX5_OPCODE_UMR); + cseg->qpn_ds =3D cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | + ds_cnt); + cseg->umr_mkey =3D rq->mpwqe_sp.umr_mkey_be; + + octowords =3D mlx5e_mpwrq_umr_octowords(npages, rq->mpwqe.umr_mode); + ucseg->xlt_octowords =3D cpu_to_be16(octowords); + ucseg->mkey_mask =3D cpu_to_be64(MLX5_MKEY_MASK_FREE); + + err =3D mlx5e_rq_umr_mkey_data_alloc(rq, npages, umr_wqe->dseg); + if (err) + return err; + + mlx5e_rq_umr_mkey_data_fill(rq, npages); + + sq->db.wqe_info[pi] =3D (struct mlx5e_icosq_wqe_info) { + .wqe_type =3D MLX5E_ICOSQ_WQE_UMR_RX_INIT, + .num_wqebbs =3D num_wqebbs, + .umr.rq =3D rq, + }; + + sq->pc +=3D num_wqebbs; + + sq->doorbell_cseg =3D cseg; + + return 0; +} + +static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, + u32 npages, u8 page_shift, u32 *umr_mkey, + enum mlx5e_mpwrq_umr_mode umr_mode) +{ + int inlen; + void *mkc; + u32 *in; + int err; + + if ((umr_mode =3D=3D MLX5E_MPWRQ_UMR_MODE_UNALIGNED || + umr_mode =3D=3D MLX5E_MPWRQ_UMR_MODE_TRIPLE) && + !MLX5_CAP_GEN(mdev, fixed_buffer_size)) { + mlx5_core_warn(mdev, "Unaligned AF_XDP requires fixed_buffer_size capabi= lity\n"); + return -EINVAL; + } + + inlen =3D MLX5_ST_SZ_BYTES(create_mkey_in); + in =3D kvzalloc(inlen, GFP_KERNEL); + if (!in) + return -ENOMEM; + + mkc =3D MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); + + MLX5_SET(mkc, mkc, free, 1); + MLX5_SET(mkc, mkc, umr_en, 1); + MLX5_SET(mkc, mkc, lw, 1); + MLX5_SET(mkc, mkc, lr, 1); + MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode)); + mlx5e_mkey_set_relaxed_ordering(mdev, mkc); + MLX5_SET(mkc, mkc, qpn, 0xffffff); + MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn); + MLX5_SET64(mkc, mkc, len, npages << page_shift); + MLX5_SET(mkc, mkc, translations_octword_size, + mlx5e_mpwrq_umr_octowords(npages, umr_mode)); + if (umr_mode =3D=3D MLX5E_MPWRQ_UMR_MODE_TRIPLE) + MLX5_SET(mkc, mkc, log_page_size, page_shift - 2); + else if (umr_mode !=3D MLX5E_MPWRQ_UMR_MODE_OVERSIZED) + MLX5_SET(mkc, mkc, log_page_size, page_shift); + err =3D mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); =20 kvfree(in); @@ -505,7 +612,6 @@ static int mlx5e_create_umr_mkey(struct mlx5_core_dev *= mdev, =20 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx= 5e_rq *rq) { - u32 xsk_chunk_size =3D rq->xsk_pool ? rq->xsk_pool->chunk_size : 0; u32 wq_size =3D mlx5_wq_ll_get_size(&rq->mpwqe.wq); u32 num_entries, max_num_entries; u32 umr_mkey; @@ -522,9 +628,16 @@ static int mlx5e_create_rq_umr_mkey(struct mlx5_core_d= ev *mdev, struct mlx5e_rq max_num_entries); =20 err =3D mlx5e_create_umr_mkey(mdev, num_entries, rq->mpwqe.page_shift, - &umr_mkey, rq->wqe_overflow.addr, - rq->mpwqe.umr_mode, xsk_chunk_size); + &umr_mkey, rq->mpwqe.umr_mode); + if (err) + return err; + rq->mpwqe_sp.umr_mkey_be =3D cpu_to_be32(umr_mkey); + + err =3D mlx5e_rq_umr_mkey_data_init(rq, num_entries); + if (err) + mlx5_core_destroy_mkey(mdev, umr_mkey); + return err; } =20 @@ -1097,6 +1210,7 @@ static void mlx5e_free_rq(struct mlx5e_rq *rq) case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: mlx5e_rq_free_shampo(rq); kvfree(rq->mpwqe.info); + mlx5e_rq_umr_mkey_data_free(rq); mlx5_core_destroy_mkey(rq->mdev, be32_to_cpu(rq->mpwqe_sp.umr_mkey_be)); mlx5e_free_mpwqe_rq_drop_page(rq); @@ -1275,8 +1389,11 @@ int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, = int wait_time) u16 min_wqes =3D mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq)); =20 do { - if (mlx5e_rqwq_get_cur_sz(rq) >=3D min_wqes) + if (mlx5e_rqwq_get_cur_sz(rq) >=3D min_wqes) { + /* memory usage completed, can be freed already */ + mlx5e_rq_umr_mkey_data_free(rq); return 0; + } =20 msleep(20); } while (time_before(jiffies, exp_time)); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index 580bb51ad7ef..5edaa416cedd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -837,6 +837,7 @@ int mlx5e_poll_ico_cq(struct mlx5e_cq *cq) wi->umr.rq->mpwqe.umr_completed++; break; case MLX5E_ICOSQ_WQE_NOP: + case MLX5E_ICOSQ_WQE_UMR_RX_INIT: break; #ifdef CONFIG_MLX5_EN_TLS case MLX5E_ICOSQ_WQE_UMR_TLS: --=20 2.44.0