From nobody Thu Apr 2 02:40:46 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A55D387361; Thu, 19 Mar 2026 02:22:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773886930; cv=none; b=t/UPYGpiHuZ6XsThtDDU5quOIe4++yredK0CKNOYsBHHBs1Uyy5VxfJeXKT1o21wkxqIo1o2fohPy91CpUiBgwD4eFh/goUDmpDpIwC7V9A1fiYGqNXNCboSCin3BUq9oJtIGTnTCkElkgh/4lvyj9sgT6OnRLGF3pZcQcUtV3Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773886930; c=relaxed/simple; bh=exNYQWFEWehk8Oqva2MEHtCAhRbvXR6fpvsE0yu97go=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=noNSTQGIsFoYYisi63lBFgZlc2qFhXUtmowMvdXQrcOcBkrdKaXh2znfhbojESNBNCcaGdurpSLY8VEpQ5737/Rfy9uHHMjXgFe29EIfqrFe/d8dfX2/QNlFmSGeiOjdhzic1kYu6d/8LoC1fg4EjbuHe/vTF5h26gUDkKWHNlk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=ahyfUS6Y; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ahyfUS6Y" X-UUID: 685a9ade233a11f1a02d4725871ece0b-20260319 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To:From; bh=DZEXnAUOTgqSP/AYe8SzTtq6MPUe7lQFE+jJlLJzL0k=; b=ahyfUS6YtZC0Gk+nDdoBQ37p7AoLmODmIo6NTzOx4Yl+nESe+9ubRPgmX6LXSReZpwiGwa0JIoNuYaWujhpUw8SjWEADr5IXgx5BtlZoPggxiQh1HM+qXvhQJrUaK52N7Lbh6sRCB5Us7k4gXEJ9P6c7wrnZqaux/CPk9VSqVcg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:733d47dd-3616-4b47-80e2-6a631ab59860,IP:0,U RL:0,TC:0,Content:-5,EDM:-20,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-25 X-CID-META: VersionHash:e7bac3a,CLOUDID:7028de16-aa6b-4b2e-be76-373ef1a42b04,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:1,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI: 0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 685a9ade233a11f1a02d4725871ece0b-20260319 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2121683931; Thu, 19 Mar 2026 10:21:59 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 19 Mar 2026 10:21:58 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Thu, 19 Mar 2026 10:21:57 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Nicolas Dufresne , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , , , , , Subject: [PATCH v13 05/12] media: mediatek: jpeg: Fix multi-core clk suspend and resume setting Date: Thu, 19 Mar 2026 10:21:44 +0800 Message-ID: <20260319022152.31313-6-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260319022152.31313-1-kyrie.wu@mediatek.com> References: <20260319022152.31313-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" The suspend/resume callback function is defined in the dev_pm_ops structure, which is defined in platform_driver. For multiple-core architecture, each hardware driver will register a platform_driver structure, so it is necessary to add a suspend/resume callback function for each hardware to support this operation. Fixes: 934e8bccac95 ("mtk-jpegenc: support jpegenc multi-hardware") Fixes: 0fa49df4222f ("media: mtk-jpegdec: support jpegdec multi-hardware") Signed-off-by: Kyrie Wu --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 28 +++------ .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 62 +++++++++++++++++-- .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 60 ++++++++++++++++-- 3 files changed, 121 insertions(+), 29 deletions(-) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.c index 2e884aa31d1a..5c88f34634f9 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -1115,6 +1115,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg) { int ret; =20 + if (jpeg->variant->multi_core) + return; + ret =3D clk_bulk_prepare_enable(jpeg->variant->num_clks, jpeg->variant->clks); if (ret) @@ -1123,6 +1126,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg) =20 static void mtk_jpeg_clk_off(struct mtk_jpeg_dev *jpeg) { + if (jpeg->variant->multi_core) + return; + clk_bulk_disable_unprepare(jpeg->variant->num_clks, jpeg->variant->clks); } @@ -1645,13 +1651,6 @@ static void mtk_jpegenc_worker(struct work_struct *w= ork) goto enc_end; } =20 - ret =3D clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk); - if (ret) { - dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n", - __func__, __LINE__); - goto enc_end; - } - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); =20 @@ -1748,20 +1747,13 @@ static void mtk_jpegdec_worker(struct work_struct *= work) jpeg_dst_buf->frame_num =3D ctx->total_frame_num; =20 mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf); - ret =3D pm_runtime_get_sync(comp_jpeg[hw_id]->dev); + ret =3D pm_runtime_resume_and_get(comp_jpeg[hw_id]->dev); if (ret < 0) { dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n", __func__, __LINE__); goto dec_end; } =20 - ret =3D clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk); - if (ret) { - dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n", - __func__, __LINE__); - goto clk_end; - } - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); =20 @@ -1771,7 +1763,7 @@ static void mtk_jpegdec_worker(struct work_struct *wo= rk) &dst_buf->vb2_buf, &fb)) { dev_err(jpeg->dev, "%s : %d, mtk_jpeg_set_dec_dst fail\n", __func__, __LINE__); - goto setdst_end; + goto set_dst_fail; } =20 schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work, @@ -1792,9 +1784,7 @@ static void mtk_jpegdec_worker(struct work_struct *wo= rk) =20 return; =20 -setdst_end: - clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk); -clk_end: +set_dst_fail: pm_runtime_put(comp_jpeg[hw_id]->dev); dec_end: v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c index 4534caeb104f..9a8dbca6af00 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c @@ -533,13 +533,12 @@ static void mtk_jpegdec_timeout_work(struct work_stru= ct *work) v4l2_m2m_buf_copy_metadata(src_buf, dst_buf); =20 mtk_jpeg_dec_reset(cjpeg->reg_base); - clk_disable_unprepare(cjpeg->jdec_clk.clks->clk); - pm_runtime_put(cjpeg->dev); cjpeg->hw_state =3D MTK_JPEG_HW_IDLE; atomic_inc(&master_jpeg->hw_rdy); wake_up(&master_jpeg->hw_wq); v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegdec_put_buf(cjpeg); + pm_runtime_put(cjpeg->dev); } =20 static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv) @@ -547,7 +546,6 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, = void *priv) struct vb2_v4l2_buffer *src_buf, *dst_buf; struct mtk_jpeg_src_buf *jpeg_src_buf; enum vb2_buffer_state buf_state; - struct mtk_jpeg_ctx *ctx; u32 dec_irq_ret; u32 irq_status; int i; @@ -557,7 +555,6 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, = void *priv) =20 cancel_delayed_work(&jpeg->job_timeout_work); =20 - ctx =3D jpeg->hw_param.curr_ctx; src_buf =3D jpeg->hw_param.src_buffer; dst_buf =3D jpeg->hw_param.dst_buffer; v4l2_m2m_buf_copy_metadata(src_buf, dst_buf); @@ -580,12 +577,11 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq= , void *priv) buf_state =3D VB2_BUF_STATE_DONE; v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegdec_put_buf(jpeg); - pm_runtime_put(ctx->jpeg->dev); - clk_disable_unprepare(jpeg->jdec_clk.clks->clk); =20 jpeg->hw_state =3D MTK_JPEG_HW_IDLE; wake_up(&master_jpeg->hw_wq); atomic_inc(&master_jpeg->hw_rdy); + pm_runtime_put(jpeg->dev); =20 return IRQ_HANDLED; } @@ -668,15 +664,69 @@ static int mtk_jpegdec_hw_probe(struct platform_devic= e *pdev) =20 platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); + ret =3D devm_clk_bulk_get(dev->dev, + jpegdec_clk->clk_num, + jpegdec_clk->clks); + if (ret) { + dev_err(&pdev->dev, "Failed to init clk\n"); + return ret; + } =20 return 0; } =20 +static int mtk_jpegdec_pm_suspend(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg =3D dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(jpeg->jdec_clk.clk_num, + jpeg->jdec_clk.clks); + + return 0; +} + +static int mtk_jpegdec_pm_resume(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg =3D dev_get_drvdata(dev); + + return clk_bulk_prepare_enable(jpeg->jdec_clk.clk_num, + jpeg->jdec_clk.clks); +} + +static int mtk_jpegdec_suspend(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg =3D dev_get_drvdata(dev); + + v4l2_m2m_suspend(jpeg->master_dev->m2m_dev); + + return pm_runtime_force_suspend(dev); +} + +static int mtk_jpegdec_resume(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg =3D dev_get_drvdata(dev); + int ret; + + ret =3D pm_runtime_force_resume(dev); + if (ret < 0) + return ret; + + v4l2_m2m_resume(jpeg->master_dev->m2m_dev); + + return 0; +} + +static const struct dev_pm_ops mtk_jpegdec_pm_ops =3D { + SYSTEM_SLEEP_PM_OPS(mtk_jpegdec_suspend, mtk_jpegdec_resume) + RUNTIME_PM_OPS(mtk_jpegdec_pm_suspend, mtk_jpegdec_pm_resume, NULL) +}; + static struct platform_driver mtk_jpegdec_hw_driver =3D { .probe =3D mtk_jpegdec_hw_probe, .driver =3D { .name =3D "mtk-jpegdec-hw", .of_match_table =3D mtk_jpegdec_hw_ids, + .pm =3D &mtk_jpegdec_pm_ops, }, }; =20 diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index 2765dafab4ad..5d1c217fea0f 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -264,13 +264,12 @@ static void mtk_jpegenc_timeout_work(struct work_stru= ct *work) v4l2_m2m_buf_copy_metadata(src_buf, dst_buf); =20 mtk_jpeg_enc_reset(cjpeg->reg_base); - clk_disable_unprepare(cjpeg->venc_clk.clks->clk); - pm_runtime_put(cjpeg->dev); cjpeg->hw_state =3D MTK_JPEG_HW_IDLE; atomic_inc(&master_jpeg->hw_rdy); wake_up(&master_jpeg->hw_wq); v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegenc_put_buf(cjpeg); + pm_runtime_put(cjpeg->dev); } =20 static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv) @@ -304,12 +303,11 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq= , void *priv) buf_state =3D VB2_BUF_STATE_DONE; v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegenc_put_buf(jpeg); - pm_runtime_put(ctx->jpeg->dev); - clk_disable_unprepare(jpeg->venc_clk.clks->clk); =20 jpeg->hw_state =3D MTK_JPEG_HW_IDLE; wake_up(&master_jpeg->hw_wq); atomic_inc(&master_jpeg->hw_rdy); + pm_runtime_put(jpeg->dev); =20 return IRQ_HANDLED; } @@ -390,15 +388,69 @@ static int mtk_jpegenc_hw_probe(struct platform_devic= e *pdev) =20 platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); + ret =3D devm_clk_bulk_get(dev->dev, + jpegenc_clk->clk_num, + jpegenc_clk->clks); + if (ret) { + dev_err(&pdev->dev, "Failed to init clk\n"); + return ret; + } + + return 0; +} + +static int mtk_jpegenc_pm_suspend(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg =3D dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(jpeg->venc_clk.clk_num, + jpeg->venc_clk.clks); =20 return 0; } =20 +static int mtk_jpegenc_pm_resume(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg =3D dev_get_drvdata(dev); + + return clk_bulk_prepare_enable(jpeg->venc_clk.clk_num, + jpeg->venc_clk.clks); +} + +static int mtk_jpegenc_suspend(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg =3D dev_get_drvdata(dev); + + v4l2_m2m_suspend(jpeg->master_dev->m2m_dev); + + return pm_runtime_force_suspend(dev); +} + +static int mtk_jpegenc_resume(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg =3D dev_get_drvdata(dev); + int ret; + + ret =3D pm_runtime_force_resume(dev); + if (ret < 0) + return ret; + + v4l2_m2m_resume(jpeg->master_dev->m2m_dev); + + return 0; +} + +static const struct dev_pm_ops mtk_jpegenc_pm_ops =3D { + SYSTEM_SLEEP_PM_OPS(mtk_jpegenc_suspend, mtk_jpegenc_resume) + RUNTIME_PM_OPS(mtk_jpegenc_pm_suspend, mtk_jpegenc_pm_resume, NULL) +}; + static struct platform_driver mtk_jpegenc_hw_driver =3D { .probe =3D mtk_jpegenc_hw_probe, .driver =3D { .name =3D "mtk-jpegenc-hw", .of_match_table =3D mtk_jpegenc_drv_ids, + .pm =3D &mtk_jpegenc_pm_ops, }, }; =20 --=20 2.45.2