From nobody Mon Apr 6 15:00:14 2026 Received: from fr5000-r.dnsiaas.com (fr5000-r.dnsiaas.com [92.42.104.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D98F3A0E84; Thu, 19 Mar 2026 07:34:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.42.104.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773905655; cv=none; b=egRK/YcPrOqngcTqbBwLn/4OqYRQ5G0kvcgoGpZ/TQ2kkGDvkxVwtZyn01Wmt8nOMkLcjt7hEqlxkeEZKlaRrg5CeItzfDftKhgA5TdV+ICPQ7S0l/Ys3h4jJ6wqIqsvGPYg/U/he/sirH/t37YARi6/AjFOby5LaQlpR5p2Fp0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773905655; c=relaxed/simple; bh=s/jc/s6Rzr1Mg/JbVnbKEPF1NVKRtlMfsACn6kbFdKc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o6lb6MSscMM9FuER6azF6I5zcLZ0cxAwXeajrwvrqqevAzelZ6tz/Rv97R0r5VBQ2MHOn4vfT7XUzcJE8qw3Q8JC0pI2lLKokxZPqw4ovOEwOJF8Kz90IyZV+PTXDc/yxRLyRyrogjakHjwBngGPu4YTD0LNdcC+d0aPBSryeis= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=superkali.me; spf=fail smtp.mailfrom=superkali.me; dkim=pass (2048-bit key) header.d=superkali.me header.i=@superkali.me header.b=NYiXBJIE; arc=none smtp.client-ip=92.42.104.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=superkali.me Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=superkali.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=superkali.me header.i=@superkali.me header.b="NYiXBJIE" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=superkali.me; s=default; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=4r6wkkKWx0HfcJZH7gXeKF9oJ6zCw/C5ilURSEcdU7I=; b=NYiXBJIEH+T+2g8hYewFkM9BDA O8NdlkcreHW0y3YCQ5IrlXicy9+WNEMURIjspR8BhZUYHhPnUMFkvPhA0XMbsF12IR0cjQFaVt72/ rGq3KvUGxISB+2xilHnmNrM89c8oLGzxYgEkvoEzBqNTFng81gEYfr1G6YMbG5+y92Vf7M1Hm7eOh VR/eMOTs6PN/rAbImC1MAnRHP4KHUPFV6XBrfTCoJ9vKkomrMAcTNAncyIjtFzYzqFIgmWx/vbu5v jr5zq6nXHlj1riLO6TnNdyd6nWKkQ6LSF3KIu7+Pf79HslyyNbuCnbTihjY8Fy5KlviERPcJJKFxa 6o26tT5Q==; Received: from [109.52.2.233] (port=10095 helo=mac.lan) by fr5000-r.dnsiaas.com with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.99.1) (envelope-from ) id 1w37tP-0000000DgEs-2phc; Thu, 19 Mar 2026 08:34:05 +0100 From: Daniele Briguglio Date: Thu, 19 Mar 2026 08:33:59 +0100 Subject: [PATCH v2 1/3] dt-bindings: clock: rockchip,rk3588-cru: add I2S MCLK output to IO clock IDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260319-rk3588-mclk-gate-grf-v2-1-c4c8daab0762@superkali.me> References: <20260319-rk3588-mclk-gate-grf-v2-0-c4c8daab0762@superkali.me> In-Reply-To: <20260319-rk3588-mclk-gate-grf-v2-0-c4c8daab0762@superkali.me> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli , Daniele Briguglio , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773905640; l=975; i=hello@superkali.me; s=20260316; h=from:subject:message-id; bh=s/jc/s6Rzr1Mg/JbVnbKEPF1NVKRtlMfsACn6kbFdKc=; b=1jo5TKoywLPX8VEd6ybg8rA7NdSpML9127iS51mq8dWB4mhGkrFI8KjxZTGl32BmLMwh//X8y +XL5WnEh++1DPdxfHGQ0DeMYWHqoEMOAKPrOu72abkvOuEQ2Vijmsev X-Developer-Key: i=hello@superkali.me; a=ed25519; pk=5tynRWQdL93CDcapJ73FkcCRY2PeBOJOIAoIhRig53U= X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - fr5000-r.dnsiaas.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - superkali.me X-Get-Message-Sender-Via: fr5000-r.dnsiaas.com: authenticated_id: hello@superkali.me X-Authenticated-Sender: fr5000-r.dnsiaas.com: hello@superkali.me X-Source: X-Source-Args: X-Source-Dir: Add clock identifiers for the four I2S MCLK output to IO gate clocks on RK3588, needed by board DTS files where the codec requires MCLK from the SoC on an external IO pin. Acked-by: Krzysztof Kozlowski Signed-off-by: Daniele Briguglio --- include/dt-bindings/clock/rockchip,rk3588-cru.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-b= indings/clock/rockchip,rk3588-cru.h index 0c7d3ca2d5bc..7528034cff56 100644 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -734,6 +734,10 @@ #define PCLK_AV1_PRE 719 #define HCLK_SDIO_PRE 720 #define PCLK_VO1GRF 721 +#define I2S0_8CH_MCLKOUT_TO_IO 722 +#define I2S1_8CH_MCLKOUT_TO_IO 723 +#define I2S2_2CH_MCLKOUT_TO_IO 724 +#define I2S3_2CH_MCLKOUT_TO_IO 725 =20 /* scmi-clocks indices */ =20 --=20 2.53.0 From nobody Mon Apr 6 15:00:14 2026 Received: from fr5000-r.dnsiaas.com (fr5000-r.dnsiaas.com [92.42.104.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9738E3A1694; Thu, 19 Mar 2026 07:34:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Received: from [109.52.2.233] (port=10095 helo=mac.lan) by fr5000-r.dnsiaas.com with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.99.1) (envelope-from ) id 1w37tR-0000000DgEs-1Eqr; Thu, 19 Mar 2026 08:34:06 +0100 From: Daniele Briguglio Date: Thu, 19 Mar 2026 08:34:00 +0100 Subject: [PATCH v2 2/3] clk: rockchip: allow grf_type_sys lookup in aux_grf_table Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260319-rk3588-mclk-gate-grf-v2-2-c4c8daab0762@superkali.me> References: <20260319-rk3588-mclk-gate-grf-v2-0-c4c8daab0762@superkali.me> In-Reply-To: <20260319-rk3588-mclk-gate-grf-v2-0-c4c8daab0762@superkali.me> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli , Daniele Briguglio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773905640; l=1708; i=hello@superkali.me; s=20260316; h=from:subject:message-id; bh=WL4AZHxfBGBXO8GMVo8sFDi5dqnXuP+ssvyAyb87JKI=; b=CIBbXZiSnKKJf6/VCZVNzJ5/Lt9EuE5/PE8VkfNlNP486LQx0DFv1wQzMlAK+TMvYM17A3kOZ iPesQEuOR6EAbz3FxOiT0p4rKB9TickY9UT0KBVTzswjrW3QbrNIp6c X-Developer-Key: i=hello@superkali.me; a=ed25519; pk=5tynRWQdL93CDcapJ73FkcCRY2PeBOJOIAoIhRig53U= X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - fr5000-r.dnsiaas.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - superkali.me X-Get-Message-Sender-Via: fr5000-r.dnsiaas.com: authenticated_id: hello@superkali.me X-Authenticated-Sender: fr5000-r.dnsiaas.com: hello@superkali.me X-Source: X-Source-Args: X-Source-Dir: Remove the grf_type_sys exclusion from the auxiliary GRF table lookup in rockchip_clk_register_branches(). Previously, branches with grf_type_sys always used ctx->grf directly, bypassing the aux_grf_table. This is a problem on SoCs like RK3588 where ctx->grf points to the PHP_GRF (set via the CRU's rockchip,grf phandle), but GATE_GRF clock entries need to access the SYS_GRF instead. With this change, grf_type_sys branches first check the aux_grf_table, and fall back to ctx->grf if no entry is found. This is backwards compatible: on SoCs that do not register grf_type_sys in the aux_grf_table, the behavior is unchanged. Reviewed-by: Nicolas Frattaroli Signed-off-by: Daniele Briguglio --- drivers/clk/rockchip/clk.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index e8b3b0b9a4f8..911e6b610618 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -509,10 +509,9 @@ void rockchip_clk_register_branches(struct rockchip_cl= k_provider *ctx, clk =3D NULL; =20 /* for GRF-dependent branches, choose the right grf first */ - if ((list->branch_type =3D=3D branch_grf_mux || - list->branch_type =3D=3D branch_grf_gate || - list->branch_type =3D=3D branch_grf_mmc) && - list->grf_type !=3D grf_type_sys) { + if (list->branch_type =3D=3D branch_grf_mux || + list->branch_type =3D=3D branch_grf_gate || + list->branch_type =3D=3D branch_grf_mmc) { hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) { if (agrf->type =3D=3D list->grf_type) { grf =3D agrf->grf; --=20 2.53.0 From nobody Mon Apr 6 15:00:14 2026 Received: from fr5000-r.dnsiaas.com (fr5000-r.dnsiaas.com [92.42.104.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37D5A3A0B11; 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Received: from [109.52.2.233] (port=10095 helo=mac.lan) by fr5000-r.dnsiaas.com with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.99.1) (envelope-from ) id 1w37tS-0000000DgEs-3VvV; Thu, 19 Mar 2026 08:34:08 +0100 From: Daniele Briguglio Date: Thu, 19 Mar 2026 08:34:01 +0100 Subject: [PATCH v2 3/3] clk: rockchip: rk3588: add GATE_GRF clocks for I2S MCLK output to IO Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260319-rk3588-mclk-gate-grf-v2-3-c4c8daab0762@superkali.me> References: <20260319-rk3588-mclk-gate-grf-v2-0-c4c8daab0762@superkali.me> In-Reply-To: <20260319-rk3588-mclk-gate-grf-v2-0-c4c8daab0762@superkali.me> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli , Daniele Briguglio , kernel test robot X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773905640; l=4935; i=hello@superkali.me; s=20260316; h=from:subject:message-id; bh=RRXcYO4mT56fSVQOstELDSYSDSMhqXysPx/fily7Lbg=; b=6wylI2my88AJ0f/POCTOB9wj2WP1YanNZ/nQ0a95gj2CwoHZOGAJbcGnCPhCpQ6XnX3tO2Vo5 2atK0jFaZWFAkT+GW+t3rnqct4SYcJ/DxsRRYAZdinNSnwSl9AYV8id X-Developer-Key: i=hello@superkali.me; a=ed25519; pk=5tynRWQdL93CDcapJ73FkcCRY2PeBOJOIAoIhRig53U= X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - fr5000-r.dnsiaas.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - superkali.me X-Get-Message-Sender-Via: fr5000-r.dnsiaas.com: authenticated_id: hello@superkali.me X-Authenticated-Sender: fr5000-r.dnsiaas.com: hello@superkali.me X-Source: X-Source-Args: X-Source-Dir: The I2S MCLK outputs on RK3588 are gated by bits in the SYS_GRF register SOC_CON6 (offset 0x318). These gates control whether the internal CRU MCLK signals reach the external IO pins connected to audio codecs. The kernel should explicitly manage these gates so that audio functionality does not depend on bootloader register state. This is analogous to what was done for RK3576 SAI MCLK outputs [1]. Register the SYS_GRF as an auxiliary GRF with grf_type_sys in the early clock init, and add GATE_GRF entries for all four I2S MCLK output gates: - I2S0_8CH_MCLKOUT_TO_IO (bit 0) - I2S1_8CH_MCLKOUT_TO_IO (bit 1) - I2S2_2CH_MCLKOUT_TO_IO (bit 2) - I2S3_2CH_MCLKOUT_TO_IO (bit 7) Board DTS files that need MCLK on an IO pin can reference these clocks, e.g.: clocks =3D <&cru I2S0_8CH_MCLKOUT_TO_IO>; Tested on the Youyeetoo YY3588 (RK3588) with an ES8388 codec on I2S0. [1] https://lore.kernel.org/r/20250305-rk3576-sai-v1-2-64e6cf863e9a@collabo= ra.com/ Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202603191419.MH6EuPga-lkp@int= el.com/ Signed-off-by: Daniele Briguglio --- drivers/clk/rockchip/clk-rk3588.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-r= k3588.c index 1694223f4f84..4611b6ce8217 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -5,7 +5,9 @@ */ =20 #include +#include #include +#include #include #include #include @@ -892,6 +894,8 @@ static struct rockchip_clk_branch rk3588_early_clk_bran= ches[] __initdata =3D { RK3588_CLKGATE_CON(8), 0, GFLAGS), MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RAT= E_PARENT, RK3588_CLKSEL_CON(30), 2, 1, MFLAGS), + GATE_GRF(I2S2_2CH_MCLKOUT_TO_IO, "i2s2_2ch_mclkout_to_io", "i2s2_2ch_mclk= out", + 0, 0x0318, 2, GFLAGS, grf_type_sys), =20 COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS, @@ -907,6 +911,8 @@ static struct rockchip_clk_branch rk3588_early_clk_bran= ches[] __initdata =3D { RK3588_CLKGATE_CON(8), 4, GFLAGS), MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RAT= E_PARENT, RK3588_CLKSEL_CON(32), 2, 1, MFLAGS), + GATE_GRF(I2S3_2CH_MCLKOUT_TO_IO, "i2s3_2ch_mclkout_to_io", "i2s3_2ch_mclk= out", + 0, 0x0318, 7, GFLAGS, grf_type_sys), GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0, RK3588_CLKGATE_CON(7), 11, GFLAGS), GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0, @@ -935,6 +941,8 @@ static struct rockchip_clk_branch rk3588_early_clk_bran= ches[] __initdata =3D { RK3588_CLKGATE_CON(7), 10, GFLAGS), MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RAT= E_PARENT, RK3588_CLKSEL_CON(28), 2, 2, MFLAGS), + GATE_GRF(I2S0_8CH_MCLKOUT_TO_IO, "i2s0_8ch_mclkout_to_io", "i2s0_8ch_mclk= out", + 0, 0x0318, 0, GFLAGS, grf_type_sys), =20 GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, RK3588_CLKGATE_CON(9), 6, GFLAGS), @@ -2220,6 +2228,8 @@ static struct rockchip_clk_branch rk3588_early_clk_br= anches[] __initdata =3D { RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS), MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RAT= E_PARENT, RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS), + GATE_GRF(I2S1_8CH_MCLKOUT_TO_IO, "i2s1_8ch_mclkout_to_io", "i2s1_8ch_mclk= out", + 0, 0x0318, 1, GFLAGS, grf_type_sys), GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL, RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS), GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSE= D, @@ -2439,6 +2449,8 @@ static struct rockchip_clk_branch rk3588_clk_branches= [] =3D { static void __init rk3588_clk_early_init(struct device_node *np) { struct rockchip_clk_provider *ctx; + struct rockchip_aux_grf *sys_grf_e; + struct regmap *sys_grf; unsigned long clk_nr_clks, max_clk_id1, max_clk_id2; void __iomem *reg_base; =20 @@ -2479,6 +2491,17 @@ static void __init rk3588_clk_early_init(struct devi= ce_node *np) &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, ARRAY_SIZE(rk3588_cpub1clk_rates)); =20 + /* Register SYS_GRF for I2S MCLK output to IO gate clocks */ + sys_grf =3D syscon_regmap_lookup_by_compatible("rockchip,rk3588-sys-grf"); + if (!IS_ERR(sys_grf)) { + sys_grf_e =3D kzalloc_obj(*sys_grf_e); + if (sys_grf_e) { + sys_grf_e->grf =3D sys_grf; + sys_grf_e->type =3D grf_type_sys; + hash_add(ctx->aux_grf_table, &sys_grf_e->node, grf_type_sys); + } + } + rockchip_clk_register_branches(ctx, rk3588_early_clk_branches, ARRAY_SIZE(rk3588_early_clk_branches)); =20 --=20 2.53.0