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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f142cf16sm419743066b.20.2026.03.19.01.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2026 01:23:30 -0700 (PDT) From: Luca Weiss Date: Thu, 19 Mar 2026 09:23:18 +0100 Subject: [PATCH v3 1/2] arm64: dts: qcom: milos: Add UFS nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260319-milos-ufs-v3-1-b7c60bdd0d48@fairphone.com> References: <20260319-milos-ufs-v3-0-b7c60bdd0d48@fairphone.com> In-Reply-To: <20260319-milos-ufs-v3-0-b7c60bdd0d48@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Konrad Dybcio , Dmitry Baryshkov , Abel Vesa X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773908609; l=4541; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=DztUC4lS/7DD4vVPL63G3J+vnYcM9o3DQ762mAq/SwY=; b=sm2YyMqQvUM21AQ7DTyDpnJanoqPxL2+GlgoyE5EnJD7GmpwOY4aVaIt7y1zWdIC7m/77H5z4 FdIRJahjwkqAN3vGul0NmjqdnVr8LcXexv/AlrrzGFK3BiHjzIZMAbO X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the nodes for the UFS PHY and UFS host controller, along with the ICE used for UFS. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/milos.dtsi | 129 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 126 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index ed814c45ca05..25c092fae262 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -798,9 +798,9 @@ gcc: clock-controller@100000 { <&sleep_clk>, <0>, /* pcie_0_pipe_clk */ <0>, /* pcie_1_pipe_clk */ - <0>, /* ufs_phy_rx_symbol_0_clk */ - <0>, /* ufs_phy_rx_symbol_1_clk */ - <0>, /* ufs_phy_tx_symbol_0_clk */ + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ =20 #clock-cells =3D <1>; @@ -1152,6 +1152,129 @@ aggre2_noc: interconnect@1700000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + ufs_mem_phy: phy@1d80000 { + compatible =3D "qcom,milos-qmp-ufs-phy"; + reg =3D <0x0 0x01d80000 0x0 0x2000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + clock-names =3D "ref", + "ref_aux", + "qref"; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + power-domains =3D <&gcc UFS_MEM_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible =3D "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&tcsr TCSR_UFS_PAD_CLKREF_EN>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + power-domains =3D <&gcc UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + operating-points-v2 =3D <&ufs_opp_table>; + + iommus =3D <&apps_smmu 0x60 0>; + + dma-coherent; + + lanes-per-direction =3D <2>; + qcom,ice =3D <&ice>; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + #reset-cells =3D <1>; + + status =3D "disabled"; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz =3D /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + ice: crypto@1d88000 { + compatible =3D "qcom,milos-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x01d88000 0x0 0x18000>; + + clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x0 0x01f40000 0x0 0x20000>; --=20 2.53.0