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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b0704ccc67sm48391035ad.15.2026.03.19.02.24.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2026 02:24:10 -0700 (PDT) From: Wangao Wang Date: Thu, 19 Mar 2026 17:23:54 +0800 Subject: [PATCH v3 2/5] media: iris: Add hardware power on/off ops for X1P42100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260319-enable_iris_on_purwa-v3-2-bf8f3e9a8c9c@oss.qualcomm.com> References: <20260319-enable_iris_on_purwa-v3-0-bf8f3e9a8c9c@oss.qualcomm.com> In-Reply-To: <20260319-enable_iris_on_purwa-v3-0-bf8f3e9a8c9c@oss.qualcomm.com> To: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wangao Wang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773912238; l=4948; i=wangao.wang@oss.qualcomm.com; s=20251021; h=from:subject:message-id; bh=KRymRX1QuZjNQ6hpNIelP6wQnSQcuOm5wBCio6j+878=; b=D5oiUNg5947RsAJYUsAgCr/T9agudeKxNvbVP/TP6S86W+GqkRmIiuvx+aTImorZ5CGQsSg72 eJPxbl9Gq0wBcts5uJo5DCb67c4r23pwDNIhWKi+oFeUthMRn4fr14r X-Developer-Key: i=wangao.wang@oss.qualcomm.com; a=ed25519; pk=bUPgYblBUAsoPyGfssbNR7ZXUSGF8v1VF4FJzSO6/aA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE5MDA3NCBTYWx0ZWRfX5oqpCYOwqaMj Lz71HN3/LBusCTTQA7cM6pR4JZVlap8OyogVDcqg2oyZbljwJ3lOcr7itYvTjz4PdT6mp6/KmHy Go94JoeOVlPCIV86h1KZbIS/SPR0Yw44DXnQBu8aCwmKLL/AQcIAjZrUvg/QtrLYJlXRwkTnkF7 rr3j61FLmiOZQs+TzQMNU9+oKOIzmuAyOQNpgKI2xH17geq8QQhJ4Y/b5FSVCsyfwvVJWXzgAaa 8yUllgN5mxUaZNY1IlP/wemHedkB41m9MQiTkl2+k/c3JiH2KRQTxSznbZwq2fntboyz35lu2n5 hIr+EUDOFIds/n9bw82O8Iljp9MrrKV/+nl5hwlGWZD2sOC2HYM5n6BV4x2QrkwGKFOHC2yhjfd bCG8mxv/djxh7JHpg3voRDQB0ouk0C7046lUWtTPkVjyiHfFCIk/a1g9zpEPHu3sEUQaAzgWmpb I9pEa9lWYBqE2KC+SJw== X-Proofpoint-GUID: 70WbrxUAfjF9qUEjyG6vdvh7qsFYHTHI X-Authority-Analysis: v=2.4 cv=ZeMQ98VA c=1 sm=1 tr=0 ts=69bbc0bc cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=aVJmGZMIucSeeH-qYSoA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: 70WbrxUAfjF9qUEjyG6vdvh7qsFYHTHI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-19_01,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 clxscore=1015 spamscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603190074 On X1P42100 the Iris block has an extra BSE clock. Wire this clock into the power on/off sequence. The BSE clock is used to drive the Bin Stream Engine, which is a sub-block of the video codec hardware responsible for bitstream-level processing. It is required to be enabled separately from the core clock to ensure proper codec operation. Signed-off-by: Wangao Wang --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 87 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 2 files changed, 88 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index fe4423b951b1e9e31d06dffc69d18071cc985731..b641a7ab1a5f9051573fe8900ba= 01aaf78603120 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -71,6 +71,85 @@ static void iris_vpu3_power_off_hardware(struct iris_cor= e *core) iris_vpu_power_off_hw(core); } =20 +static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + if (ret) + goto err_disable_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); + if (ret) + goto err_disable_hw_clock; + + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); + if (ret) + goto err_disable_bse_hw_clock; + + return 0; + +err_disable_bse_hw_clock: + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); +err_disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + + return ret; +} + +static void iris_vpu3_purwa_power_off_hardware(struct iris_core *core) +{ + u32 reg_val =3D 0, value, i; + int ret; + + if (iris_vpu3x_hw_power_collapsed(core)) + goto disable_power; + + dev_err(core->dev, "video hw is power on\n"); + + value =3D readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + if (value) + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + for (i =3D 0; i < core->iris_platform_data->num_vpp_pipe; i++) { + ret =3D readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 *= i, + reg_val, reg_val & 0x400000, 2000, 20000); + if (ret) + goto disable_power; + } + + writel(VIDEO_NOC_RESET_REQ, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_RE= Q); + + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + reg_val, reg_val & 0x3, 200, 2000); + if (ret) + goto disable_power; + + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); + + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + reg_val, !(reg_val & 0x3), 200, 2000); + if (ret) + goto disable_power; + + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + +disable_power: + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , false); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +} + static void iris_vpu33_power_off_hardware(struct iris_core *core) { bool handshake_done =3D false, handshake_busy =3D false; @@ -268,6 +347,14 @@ const struct vpu_ops iris_vpu3_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, }; =20 +const struct vpu_ops iris_vpu3_purwa_ops =3D { + .power_off_hw =3D iris_vpu3_purwa_power_off_hardware, + .power_on_hw =3D iris_vpu3_purwa_power_on_hw, + .power_off_controller =3D iris_vpu_power_off_controller, + .power_on_controller =3D iris_vpu_power_on_controller, + .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, +}; + const struct vpu_ops iris_vpu33_ops =3D { .power_off_hw =3D iris_vpu33_power_off_hardware, .power_on_hw =3D iris_vpu_power_on_hw, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index f6dffc613b822341fb21e12de6b1395202f62cde..88a23cbdc06c5b38b4c8db67718= cbd538f0e0721 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -10,6 +10,7 @@ struct iris_core; =20 extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; +extern const struct vpu_ops iris_vpu3_purwa_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; extern const struct vpu_ops iris_vpu4x_ops; --=20 2.43.0