From nobody Mon Apr 6 10:45:14 2026 Received: from mail-24416.protonmail.ch (mail-24416.protonmail.ch [109.224.244.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BD7338F23C for ; Thu, 19 Mar 2026 11:58:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773921484; cv=none; b=aIhnCZa8P8jWbBvbbeDWmMSV0/DssgEkCoZXFGvUf1r1a3dx7ducQ6DYsiovaXYR8Ck1mra6VvpK7WhBMLq0zDDEsFQywxltrrR49xOQJw0bLHCHjgg+njgRAGPzLo2GPxN2fhQlHRU8dWULx37FZ4IatkSBMZzjt4j5Z33K1e8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773921484; c=relaxed/simple; bh=mEBBmmKkewV68WUhcRxlXKoX+eqcn8AWTduVHXPX4BA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=R5yZoafoWjnu7+uJvi69pTUHYDzuYgmsgVOIQSh+a9HEiHkpsJemOUtG2woVcoxf/9+Rb5W0VaM67cv8dLmMkf5nWOxe62oTO94pJE/j9rczSfgZebcX61DED5OSHUms7n8YZTrkNVXnqGJK4tx2Y7DtdclyDv9ALzQhYmDjmhA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=IKIt3sAG; arc=none smtp.client-ip=109.224.244.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="IKIt3sAG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773921473; x=1774180673; bh=mEBBmmKkewV68WUhcRxlXKoX+eqcn8AWTduVHXPX4BA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=IKIt3sAGOeIxPaCMUocRU+SoP7Tx2/8Gy90HmLHwY77ezeexR36SxfYHixGsqX2tO NA6suNR3LDNdRVz7vXnaAS8rYKE0cj4P+a7FXE3M9sbc1K5hBNOxKRTf00u0kh9FtH VhBouK/lPLslmWCqS5c1ydNeMN9Pw28k9zmhBZ7IrJOr61yeHEQ6r8DFYArWu0GxTR hZri0iMjdqDL7x1i6ETzLTq8wAWYSgM4tULTbGiJf5htR3Xx8Z942dUoRvDCiL5EEP /vLGAilJhB6igsMqCuGvCWV1gGe7QfmhDBQNmygw46rcrmEJ12dBEdtEuKqyDKVMyS 1Vz13/mIRTArw== Date: Thu, 19 Mar 2026 11:57:47 +0000 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Jeffrey Hugo From: Alexander Koskovich Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich Subject: [PATCH v3 1/4] drm/msm/dsi: rename MSM8998 DSI version from V2_2_0 to V2_0_0 Message-ID: <20260319-dsi-rgb101010-support-v3-1-85b99df2d090@pm.me> In-Reply-To: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> References: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 2976adefa00dd9004104e9d67642b07ae93d6130 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MSM8998 DSI controller is v2.0.0 as stated in commit 7b8c9e203039 ("drm/msm/dsi: Add support for MSM8998 DSI controller"). The value was always correct just the name was wrong. Rename and reorder to maintain version sorting. Fixes: 7b8c9e203039 ("drm/msm/dsi: Add support for MSM8998 DSI controller") Signed-off-by: Alexander Koskovich Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 ++-- drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/ds= i_cfg.c index bd3c51c350e7..da3fe6824495 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -317,10 +317,10 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handl= ers[] =3D { &msm8996_dsi_cfg, &msm_dsi_6g_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_2, &msm8976_dsi_cfg, &msm_dsi_6g_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_0_0, + &msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_1_0, &sdm660_dsi_cfg, &msm_dsi_6g_v2_host_ops}, - {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_0, - &msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1, &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0, diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/ds= i_cfg.h index 5dc812028bd5..ccf06679608e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -19,8 +19,8 @@ #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001 #define MSM_DSI_6G_VER_MINOR_V1_4_2 0x10040002 +#define MSM_DSI_6G_VER_MINOR_V2_0_0 0x20000000 #define MSM_DSI_6G_VER_MINOR_V2_1_0 0x20010000 -#define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000 #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001 #define MSM_DSI_6G_VER_MINOR_V2_3_0 0x20030000 #define MSM_DSI_6G_VER_MINOR_V2_3_1 0x20030001 --=20 2.53.0 From nobody Mon Apr 6 10:45:14 2026 Received: from mail-10629.protonmail.ch (mail-10629.protonmail.ch [79.135.106.29]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91A483CE4AE; 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charset="utf-8" Add a helper for checking if the DSI hardware version is greater than or equal to a given version, for use in a future change. Signed-off-by: Alexander Koskovich Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/dsi/dsi_host.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index db6da99375a1..6fad9a612d4d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -782,13 +782,20 @@ static void dsi_ctrl_disable(struct msm_dsi_host *msm= _host) dsi_write(msm_host, REG_DSI_CTRL, 0); } =20 +static bool msm_dsi_host_version_ge(struct msm_dsi_host *msm_host, + u32 major, u32 minor) +{ + return msm_host->cfg_hnd->major =3D=3D major && + msm_host->cfg_hnd->minor >=3D minor; +} + bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host =3D to_msm_dsi_host(host); =20 return msm_host->dsc && - (msm_host->cfg_hnd->major =3D=3D MSM_DSI_VER_MAJOR_6G && - msm_host->cfg_hnd->minor >=3D MSM_DSI_6G_VER_MINOR_V2_5_0); + msm_dsi_host_version_ge(msm_host, MSM_DSI_VER_MAJOR_6G, + MSM_DSI_6G_VER_MINOR_V2_5_0); } =20 static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, --=20 2.53.0 From nobody Mon Apr 6 10:45:14 2026 Received: from mail-106120.protonmail.ch (mail-106120.protonmail.ch [79.135.106.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C26A93CD8BA; Thu, 19 Mar 2026 11:58:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.120 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773921487; cv=none; b=lVtIhz9lRIB8K4rJzLbQTZvTeIfU3vyBYVRJoVDe2H2UaRoHTBTXKWa6J53E+lbZl/q8Y6I7fZiJqrKEKoxCnidf0MZmiHcFzfTTX4Z5kT2znJ3nKKHRBg7tx9G70Z1bF6tp2m2sSHnTXtY284JIHszhcpCyxcR98/bRAUqYlAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773921487; c=relaxed/simple; bh=1PMJifDV00qUaDh5JEUI3gqWlrTQUg2gT/Vva3OFaGs=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L4tLxCwq4xgJ+WNzlbvW2OXHfGYMBXgykyhJ8xKzX8kcxLVAtJhyTBXOyfuz7eENM/4xrhwPlFiW28i8g2pifF8ijsBriV9Etnt5lLJQcEQaJYu1lvixm4jQhpQZpY+A83pGUWBCsoAOdkbmx07gWbtbUlzCzeJmxUAYeE9IvzQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=A3HOgA3N; arc=none smtp.client-ip=79.135.106.120 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="A3HOgA3N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773921481; x=1774180681; bh=GG34JKH3bqtgzcVrg1uStZ2u9nut8a8HcOX8Ff5W+W4=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=A3HOgA3NifEOlXSCCJpbU3gzq1d6TmKDl0ieT3LIZ5dagDmC4fCB2PVNXmVjzYfbe JXPGgk9PD12TT6mWuAo1YbyRCfTbaVJNFFWZvah6v1846Za0MTRF55tdnlEodlBzv8 Ib3DmZaNIk28tNBeQHE83Q+aukiSuMWY2DbT6dA3l1GVDBLGKTk7YfXbtzBrKbfY6M rC21ChKaWan0bg2hfFeYH9hY/rwfuCGTco7ZLbrEN65ZH9tMy06Z7v+87+2/9CZD5g w+YwdPIraaz2S8Wg/MCPisBYtorqeRJsXF0R0Rfx+7ZrELvnhDm9yCs9z3vjMqCQf2 qV5hb/CXJvw6g== Date: Thu, 19 Mar 2026 11:57:56 +0000 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Jeffrey Hugo From: Alexander Koskovich Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich Subject: [PATCH v3 3/4] drm/msm/dsi: Add support for RGB101010 pixel format Message-ID: <20260319-dsi-rgb101010-support-v3-3-85b99df2d090@pm.me> In-Reply-To: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> References: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 43f2fd514197e1fb7f5ee3e1d109c297a104a6ea Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add video and command mode destination format mappings for RGB101010, and extend the VID_CFG0 DST_FORMAT bitfield to 3 bits to accommodate the new format value. Make sure this is guarded behind MSM_DSI_6G_VER >=3D V2.1.0 as anything older does not support this. Required for 10 bit panels such as the BOE BF068MWM-TD0. Signed-off-by: Alexander Koskovich Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/dsi/dsi_host.c | 10 ++++++++++ drivers/gpu/drm/msm/registers/display/dsi.xml | 5 ++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index 6fad9a612d4d..65c5b0e904ee 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -757,6 +757,7 @@ static inline enum dsi_vid_dst_format dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt) { switch (mipi_fmt) { + case MIPI_DSI_FMT_RGB101010: return VID_DST_FORMAT_RGB101010; case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; @@ -769,6 +770,7 @@ static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt) { switch (mipi_fmt) { + case MIPI_DSI_FMT_RGB101010: return CMD_DST_FORMAT_RGB101010; case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; case MIPI_DSI_FMT_RGB666_PACKED: case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; @@ -1705,6 +1707,14 @@ static int dsi_host_attach(struct mipi_dsi_host *hos= t, if (dsi->lanes > msm_host->num_data_lanes) return -EINVAL; =20 + if (dsi->format =3D=3D MIPI_DSI_FMT_RGB101010 && + !msm_dsi_host_version_ge(msm_host, MSM_DSI_VER_MAJOR_6G, + MSM_DSI_6G_VER_MINOR_V2_1_0)) { + DRM_DEV_ERROR(&msm_host->pdev->dev, + "RGB101010 not supported on this DSI controller\n"); + return -EINVAL; + } + msm_host->channel =3D dsi->channel; msm_host->lanes =3D dsi->lanes; msm_host->format =3D dsi->format; diff --git a/drivers/gpu/drm/msm/registers/display/dsi.xml b/drivers/gpu/dr= m/msm/registers/display/dsi.xml index c7a7b633d747..e40125f75175 100644 --- a/drivers/gpu/drm/msm/registers/display/dsi.xml +++ b/drivers/gpu/drm/msm/registers/display/dsi.xml @@ -15,6 +15,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> + @@ -39,6 +40,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> + @@ -142,7 +144,8 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> - + + --=20 2.53.0 From nobody Mon Apr 6 10:45:14 2026 Received: from mail-08.mail-europe.com (mail-08.mail-europe.com [57.129.93.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECE9D3CD8D2; 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charset="utf-8" Using bits_per_component * 3 as the divisor for the compressed INTF timing width produces constant FIFO errors for the BOE BF068MWM-TD0 panel due to bits_per_component being 10 which results in a divisor of 30 instead of 24. Regardless of the compression ratio and pixel depth, 24 bits of compressed data are transferred per pclk, so the divisor should always be 24. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 0ba777bda253..5419ef0be137 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -122,19 +122,18 @@ static void drm_mode_to_intf_timing_params( } =20 /* - * for DSI, if compression is enabled, then divide the horizonal active - * timing parameters by compression ratio. bits of 3 components(R/G/B) - * is compressed into bits of 1 pixel. + * For DSI, if DSC is enabled, 24 bits of compressed data are + * transferred per pclk regardless of the source pixel depth. */ if (phys_enc->hw_intf->cap->type !=3D INTF_DP && timing->compression_en) { struct drm_dsc_config *dsc =3D dpu_encoder_get_dsc_config(phys_enc->parent); + /* * TODO: replace drm_dsc_get_bpp_int with logic to handle * fractional part if there is fraction */ - timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / - (dsc->bits_per_component * 3); + timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / 24; timing->xres =3D timing->width; } } --=20 2.53.0