From nobody Mon Apr 6 16:47:57 2026 Received: from va-2-113.ptr.blmpb.com (va-2-113.ptr.blmpb.com [209.127.231.113]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20E57277CB8 for ; Wed, 18 Mar 2026 17:52:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.127.231.113 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773856359; cv=none; b=AynS4sZv+utFyXAH1IXtLxxGN/KkAeqRfolAA8UE7PIRlXAfzGsdOdGS0JYVt9cql9TmTQe1yUAfQtgLAYQs/UgHOVAPKQ7LWMa44LSnCzAGm1xh2h+GO/n6Kg5T+Mu9hjtZpiYMqTeu5PSaT2PUJY0LHWAFJk0it8INSAlcIUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773856359; c=relaxed/simple; bh=Ah2/ILWly2eCI12KxAzEmpP+iirap6VHSi7VvNU4ANw=; h=Cc:Message-Id:Mime-Version:To:From:Subject:Date:Content-Type; b=K0ULnk6EOsSPwmS5htfbGNgYAy70WXKVi7opgPpPXKTdJMAOc9kqLv/MbhbTjqeQxbS1tkYv38xKUCc3iPg4ANasNB6BIwNyiSLKLhYK9y7wgEIXauLae861us8sCbOc6WPGhaesLRbV0TKyjUl86EiS0ER7+EKlK3kdlr2Otz8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=I1e8bjnF; arc=none smtp.client-ip=209.127.231.113 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="I1e8bjnF" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=2212171451; d=bytedance.com; t=1773856346; h=from:subject: mime-version:from:date:message-id:subject:to:cc:reply-to:content-type: mime-version:in-reply-to:message-id; bh=4yw0+cD6IGhDPNiQGNKog+UxSd0veHxGIkzDTiQIVA8=; b=I1e8bjnFzKJcxXQgaISby+Zj80hDnx2hy2NPhpSnyqL4OUai9kSnsgwj1Ae7J2u4cOEJTB +2+AwpEGD9Ehc+H0a5fzrsYNDQQzypNTvsmVMhLVka1jaZcmK//n9/fxixgTga9j2gUlaU jpv9M5GKW4zVzCJ3oW7yGpZbO2O2WegPkHCFDKfvJmpOSQmN4xqeCBeFNBfej+l/WXxeA9 +gE/fshTv9p4U31EB1LZmB1s26K+Zl/mvpkqwR8Dq6ewVD1KEJuCGgMVa/Ww39q2g6JzkL 0ZG8kUjLAtNdyM7rV1iZEgbox/gtF87hskXjsJYmKH0/QdJ+K4RfUuPIRLTcmQ== Cc: Message-Id: <20260318175204.21762-1-linyongting@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.50.1 Content-Transfer-Encoding: quoted-printable To: , , , , , , , , , , , From: "Yongting Lin" Subject: [PATCH] x86/cpu: Add INVLPGB CPU feature flag to /proc/cpuinfo X-Original-From: Yongting Lin X-Lms-Return-Path: Date: Wed, 18 Mar 2026 10:52:04 -0700 Content-Type: text/plain; charset="utf-8" commit 767ae437a32d ("x86/mm: Add INVLPGB feature and Kconfig entry") introduced support for the INVLPGB instruction as a fast TLB invalidation mechanism. However, no corresponding CPU feature flag is exposed via /proc/cpuinfo. Add the "invlpgb" feature flag in arch/x86/include/asm/cpufeatures.h. The flag is picked up by arch/x86/kernel/cpu/mkcapflags.sh and exported through the x86_cap_flags array, making it visible in /proc/cpuinfo. Signed-off-by: Yongting Lin --- arch/x86/include/asm/cpufeatures.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index dbe104df339b..12f0a6610c93 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -332,7 +332,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Co= unt */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/res= tore FP error pointers */ -#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC instruction= s supported */ +#define X86_FEATURE_INVLPGB (13*32+ 3) /* "invlpgb" INVLPGB and TLBSYNC i= nstructions supported */ #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register a= t user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instructio= n */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Bar= rier */ --=20 2.39.5