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Wed, 18 Mar 2026 10:30:18 -0700 From: Akhil R To: Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J . Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 09/12] i3c: dw-i3c-master: Add a quirk to skip clock and reset Date: Wed, 18 Mar 2026 22:57:22 +0530 Message-ID: <20260318172820.13771-10-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC9:EE_|BL1PR12MB5780:EE_ X-MS-Office365-Filtering-Correlation-Id: bfafbbe6-e565-47db-5f2d-08de851418c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|82310400026|36860700016|921020|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: b+GaeNpmgpYp1qF80LYMDsZXBHx38qxiGexE+h3CdxXBmevtzFnBX3xfA5YYqwpf0hbozuVuG/NlhKpBFnLchKEx9jz5X6fSzyu2ky1TvwRJificrkDO3MHmNlH7xu7ceZQ7Wy9H/jFMLT34B0jb+UCUw4yLxJD/S+ylQ9aGDDyMw6B7IY7B9Lg0eh7CbMT0LlHc0tjfRmPoSvoSUXBINOeLHKgRoHlRRHW+Qw6gIuKBHOoMFVxKyMAq7ZW5jOm3wFbpGF39HPmZsqV68QLZOP1j69SQMzXUSGo3RuJAF2ben5ePzwMb1b3ZcS8YbVkF/Dy5E5D91A6FEIcnOrY9dKJuGuaIKrDGUgt/gX7qWlM5LOJ52C2EVz4pneJWRTUAPGoHa8mSuMhCUPSI7fJxmQ34NIBylVXM7pn5m9O+pRpGj9SiUnbQpdUWnXUBpoVNGWsK8u93Pz+7GxigSLkP2S9k/RHaO1CVUq+rUnLyEavgt0+diEIT1g4QXlJllYKqT9LiipycIEUMfHFcdV2kKXkVRdVVBp623GYwIsAIYvfhZH2Kor4dAHDjzuboh8UIHnVnVOp5bIJGgg34fQjpspv5o1g5fac+ci9iS9f9pDPP4XfvON4wdoUvwxfuMBM3k8LDqddAgmmGkICM4BbC/VCj11789nRHp2JcDzeLcKNjGp6tWgnmDYvvKsRDbCgK9f/7Yp0hbxCXraTFL2C/ODh7tGIlalP6V0rnS4rKrL0wGwovmuGxU6g4y4/sWmet8IV4xfEk57XnFuVdNFRre/OzLEBbvhKDCDZNmoDLpBIvqQudAL+C5yrtCEwGIQEl X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(82310400026)(36860700016)(921020)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rZ6UIEnzdKdO2AOddqTqGeGw/dUWYkS+2kyMPnf4TTu5Lksky1BunkQ/wBFliENJcHsB1nDPPGMvUZe+rXzaKB/zN2l1oBdQ7qMh5Qw9x1kkKiyclQ/ikMgaH5Fqdso458wjT2EsN3qUsScdTyJd+wWDeBpaQlGf//w3djWFQ+WZIyJw5ebpQftKHUOx1vP5z2VtSwDTewnuxdJevTnjAet0Xl6oOnuPHSvmm3tszqn/esgJ/48F7xZgzhGFPXgPwPX8X/Z0HOB0I7qEBQthCiV0NlBzkGHhUcVeRzCJl6wKJ5fP2YwafB39/Bdo/XiHWfece/82GeAp7V1IP85piGYgWDuSAtadZjOvVF2ww3Xzhncj3Jg47gLsVojH+lkVqog6J9DzH5GP75zMHVgGiVnJJBzYSJh4bqe6eo4MRr9z15D8P8qXAPgs+EHyz3ZI X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:30:49.3335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bfafbbe6-e565-47db-5f2d-08de851418c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5780 Content-Type: text/plain; charset="utf-8" Some ACPI-enumerated devices like Tegra410 do not have clock and reset resources exposed via the clk/reset frameworks. Add a match data for such devices to skip acquiring clock and reset controls during probe. Move match data parsing before clock/reset acquisition so the quirk is available early enough. When the quirk is set, fall back to reading the clock rate from the "clock-frequency" device property instead. Signed-off-by: Akhil R --- drivers/i3c/master/dw-i3c-master.c | 57 +++++++++++++++++++----------- 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 05ccdf177b6d..2dae63983303 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -241,6 +241,7 @@ /* List of quirks */ #define AMD_I3C_OD_PP_TIMING BIT(1) #define DW_I3C_DISABLE_RUNTIME_PM_QUIRK BIT(2) +#define DW_I3C_ACPI_SKIP_CLK_RST BIT(3) =20 struct dw_i3c_cmd { u32 cmd_lo; @@ -560,13 +561,26 @@ static void dw_i3c_master_set_intr_regs(struct dw_i3c= _master *master) writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); } =20 +static unsigned long dw_i3c_master_get_core_rate(struct dw_i3c_master *mas= ter) +{ + unsigned int core_rate_prop; + + if (!(master->quirks & DW_I3C_ACPI_SKIP_CLK_RST)) + return clk_get_rate(master->core_clk); + + if (device_property_read_u32(master->dev, "clock-frequency", &core_rate_p= rop)) + return 0; + + return core_rate_prop; +} + static int dw_i3c_clk_cfg(struct dw_i3c_master *master) { unsigned long core_rate, core_period; u32 scl_timing; u8 hcnt, lcnt; =20 - core_rate =3D clk_get_rate(master->core_clk); + core_rate =3D dw_i3c_master_get_core_rate(master); if (!core_rate) return -EINVAL; =20 @@ -619,7 +633,7 @@ static int dw_i2c_clk_cfg(struct dw_i3c_master *master) u16 hcnt, lcnt; u32 scl_timing; =20 - core_rate =3D clk_get_rate(master->core_clk); + core_rate =3D dw_i3c_master_get_core_rate(master); if (!core_rate) return -EINVAL; =20 @@ -1600,21 +1614,31 @@ int dw_i3c_common_probe(struct dw_i3c_master *maste= r, if (IS_ERR(master->regs)) return PTR_ERR(master->regs); =20 - master->core_clk =3D devm_clk_get_enabled(&pdev->dev, NULL); - if (IS_ERR(master->core_clk)) - return PTR_ERR(master->core_clk); + if (has_acpi_companion(&pdev->dev)) { + quirks =3D (unsigned long)device_get_match_data(&pdev->dev); + } else if (pdev->dev.of_node) { + drvdata =3D device_get_match_data(&pdev->dev); + if (drvdata) + quirks =3D drvdata->flags; + } + master->quirks =3D quirks; + + if (!(master->quirks & DW_I3C_ACPI_SKIP_CLK_RST)) { + master->core_clk =3D devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(master->core_clk)) + return PTR_ERR(master->core_clk); + + master->core_rst =3D devm_reset_control_get_optional_exclusive(&pdev->de= v, + "core_rst"); + if (IS_ERR(master->core_rst)) + return PTR_ERR(master->core_rst); + reset_control_deassert(master->core_rst); + } =20 master->pclk =3D devm_clk_get_optional_enabled(&pdev->dev, "pclk"); if (IS_ERR(master->pclk)) return PTR_ERR(master->pclk); =20 - master->core_rst =3D devm_reset_control_get_optional_exclusive(&pdev->dev, - "core_rst"); - if (IS_ERR(master->core_rst)) - return PTR_ERR(master->core_rst); - - reset_control_deassert(master->core_rst); - spin_lock_init(&master->xferqueue.lock); INIT_LIST_HEAD(&master->xferqueue.list); =20 @@ -1647,15 +1671,6 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, master->maxdevs =3D ret >> 16; master->free_pos =3D GENMASK(master->maxdevs - 1, 0); =20 - if (has_acpi_companion(&pdev->dev)) { - quirks =3D (unsigned long)device_get_match_data(&pdev->dev); - } else if (pdev->dev.of_node) { - drvdata =3D device_get_match_data(&pdev->dev); - if (drvdata) - quirks =3D drvdata->flags; - } - master->quirks =3D quirks; - /* Keep controller enabled by preventing runtime suspend */ if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK) pm_runtime_get_noresume(&pdev->dev); --=20 2.50.1