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Wed, 18 Mar 2026 10:28:47 -0700 From: Akhil R To: Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J . Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 01/12] dt-bindings: i3c: Add mipi-i3c-static-method to support SETAASA Date: Wed, 18 Mar 2026 22:57:14 +0530 Message-ID: <20260318172820.13771-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E81:EE_|IA1PR12MB6481:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b492d84-282a-4464-f116-08de8513df9f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700016|921020|13003099007|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: oStjSGASoXxCvUdbpxobU3Zc4pKjmeJf/IYTNbHUoFlxhaTQ9R7Oye5Kuwje/Lpu0htaiFiPsi4QKcoIK6MXvw7Hw89yWdff9M1kaxVkk7J+NDRdPkLRUWZVQwkZFkcsJ9zizK+U/37wfMW23IkRMwjSOCNk9fLVfZBIteGvGktX9jqwYvmhEjOMfoDwnY+9rokKyCoLV4FRFYmP0iKv0O0zek+0eyTLpUyZEsL7XQBqiUy0hMvb2aNU6POrFXCuXY8OtOyDg6LHQgoZttQxyAJWNGxGlK2QtTr1mdNMfbBBMOpud90TWz4hR36CHlPtDZTNH5ttUUE068bmp+B2hkp+BEYOkyPeD2L7pT7fAtZSJnFx3i50plAmvZqggETdNx46LencvT0Sae8H+5OKp8h7434i9K0PtRQQfySnPc887O1o2zb9V3uhsPZm1WVAyz+LZUyE03wmKDvyh5j1UoMKN0nLJMX+nzCvV5xE62KZZMPuKYOGPTWi7AiJiNZOOMDxc4YJi6wLEvXO5PD9kFttzdGejcWZuE/wBZCWjQFnjsfZMXmCLC1kWgb37AsVgA21y9nHZ5XIhHrZTFf0OTOCe7IzUUBTlGWjcPG1wnntRu4Ku9sGainGy9cyg09+pnJmgPaakbraUtWb3wmvYWo7hn4/jC7BBRFPX7xk/qeZugMQNI0hBCaDBV4lO5tYqjap+UNKBR4KVdaVcLMBjlLNOo3ROlAvD4tZ8sXuTvm7wvgKh/+Vga2M91IBLKG+pVmyDLOkFLfHTiU0/OSgTBvwGX+umzAZ6EX/kGlCBUnBbyHYn0oeCh9u3phQ93us X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700016)(921020)(13003099007)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 37onCCe07+QTOEemp82bm4Ux1kYbyjU2RMf4fpIFs4I5Q0S0P7vW6m8CLO4T95eHJrYWsxU1N0A5mTwFAvVt+TDmlL8cESOyg4hDjJqPDspMnZPuC4hdJKPSuwj4JhYS1OZ7PzD1lm2tvKz2ADqJVETuwioiUQjTNE/Ci56RQz9Cd+he2aPLPfK8dZpdz0DlqUVhmMeRni83Yi+6kng7noDaT7jFpFeX8B/e6SSnhvG8AB3bR1kFE7PBgrAS/SuTl5J6HhzPMnmBHKom3wu3mX8LuQg1FKXKsLbqp13EdBKF3UmdDEHxAWVV8lYc1tkGIG746BnzbSB9RH6V1PKX5K+HQiFKAVn/+l8hOPEuBjF6zzsFlRB/CqhnODSCk6tIfnBFkDZHGKPUnjNkrbnWKoULVY6ItoZbNqxDZ51jSXcApJ3tJCyDMJuVGY9upeeB X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:29:13.4901 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b492d84-282a-4464-f116-08de8513df9f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E81.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6481 Content-Type: text/plain; charset="utf-8" Add the 'mipi-i3c-static-method' property mentioned in the MIPI I3C Discovery and Configuration Specification [1] to specify which discovery method an I3C device supports during bus initialization. The property is a bitmap, where a bit value of 1 indicates support for that method, and 0 indicates lack of support. Bit 0: SETDASA CCC (Direct) Bit 1: SETAASA CCC (Broadcast) Bit 2: Other CCC (vendor / standards extension) All other bits are reserved. It is specifically needed when an I3C device requires SETAASA for the address assignment. SETDASA will be supported by default if this property is absent - which means for now the property just serves as a flag to enable SETAASA, but keep the property as a bitmap to align with the specifications. [1] https://www.mipi.org/specifications/disco Signed-off-by: Akhil R --- .../devicetree/bindings/i3c/i3c.yaml | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/i3c/i3c.yaml b/Documentation= /devicetree/bindings/i3c/i3c.yaml index e25fa72fd785..1705d90d4d79 100644 --- a/Documentation/devicetree/bindings/i3c/i3c.yaml +++ b/Documentation/devicetree/bindings/i3c/i3c.yaml @@ -31,10 +31,12 @@ properties: described in the device tree, which in turn means we have to describe I3C devices. =20 - Another use case for describing an I3C device in the device tree is = when - this I3C device has a static I2C address and we want to assign it a - specific I3C dynamic address before the DAA takes place (so that oth= er - devices on the bus can't take this dynamic address). + Other use-cases for describing an I3C device in the device tree are: + - When the I3C device has a static I2C address and we want to assign + it a specific I3C dynamic address before the DAA takes place (so + that other devices on the bus can't take this dynamic address). + - When the I3C device requires SETAASA for its discovery and uses a + pre-defined static address. =20 "#size-cells": const: 0 @@ -147,6 +149,26 @@ patternProperties: through SETDASA. If static address is not present, this address = is assigned through SETNEWDA after assigning a temporary address via ENTDAA. =20 + mipi-i3c-static-method: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x1 + maximum: 0xff + default: 1 + description: | + Bitmap describing which methods of Dynamic Address Assignment fr= om a + static address are supported by this I3C Target. A bit value of 1 + indicates support for that method, and 0 indicates lack of suppo= rt. + Bit 0: SETDASA CCC (Direct) + Bit 1: SETAASA CCC (Broadcast) + Bit 2: Other CCC (vendor / standards extension) + All other bits are reserved. + + This property follows the MIPI I3C specification. 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Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 02/12] ACPICA: Read LVR from the I2C resource descriptor Date: Wed, 18 Mar 2026 22:57:15 +0530 Message-ID: <20260318172820.13771-3-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E83:EE_|CH2PR12MB4277:EE_ X-MS-Office365-Filtering-Correlation-Id: 615e374c-98a9-4c2d-47aa-08de8513e906 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|7416014|376014|921020|13003099007|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: gP4eTrkkLd07z06SEc5iGHO02xdM1zuwQKF+bqsm+SXpjgv8VKYb2XdHDdkRfZVUIk0v/TTtqiOcIp0aevL/jCneUaLIYUfPJrTeOBwk9eGkP+7YzTLaK3sa+rb0Q8fb7/ikIGXJguIausUl4nJGkVdpkOWunc94vtwaXO0IVBgUljHt683I5mc3GEDb8lxHYyoAcx1eyUIO/T7pIiK64lDtAt+UUHd/Jm5g11tGR+qfSuNliR6X2cjevaAma4RUI1lLuOl39g5Mi40fXAuwZvknMvXd5V4o1M63RVtwOx1qJf78sr5C3zBGqC/IQWBWn/x1cgdjL959u/2MrOCoX3QgntJpI3BN6L2WIlba8gcETF722PZYQDa02S2w8fpEuavXq7uany1pBMTZVF+9Oby25UKq9vRIVxVHUIAUHdCaKgKv7sBt7IgmFlLZkqYgwELcNESAj4+oF9crZUOjowqK9dceIMmyKdj0A90Z6iN+NZO99lawJ5M4NdHTX/hKIYSaKcaRaq1CGhOzHRY6nkJPjgt1AIl9NKAb1EA+buFEGXuOFJPMRpXcJCHbmhQFr3UvTu+uo60PLn8JOJ/9gpOo8WNgQXc2jZe8WnzF2MEVvLljA8rku4TQ9QG5lboAYEYsW+ehgWS2NUaISczEbMmOIKBLlp2HiUNyMwXfR98khn9Rdo9qjwFUaQmC8OY1q8Mlo05LrLPJibiQBCR1ThQMdUqpfx5bx+Ou5P3oE/jzsJDCN3qtbe6ngwu8cWMGZWbRgE8gh43QiIuTgqtiv23/NkiVqS5Z20/MIl1AnrxAe8/G1/gKER5R6sEfyYypmkW1iqEE6R20mq/crB+Swg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(7416014)(376014)(921020)(13003099007)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: g/NXMGUuFCSTyYWryMMZ21dSZz/b+WEZDapWZOni3QHIRESnEB6SpoO9fAxGYIktKRFwkEKY4580YSMjZdR07t8BG/dHqQm3GFiH3yxMtDh/NZWepDbJkR2RQphHXZA0QUzhk6DUYOGKvsXy5NLthHhn0xHm9QyMSY8oUPSYlWkDEqoV60dEtHKht03svbYR3dPNeQAtXz8mk2H+HbdAlkooK6m3VSEdIOKlEqn0n2b+Bybn4/S7D4LSEVeUV4CsfYL8Ddm7Vyk0tx5NTEBYjhsc4oWlo7u68ByvELfS71SgdRTjilx/KToS3UBGZddy2tJ0XYQjs9WvX/DGpeW6TmIuatvNLUcaIsoAGQPzHNqr2UBi76OQe5x/je2sF1ICPr+9HsdDTawMkM4+RNuaBv9W8t+w7SCwhHpmyQElBxSwmUoHDm0MGurQ5hQwx11B X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:29:29.2624 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 615e374c-98a9-4c2d-47aa-08de8513e906 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E83.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4277 Content-Type: text/plain; charset="utf-8" ACPI 6.3 specifies byte 8 of I2C Serial Bus Connection descriptor to be used for Legacy Virtual Register (LVR) data as specified in the MIPI I3C Specification for an I2C device connected to an I3C Host Controller. LVR will be read by I3C host controller drivers and it provides details about the specific speed and 50ns spike filter capabilities of I2C devices. Update the rsconvert_info to include this field. For I2C devices on an I2C bus, this field is Reserved and unused. This commit is the result of squashing the following: ACPICA commit 70082dc8fc847673ac7f4bbb1541776730f0b63e ACPICA commit e62e74baf7e08cf059ec82049aeccd565b24d661 ACPICA commit c404118235108012cad396c834b5aabe2dd1b51a ACPICA commit 7650d4a889ea7907060bfce89f4f780ce83e7b28 ACPICA commit 014fa9f2dbcc6b1bd42a4a4a6f6705d9cf7d460b Link: https://github.com/acpica/acpica/commit/70082dc8 Link: https://github.com/acpica/acpica/commit/b3c38dc9 Signed-off-by: Akhil R --- drivers/acpi/acpica/rsserial.c | 6 +++++- include/acpi/acrestyp.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/acpica/rsserial.c b/drivers/acpi/acpica/rsserial.c index 279bfa27da94..c06e918ab889 100644 --- a/drivers/acpi/acpica/rsserial.c +++ b/drivers/acpi/acpica/rsserial.c @@ -315,7 +315,7 @@ struct acpi_rsconvert_info acpi_rs_convert_csi2_serial_= bus[14] =3D { * *************************************************************************= *****/ =20 -struct acpi_rsconvert_info acpi_rs_convert_i2c_serial_bus[17] =3D { +struct acpi_rsconvert_info acpi_rs_convert_i2c_serial_bus[18] =3D { {ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_SERIAL_BUS, ACPI_RS_SIZE(struct acpi_resource_i2c_serialbus), ACPI_RSC_TABLE_SIZE(acpi_rs_convert_i2c_serial_bus)}, @@ -391,6 +391,10 @@ struct acpi_rsconvert_info acpi_rs_convert_i2c_serial_= bus[17] =3D { AML_OFFSET(i2c_serial_bus.type_specific_flags), 0}, =20 + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.i2c_serial_bus.lvr), + AML_OFFSET(i2c_serial_bus.type_specific_flags) + 1, + 1}, + {ACPI_RSC_MOVE32, ACPI_RS_OFFSET(data.i2c_serial_bus.connection_speed), AML_OFFSET(i2c_serial_bus.connection_speed), 1}, diff --git a/include/acpi/acrestyp.h b/include/acpi/acrestyp.h index 842f932e2c2b..38a19b1d19ac 100644 --- a/include/acpi/acrestyp.h +++ b/include/acpi/acrestyp.h @@ -423,6 +423,7 @@ struct acpi_resource_i2c_serialbus { ACPI_RESOURCE_SERIAL_COMMON u8 access_mode; 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Wed, 18 Mar 2026 10:29:10 -0700 From: Akhil R To: Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J . Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 03/12] i3c: master: Use unified device property interface Date: Wed, 18 Mar 2026 22:57:16 +0530 Message-ID: <20260318172820.13771-4-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC4:EE_|CH1PR12MB9622:EE_ X-MS-Office365-Filtering-Correlation-Id: 969a8c6e-bf0a-44bb-75b8-08de8513ecfa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|82310400026|1800799024|56012099003|18002099003|22082099003|921020; X-Microsoft-Antispam-Message-Info: ej+zICg4bNVepXK/1GH+c+3UEvJUU8bg/SW+dbJGtkzo9OjuNyxv2RGorwQn4xOUCb1w8awx7uigU9PFCq6AzDkyeIF8eAkrS+41B0sdcq2TSU03Ni9z2eCU7I+r+jvwYhhT/UfZlDfP0RgRlaZGMxSCG+EB/nZJtqjemkowH7SUKPDF+RYWagPmiZ0go8bRpyOiqjBf/odPMAzJll9yIcrx6kcqKXG0OYGOQB4AiwUrRjyfxJ1MExGmruv46Q29fFlbLtTfqHW7u5pIWxD9bDxE+JoLyXNmSTdfIY1fJ1jAjgnFkUraAgIACgJinBaBnO6XOX5K3R18GfF+YE1iVIstvWx03W32wiKUX71SHdLf8UrJZl7UjKn4nkjWRXvehoc+Wv+SeGS8BOcuwX6hLkSNPSljHGRfOkxvMK/JgXKQKag7A2m2fDH6/Mp2aVSq41A9QFHq5lmZIBux9m6r9gLEja6znEHGtjSNAM4cYf0zxjKNOkc71f0X9WBwzvBgFIUC0wcMkbblZbNWkGPidYWOcodpGjQbZ7m1qu5ofezZ/sAvoq0knZxO0BT2lqX7hZFxazi5AdaV9TiZNC0VyVUAjktOpDE10FaW/m7GvhGI91mYtMgL4BrQYvQ4Iri8C2OPRkByM9ar5t4ZBl1malnQ1d+J0VFEERaUZVPY72t8VV+q45wTHwKULMwAzMXnQkLbg86sCdXpijeT4lu3OGOSTdJXMH/5UhYUHcOXcIrDuhASS/S+tyBdfgtRv4zzhsiFoXnj2MIzzwFAd7iv+Av1/SDI88angiSdAtWu5iaTq7AFVhjmxustO1VmfXTd X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(7416014)(82310400026)(1800799024)(56012099003)(18002099003)(22082099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mmnaPrX0nvnKrPNcN9SM00bRPbEhmhedQyUeEHgwaDC2atyTgaO2RG+wY+sWEyiyekJ2H4PVjwqmvLsdiCmYpscCxJs+HW5oupWmI7glI1CfyCGv2dSZwUFfF6DGj/C0y8ktcBkh5M7df1E8/BaN4sEUSuqw86FJcQASW+RO+Opy1aTQ7lWhvyGZp7idRyELb22jE2BaLi+4QTaaWvD8drnjWoVe1Pbch2hHYEtBVtEW0pBR2aHbqzbn9Tc9KFiHZ6GLUeuilSjPRnR9T4QuGNhXHePO1Eop1vEFJHb4oR0Srv/ne0En+f3cNLMzIOxMtsXxuv3/Dk1/+WNnagIyKQ2+VZkhl/qhgnwH2nG1L6NLhQrS76sfHqe6Wq34/8mHpTGg2I1SVZbW1AQbxYtmDRKp82bLglKlBVTTKNVyor8ms49CrpjYu0wxfo8gDX8W X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:29:35.8384 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 969a8c6e-bf0a-44bb-75b8-08de8513ecfa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9622 Content-Type: text/plain; charset="utf-8" Replace all OF-specific functions with unified device property functions as a prerequisite to support both ACPI and device tree. Signed-off-by: Akhil R Reviewed-by: Frank Li --- drivers/i3c/master.c | 91 ++++++++++++++++++++++---------------- include/linux/i3c/master.h | 5 ++- 2 files changed, 55 insertions(+), 41 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index c32847bc4d0d..2c479fecbfdf 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -5,16 +5,19 @@ * Author: Boris Brezillon */ =20 +#include #include #include #include #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -497,7 +500,7 @@ static void i3c_bus_cleanup(struct i3c_bus *i3cbus) mutex_unlock(&i3c_core_lock); } =20 -static int i3c_bus_init(struct i3c_bus *i3cbus, struct device_node *np) +static int i3c_bus_init(struct i3c_bus *i3cbus, struct fwnode_handle *fwno= de) { int ret, start, end, id =3D -1; =20 @@ -507,8 +510,8 @@ static int i3c_bus_init(struct i3c_bus *i3cbus, struct = device_node *np) i3c_bus_init_addrslots(i3cbus); i3cbus->mode =3D I3C_BUS_MODE_PURE; =20 - if (np) - id =3D of_alias_get_id(np, "i3c"); + if (fwnode && is_of_node(fwnode)) + id =3D of_alias_get_id(to_of_node(fwnode), "i3c"); =20 mutex_lock(&i3c_core_lock); if (id >=3D 0) { @@ -811,7 +814,7 @@ static void i3c_masterdev_release(struct device *dev) WARN_ON(!list_empty(&bus->devs.i2c) || !list_empty(&bus->devs.i3c)); i3c_bus_cleanup(bus); =20 - of_node_put(dev->of_node); + fwnode_handle_put(dev->fwnode); } =20 static const struct device_type i3c_masterdev_type =3D { @@ -995,7 +998,7 @@ static void i3c_device_release(struct device *dev) =20 WARN_ON(i3cdev->desc); =20 - of_node_put(i3cdev->dev.of_node); + fwnode_handle_put(dev->fwnode); kfree(i3cdev); } =20 @@ -1783,7 +1786,7 @@ i3c_master_register_new_i3c_devs(struct i3c_master_co= ntroller *master) desc->info.pid); =20 if (desc->boardinfo) - desc->dev->dev.of_node =3D desc->boardinfo->of_node; + device_set_node(&desc->dev->dev, desc->boardinfo->fwnode); =20 ret =3D device_register(&desc->dev->dev); if (ret) { @@ -2402,8 +2405,8 @@ EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked); #define OF_I3C_REG1_IS_I2C_DEV BIT(31) =20 static int -of_i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master, - struct device_node *node, u32 *reg) +i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master, + struct fwnode_handle *fwnode, u32 *reg) { struct i2c_dev_boardinfo *boardinfo; struct device *dev =3D &master->dev; @@ -2413,9 +2416,13 @@ of_i3c_master_add_i2c_boardinfo(struct i3c_master_co= ntroller *master, if (!boardinfo) return -ENOMEM; =20 - ret =3D of_i2c_get_board_info(dev, node, &boardinfo->base); - if (ret) - return ret; + if (is_of_node(fwnode)) { + ret =3D of_i2c_get_board_info(dev, to_of_node(fwnode), &boardinfo->base); + if (ret) + return ret; + } else { + return -EINVAL; + } =20 /* * The I3C Specification does not clearly say I2C devices with 10-bit @@ -2431,14 +2438,14 @@ of_i3c_master_add_i2c_boardinfo(struct i3c_master_c= ontroller *master, boardinfo->lvr =3D reg[2]; =20 list_add_tail(&boardinfo->node, &master->boardinfo.i2c); - of_node_get(node); + fwnode_handle_get(fwnode); =20 return 0; } =20 static int -of_i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master, - struct device_node *node, u32 *reg) +i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master, + struct fwnode_handle *fwnode, u32 *reg) { struct i3c_dev_boardinfo *boardinfo; struct device *dev =3D &master->dev; @@ -2461,7 +2468,7 @@ of_i3c_master_add_i3c_boardinfo(struct i3c_master_con= troller *master, =20 boardinfo->static_addr =3D reg[0]; =20 - if (!of_property_read_u32(node, "assigned-address", &init_dyn_addr)) { + if (!fwnode_property_read_u32(fwnode, "assigned-address", &init_dyn_addr)= ) { if (init_dyn_addr > I3C_MAX_ADDR) return -EINVAL; =20 @@ -2478,14 +2485,14 @@ of_i3c_master_add_i3c_boardinfo(struct i3c_master_c= ontroller *master, return -EINVAL; =20 boardinfo->init_dyn_addr =3D init_dyn_addr; - boardinfo->of_node =3D of_node_get(node); + boardinfo->fwnode =3D fwnode_handle_get(fwnode); list_add_tail(&boardinfo->node, &master->boardinfo.i3c); =20 return 0; } =20 -static int of_i3c_master_add_dev(struct i3c_master_controller *master, - struct device_node *node) +static int i3c_master_add_dev(struct i3c_master_controller *master, + struct fwnode_handle *fwnode) { u32 reg[3]; int ret; @@ -2493,7 +2500,7 @@ static int of_i3c_master_add_dev(struct i3c_master_co= ntroller *master, if (!master) return -EINVAL; =20 - ret =3D of_property_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg)); + ret =3D fwnode_property_read_u32_array(fwnode, "reg", reg, ARRAY_SIZE(reg= )); if (ret) return ret; =20 @@ -2502,25 +2509,25 @@ static int of_i3c_master_add_dev(struct i3c_master_= controller *master, * dealing with an I2C device. */ if (!reg[1]) - ret =3D of_i3c_master_add_i2c_boardinfo(master, node, reg); + ret =3D i3c_master_add_i2c_boardinfo(master, fwnode, reg); else - ret =3D of_i3c_master_add_i3c_boardinfo(master, node, reg); + ret =3D i3c_master_add_i3c_boardinfo(master, fwnode, reg); =20 return ret; } =20 -static int of_populate_i3c_bus(struct i3c_master_controller *master) +static int fwnode_populate_i3c_bus(struct i3c_master_controller *master) { struct device *dev =3D &master->dev; - struct device_node *i3cbus_np =3D dev->of_node; + struct fwnode_handle *fwnode =3D dev_fwnode(dev); int ret; u32 val; =20 - if (!i3cbus_np) + if (!fwnode) return 0; =20 - for_each_available_child_of_node_scoped(i3cbus_np, node) { - ret =3D of_i3c_master_add_dev(master, node); + fwnode_for_each_available_child_node_scoped(fwnode, child) { + ret =3D i3c_master_add_dev(master, child); if (ret) return ret; } @@ -2530,10 +2537,10 @@ static int of_populate_i3c_bus(struct i3c_master_co= ntroller *master) * on the bus are not supporting typical rates, or if the bus topology * prevents it from using max possible rate. */ - if (!of_property_read_u32(i3cbus_np, "i2c-scl-hz", &val)) + if (!device_property_read_u32(dev, "i2c-scl-hz", &val)) master->bus.scl_rate.i2c =3D val; =20 - if (!of_property_read_u32(i3cbus_np, "i3c-scl-hz", &val)) + if (!device_property_read_u32(dev, "i3c-scl-hz", &val)) master->bus.scl_rate.i3c =3D val; =20 return 0; @@ -2588,7 +2595,7 @@ static u8 i3c_master_i2c_get_lvr(struct i2c_client *c= lient) u8 lvr =3D I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE; u32 reg[3]; =20 - if (!of_property_read_u32_array(client->dev.of_node, "reg", reg, ARRAY_SI= ZE(reg))) + if (!fwnode_property_read_u32_array(client->dev.fwnode, "reg", reg, ARRAY= _SIZE(reg))) lvr =3D reg[2]; =20 return lvr; @@ -2707,7 +2714,8 @@ static int i3c_master_i2c_adapter_init(struct i3c_mas= ter_controller *master) struct i2c_adapter *adap =3D i3c_master_to_i2c_adapter(master); struct i2c_dev_desc *i2cdev; struct i2c_dev_boardinfo *i2cboardinfo; - int ret, id; + struct fwnode_handle *fwnode =3D dev_fwnode(&master->dev); + int ret, id =3D -1; =20 adap->dev.parent =3D master->dev.parent; adap->owner =3D master->dev.parent->driver->owner; @@ -2716,7 +2724,9 @@ static int i3c_master_i2c_adapter_init(struct i3c_mas= ter_controller *master) adap->timeout =3D HZ; adap->retries =3D 3; =20 - id =3D of_alias_get_id(master->dev.of_node, "i2c"); + if (fwnode && is_of_node(fwnode)) + id =3D of_alias_get_id(to_of_node(fwnode), "i2c"); + if (id >=3D 0) { adap->nr =3D id; ret =3D i2c_add_numbered_adapter(adap); @@ -3017,7 +3027,7 @@ int i3c_master_register(struct i3c_master_controller = *master, return ret; =20 master->dev.parent =3D parent; - master->dev.of_node =3D of_node_get(parent->of_node); + device_set_node(&master->dev, fwnode_handle_get(dev_fwnode(parent))); master->dev.bus =3D &i3c_bus_type; master->dev.type =3D &i3c_masterdev_type; master->dev.release =3D i3c_masterdev_release; @@ -3036,13 +3046,13 @@ int i3c_master_register(struct i3c_master_controlle= r *master, master->dev.coherent_dma_mask =3D parent->coherent_dma_mask; master->dev.dma_parms =3D parent->dma_parms; =20 - ret =3D i3c_bus_init(i3cbus, master->dev.of_node); + ret =3D i3c_bus_init(i3cbus, dev_fwnode(&master->dev)); if (ret) goto err_put_dev; =20 dev_set_name(&master->dev, "i3c-%d", i3cbus->id); =20 - ret =3D of_populate_i3c_bus(master); + ret =3D fwnode_populate_i3c_bus(master); if (ret) goto err_put_dev; =20 @@ -3300,11 +3310,14 @@ static int __init i3c_init(void) { int res; =20 - res =3D of_alias_get_highest_id("i3c"); - if (res >=3D 0) { - mutex_lock(&i3c_core_lock); - __i3c_first_dynamic_bus_num =3D res + 1; - mutex_unlock(&i3c_core_lock); + /* of_alias_get_highest_id is DT-specific, only call for DT systems */ + if (IS_ENABLED(CONFIG_OF)) { + res =3D of_alias_get_highest_id("i3c"); + if (res >=3D 0) { + mutex_lock(&i3c_core_lock); + __i3c_first_dynamic_bus_num =3D res + 1; + mutex_unlock(&i3c_core_lock); + } } =20 res =3D bus_register_notifier(&i2c_bus_type, &i2cdev_notifier); diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index 592b646f6134..6b03a3ce574c 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -177,7 +177,8 @@ struct i3c_device_ibi_info { * @pid: I3C Provisioned ID exposed by the device. This is a unique identi= fier * that may be used to attach boardinfo to i3c_dev_desc when the device * does not have a static address - * @of_node: optional DT node in case the device has been described in the= DT + * @fwnode: Firmware node (DT or ACPI) in case the device has been + * described in firmware * * This structure is used to attach board-level information to an I3C devi= ce. * Not all I3C devices connected on the bus will have a boardinfo. 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Read _ADR and LVR from the ACPI resources and extract the data as per the ACPI specification for an I3C bus. Also read mipi-i3c-static-address as per the MIPI DISCO specifications [1] to get the static address to be used. Although the existing subsystem allows host controllers to register through the ACPI table, it was not possible to describe I3C or I2C devices there. This change enables describing the I3C or I2C devices in the ACPI table, which is required if the device is using a static address or if it needs some specific properties to be attached to it. [1] https://www.mipi.org/specifications/disco Signed-off-by: Akhil R --- drivers/i3c/master.c | 101 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 93 insertions(+), 8 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 2c479fecbfdf..15a356a2b3c8 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -2404,12 +2404,31 @@ EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked); =20 #define OF_I3C_REG1_IS_I2C_DEV BIT(31) =20 +static int i3c_acpi_get_i2c_resource(struct acpi_resource *ares, void *dat= a) +{ + struct i2c_dev_boardinfo *boardinfo =3D data; + struct acpi_resource_i2c_serialbus *sb; + + if (!i2c_acpi_get_i2c_resource(ares, &sb)) + return 1; + + boardinfo->base.addr =3D sb->slave_address; + if (sb->access_mode =3D=3D ACPI_I2C_10BIT_MODE) + boardinfo->base.flags |=3D I2C_CLIENT_TEN; + + boardinfo->lvr =3D sb->lvr; + + return 0; +} + static int i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master, struct fwnode_handle *fwnode, u32 *reg) { struct i2c_dev_boardinfo *boardinfo; struct device *dev =3D &master->dev; + struct acpi_device *adev; + LIST_HEAD(resources); int ret; =20 boardinfo =3D devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL); @@ -2420,6 +2439,23 @@ i3c_master_add_i2c_boardinfo(struct i3c_master_contr= oller *master, ret =3D of_i2c_get_board_info(dev, to_of_node(fwnode), &boardinfo->base); if (ret) return ret; + + /* LVR is encoded in reg[2] for Device Tree. */ + boardinfo->lvr =3D reg[2]; + } else if (is_acpi_device_node(fwnode)) { + adev =3D to_acpi_device_node(fwnode); + boardinfo->base.fwnode =3D acpi_fwnode_handle(adev); + + ret =3D acpi_dev_get_resources(adev, &resources, + i3c_acpi_get_i2c_resource, boardinfo); + + if (ret < 0) + return ret; + + acpi_dev_free_resource_list(&resources); + + if (!boardinfo->base.addr) + return -ENODEV; } else { return -EINVAL; } @@ -2434,9 +2470,6 @@ i3c_master_add_i2c_boardinfo(struct i3c_master_contro= ller *master, return -EOPNOTSUPP; } =20 - /* LVR is encoded in reg[2]. */ - boardinfo->lvr =3D reg[2]; - list_add_tail(&boardinfo->node, &master->boardinfo.i2c); fwnode_handle_get(fwnode); =20 @@ -2491,8 +2524,8 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_contro= ller *master, return 0; } =20 -static int i3c_master_add_dev(struct i3c_master_controller *master, - struct fwnode_handle *fwnode) +static int i3c_master_add_of_dev(struct i3c_master_controller *master, + struct fwnode_handle *fwnode) { u32 reg[3]; int ret; @@ -2516,6 +2549,31 @@ static int i3c_master_add_dev(struct i3c_master_cont= roller *master, return ret; } =20 +static int i3c_master_add_acpi_dev(struct i3c_master_controller *master, + struct fwnode_handle *fwnode) +{ + struct acpi_device *adev =3D to_acpi_device_node(fwnode); + acpi_bus_address adr; + u32 reg[3] =3D { 0 }; + + /* + * If the ACPI table entry does not have _ADR method, it's an I2C device + * If the ACPI table entry has _ADR method, it's an I3C device + */ + if (!acpi_has_method(adev->handle, "_ADR")) + return i3c_master_add_i2c_boardinfo(master, fwnode, reg); + + adr =3D acpi_device_adr(adev); + + /* For I3C devices, _ADR will have the 48 bit PID of the device */ + reg[1] =3D upper_32_bits(adr); + reg[2] =3D lower_32_bits(adr); + + fwnode_property_read_u32(fwnode, "mipi-i3c-static-address", ®[0]); + + return i3c_master_add_i3c_boardinfo(master, fwnode, reg); +} + static int fwnode_populate_i3c_bus(struct i3c_master_controller *master) { struct device *dev =3D &master->dev; @@ -2527,7 +2585,13 @@ static int fwnode_populate_i3c_bus(struct i3c_master= _controller *master) return 0; =20 fwnode_for_each_available_child_node_scoped(fwnode, child) { - ret =3D i3c_master_add_dev(master, child); + if (is_of_node(child)) + ret =3D i3c_master_add_of_dev(master, child); + else if (is_acpi_device_node(child)) + ret =3D i3c_master_add_acpi_dev(master, child); + else + continue; + if (ret) return ret; } @@ -2593,10 +2657,31 @@ static u8 i3c_master_i2c_get_lvr(struct i2c_client = *client) { /* Fall back to no spike filters and FM bus mode. */ u8 lvr =3D I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE; 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Wed, 18 Mar 2026 10:29:39 -0700 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 18 Mar 2026 10:29:39 -0700 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 18 Mar 2026 10:29:33 -0700 From: Akhil R To: Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J . Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 05/12] i3c: master: Add support for devices using SETAASA Date: Wed, 18 Mar 2026 22:57:18 +0530 Message-ID: <20260318172820.13771-6-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC3:EE_|IA0PR12MB8086:EE_ X-MS-Office365-Filtering-Correlation-Id: 9652bde6-58cb-40a4-e205-08de8513fc18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|7416014|376014|921020|13003099007|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: Zn6iWMtD7P4lKpo95NKyVP7e/7UMQKWmHP3bPPli2LO/qPbhM0LbqV4yRGGA71IWPHq8CojAef1xXHp0IZN5iItJmw7FUwqw8+TcDIrpw4cjol16e8LqaP2DYZZIL97JTzELovLy+rtuO/IKERxGEr4q+Rgo3LpKtUMkHCs8I6qGyUoMCSQm+Y6ITt4RCRJC0p2hYRkYYk3SXcN2YjpPRW9U2XZz000dsvPldOsNKrDI5udpFj2WWQ3RkBgV9DSZHittu0d3TrDdcKzclWj3nyAly8k43MN9lK3k22aE/isk/2ovUiOvjrv4PHarDBVj0auZqhIcA/C4SDBdzG72lcvlf0s11mHyNdByoc2izLNkZTQgcCg6X0pQjVcsbvQ+NBEbr8+rKZ2o4wAuXBHakozNbhqtm2IVurqQ5LbMeKZex2MSt6aBS6zLRiTDhS0t7zcGnqZTMImnwaGrfQ10Bdwfgcw7EQmsBaSNEVCPqCyXwP83KADimzAXapkaEX9nSbGdg1CnUsgDP//LUmKDRc49UHQT9/+aBg7L3cErg11WLn+xngIi+YAG6v3hF6h0OE3WYojMH9pLChe1PLIZtSCljtH7sbNuwFmoUewYtVsBKDLS/uiBi5trIbgvGDJIY0BFLlxmhsyKBS1YWhhWVFMiIFDl8OW9dMkjeuIfdv7nuuWR/PYz5A0YYbY3I2Myq/s7xtcz56N4ssbCPvMRB/hEUNcp//Ry3l2Nlhs9jhTlFY/CSzdWLDrrXZsmW4tzJa384zN/9RrR666UULAtwECPpaLy2Qo4UM9/KddVCtXGU+W2djIDFX2JxEjFWrIN X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(7416014)(376014)(921020)(13003099007)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bdk4iuB5jDZPx1AmXLwU/PrzTMgLsdAbtYLpg/hsMOiUTAxNCYXo97UhZK2L1T2ZnIvF3yQasGA6sc+/1Bfa6qwDG1rwmDEVIiWr1kNkgsASjZ6Fif2KdtfDSTqCYQIIdTxdNaFVuVM3GXxE5rAFo2sLnP+rZk/LmkF/47uUoei3oEj/AITVq9U92aPHpYTklr23CwTVzvvspB20rc/QJv/vrM8xVMrOMx1rTcTF0t6RCDlzIl1332QxLtmusR1hErz5UwUvXM1nR3uCAnZCUEDGtxwD8xHy9GwQl+7G1VhSYtTKp62vN6tprcx9rlMb7CpOtzxvoyh4HCrpfZE3NPBWrE/3Ynrs6mjR9xjtVvJHq6IZW/+vE2LcUzRohHPRaqcr+TwHhO+lUOIhPGoBINfZv+ZIZubyk9gVVQVpwRicm0aakjCuP2p0Pjubib8o X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:30:01.2228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9652bde6-58cb-40a4-e205-08de8513fc18 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8086 Content-Type: text/plain; charset="utf-8" Add support for devices using SETAASA, such as SPD5118 and SPD5108 attached to DDR5 memory modules that do not support ENTDAA. Follow the guidelines proposed by the MIPI Discovery and Configuration Specification[1] for discovering such devices. SETAASA (Set All Addresses to Static Address) differs from standard I3C address assignment that uses ENTDAA or SETDASA to assign dynamic addresses. Devices using SETAASA assign their pre-defined static addresses as their dynamic addresses during DAA, and it is not mandatory for these devices to implement standard CCC commands like GETPID, GETDCR, or GETBCR. For such devices, it is generally recommended to issue SETHID (specified by JEDEC JESD300) as a prerequisite for SETAASA to stop HID bit flipping. [1] https://www.mipi.org/specifications/disco Signed-off-by: Akhil R --- drivers/i3c/master.c | 72 +++++++++++++++++++++++++++++++++++++- include/linux/i3c/ccc.h | 1 + include/linux/i3c/master.h | 17 +++++++++ 3 files changed, 89 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 15a356a2b3c8..40a3bb734234 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -1049,6 +1049,47 @@ static int i3c_master_rstdaa_locked(struct i3c_maste= r_controller *master, return ret; } =20 +/** + * i3c_master_setaasa_locked() - start a SETAASA procedure (Set All Addres= ses to Static Address) + * @master: I3C master object + * + * Send a SETAASA CCC command to set all attached I3C devices' dynamic add= resses to + * their static address. + * + * This function must be called with the bus lock held in write mode. + * + * First, the SETHID CCC command is sent, followed by the SETAASA CCC. + * + * Return: 0 in case of success, a positive I3C error code if the error is + * one of the official Mx error codes, and a negative error code otherwise. + */ +static int i3c_master_setaasa_locked(struct i3c_master_controller *master) +{ + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + /* + * Send SETHID CCC command. Though it is a standard CCC command specified + * in JESD300-5, we are not defining a separate macro to be explicit that + * the value falls under the vendor specific range. + */ + i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0); + i3c_ccc_cmd_init(&cmd, false, I3C_CCC_VENDOR(0, true), &dest, 1); + ret =3D i3c_master_send_ccc_cmd_locked(master, &cmd); + i3c_ccc_cmd_dest_cleanup(&dest); + if (ret) + return ret; + + /* Send SETAASA CCC command */ + i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0); + i3c_ccc_cmd_init(&cmd, false, I3C_CCC_SETAASA, &dest, 1); + ret =3D i3c_master_send_ccc_cmd_locked(master, &cmd); + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + /** * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment) * procedure @@ -1733,6 +1774,18 @@ static int i3c_master_early_i3c_dev_add(struct i3c_m= aster_controller *master, if (ret) goto err_free_dev; =20 + /* + * For devices using SETAASA instead of ENTDAA, the address is statically + * assigned. Update the dynamic address to the provided static address. + * Reattaching the I3C device is not useful. It is also not mandatory + * for such devices to implement CCC commands like GETPID, GETDCR etc. + * Hence, we can return here. + */ + if (i3cdev->boardinfo->static_addr_method & I3C_ADDR_METHOD_SETAASA) { + i3cdev->info.dyn_addr =3D i3cdev->boardinfo->static_addr; + return 0; + } + ret =3D i3c_master_setdasa_locked(master, i3cdev->info.static_addr, i3cdev->boardinfo->init_dyn_addr); if (ret) @@ -2132,6 +2185,12 @@ static int i3c_master_bus_init(struct i3c_master_con= troller *master) goto err_bus_cleanup; } =20 + if (master->addr_method & I3C_ADDR_METHOD_SETAASA) { + ret =3D i3c_master_setaasa_locked(master); + if (ret) + goto err_bus_cleanup; + } + /* Disable all slave events before starting DAA. */ ret =3D i3c_master_disec_locked(master, I3C_BROADCAST_ADDR, I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR | @@ -2483,7 +2542,7 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_contro= ller *master, struct i3c_dev_boardinfo *boardinfo; struct device *dev =3D &master->dev; enum i3c_addr_slot_status addrstatus; - u32 init_dyn_addr =3D 0; + u32 init_dyn_addr =3D 0, static_addr_method =3D 0; =20 boardinfo =3D devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL); if (!boardinfo) @@ -2511,6 +2570,16 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_contr= oller *master, return -EINVAL; } =20 + if (!fwnode_property_read_u32(fwnode, "mipi-i3c-static-method", &static_a= ddr_method)) { + if (static_addr_method & ~(I3C_ADDR_METHOD_SETDASA | I3C_ADDR_METHOD_SET= AASA)) + dev_warn(dev, "Invalid bits set in mipi-i3c-static-method, ignoring.\n"= ); + else + boardinfo->static_addr_method =3D static_addr_method; + } + + /* Update the address methods required for device discovery */ + master->addr_method |=3D boardinfo->static_addr_method; + boardinfo->pid =3D ((u64)reg[1] << 32) | reg[2]; =20 if ((boardinfo->pid & GENMASK_ULL(63, 48)) || @@ -3118,6 +3187,7 @@ int i3c_master_register(struct i3c_master_controller = *master, master->dev.release =3D i3c_masterdev_release; master->ops =3D ops; master->secondary =3D secondary; + master->addr_method =3D I3C_ADDR_METHOD_SETDASA; INIT_LIST_HEAD(&master->boardinfo.i2c); INIT_LIST_HEAD(&master->boardinfo.i3c); =20 diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h index ad59a4ae60d1..a145d766ab6f 100644 --- a/include/linux/i3c/ccc.h +++ b/include/linux/i3c/ccc.h @@ -32,6 +32,7 @@ #define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true) #define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true) #define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true) +#define I3C_CCC_SETAASA I3C_CCC_ID(0x29, true) =20 /* Unicast-only commands */ #define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false) diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index 6b03a3ce574c..71802d9b5943 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -174,6 +174,14 @@ struct i3c_device_ibi_info { * assigned a dynamic address by the master. Will be used during * bus initialization to assign it a specific dynamic address * before starting DAA (Dynamic Address Assignment) + * @static_addr_method: Bitmap describing which methods of Dynamic Address + * Assignment from a Static Address are supported by this I3C Target. + * A value of 1 in a bit position indicates that the Bus Controller + * supports that method, and a value of 0 indicates that the Bus + * Controller does not support that method. + * Bit 0: SETDASA + * Bit 1: SETAASA + * All other bits are reserved. * @pid: I3C Provisioned ID exposed by the device. This is a unique identi= fier * that may be used to attach boardinfo to i3c_dev_desc when the device * does not have a static address @@ -189,6 +197,7 @@ struct i3c_dev_boardinfo { struct list_head node; u8 init_dyn_addr; u8 static_addr; + u8 static_addr_method; u64 pid; struct fwnode_handle *fwnode; }; @@ -498,6 +507,8 @@ struct i3c_master_controller_ops { unsigned long dev_nack_retry_cnt); }; =20 +#define I3C_ADDR_METHOD_SETDASA BIT(0) +#define I3C_ADDR_METHOD_SETAASA BIT(1) /** * struct i3c_master_controller - I3C master controller object * @dev: device to be registered to the device-model @@ -516,6 +527,11 @@ struct i3c_master_controller_ops { * @boardinfo.i2c: list of I2C boardinfo objects * @boardinfo: board-level information attached to devices connected on th= e bus * @bus: I3C bus exposed by this master + * @addr_method: Bitmap describing which methods of Address Assignment req= uired + * to be run for discovering all the devices on the bus. + * Bit 0: SETDASA + * Bit 1: SETAASA + * All other bits are reserved. * @wq: workqueue which can be used by master * drivers if they need to postpone operations that need to take place * in a thread context. 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Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 06/12] i3c: master: Add support for devices without PID Date: Wed, 18 Mar 2026 22:57:19 +0530 Message-ID: <20260318172820.13771-7-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E81:EE_|MN2PR12MB4359:EE_ X-MS-Office365-Filtering-Correlation-Id: 60a35f49-eff1-4d27-f478-08de85140025 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|82310400026|36860700016|921020|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: Gnv9S+N8z9E69YhHPo/8Daecjrt7FhfOQLS6es1Nf8+Y7GMcTobDj9+K1rUefJupfmPXXhhVL4J8yQ9O5VntOYJ7kzGfXc+NPxV7+pFi1JxPIiQBXGxdNJniA3T7r0I7CpvTYhNFFZvQbavDYxIoofYvX+84wbcrMoDWEZbGpOaHkLNjzeMBiF1MD/3Hjv+5sQ1kqppTBGyoq7Biwe9X+63DXJ78POl7kiLW7J13NomEflTW7m7GihjSZq6u2/OKt5Geg8OmszZnlwRnVlS/hte7gChC7y67U9yGuelFv1uTjWln2EWAvZ8l0oR7vQeli+lV9oPMvO4ICOphuj9EwfrQ9Gb7TpkmHheL3Y87jZBe6b/Ey1IiAY8AOiIp1oAvsVndtMV4HDiAZUJ9juGRwjJQYuAU06PotfK+aebGQCRTRI7HgSIcUb+recnJbAO4jxIoNcjQ9ltynVS44ULkmuLushxztEt4CbD6qAqPrmOokfkep0d3OKYKjQcu/YJ906UCkJOA1jKjknoyEAdxeFmdAqGvoT56GwSn2w3WnwpESMQGOgyypOFkzUJk5HbZKM1ySzdJK6jZNGi/mjs7xtK1o6NPcGPYQ+dNL4tnmzYDSX2iMTNtpyFm0cHnC83Z8y+kRy27FimJGhYwMR5bv8V+CYrEs/7qkhNRME6v+GcRPe6owDe+1oSNAnKE0mxjxG2LStv3xRKLgBDcoK6lkGb1EF3TYm6idDPXxtMA0I7u9S5+v4SA45nmeSVUQhgNYKqFh1/lIWsd8KDVgBsRlC1EWmDFcmZ3DsViimrwxvrFSI/Js30iCZXgM7x6T90I X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(82310400026)(36860700016)(921020)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GmvKvUX3gJtj0WxLZGBgXhIZmknL8U3wLDF/85e3e+wNB3N+DRDvoIkKaAPX5KNoVCAn1Npf3w18K6bmX9B5xMPiBKiLr2zMhMQRdzhzkr0KAMWUx/2cDTS3rNI0maJMlLChbzHgj6RY2gYxuwWtJfLFkyBbaWbvFf6oigHii5jRYv7ZyLQ9etXsc4tzfz6KqYjqFHzczEIz63IN0a8WTg0nA98DQcQ/71DYAA6BV/Hw7ytvOlAp+QlBW8aYKWoN5rNNSQhC2n3ZYVoJyXGfLtUS56AD5INbBSITx6x1q0pcbwhaBxHchopztp77fz+hD/ie+194ikP/XaIAZbpEucplX0jLx5f/R5yRdHk73f5D7rZf5KDgftdTy3BM+hQggxeGlUA7mZJZaZc28AOuRc9WKCC13DOvWYMEo90ONT+LeX4/r39MlunEtJcNom9k X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:30:08.0541 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60a35f49-eff1-4d27-f478-08de85140025 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E81.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4359 Content-Type: text/plain; charset="utf-8" Devices using SETAASA for address assignment are not required to have a 48-bit PID according to the I3C specification. Allow such devices to register and use the static address where PID was required. Signed-off-by: Akhil R --- drivers/i3c/master.c | 51 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 11 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 40a3bb734234..0cce75bb05b0 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -1835,8 +1835,17 @@ i3c_master_register_new_i3c_devs(struct i3c_master_c= ontroller *master) desc->dev->dev.type =3D &i3c_device_type; desc->dev->dev.bus =3D &i3c_bus_type; desc->dev->dev.release =3D i3c_device_release; - dev_set_name(&desc->dev->dev, "%d-%llx", master->bus.id, - desc->info.pid); + + /* + * For devices without PID (e.g., SETAASA devices), use + * static address for naming instead. + */ + if (desc->info.pid) + dev_set_name(&desc->dev->dev, "%d-%llx", master->bus.id, + desc->info.pid); + else + dev_set_name(&desc->dev->dev, "%d-static_addr-%02x", master->bus.id, + desc->info.static_addr); =20 if (desc->boardinfo) device_set_node(&desc->dev->dev, desc->boardinfo->fwnode); @@ -2281,8 +2290,18 @@ static void i3c_master_attach_boardinfo(struct i3c_d= ev_desc *i3cdev) struct i3c_dev_boardinfo *i3cboardinfo; =20 list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) { - if (i3cdev->info.pid !=3D i3cboardinfo->pid) - continue; + /* + * For devices without PID (e.g., SETAASA devices), match by + * static address. For devices with PID, match by PID. + */ + if (i3cboardinfo->pid) { + if (i3cdev->info.pid !=3D i3cboardinfo->pid) + continue; + } else { + if (!i3cboardinfo->static_addr || + i3cdev->info.static_addr !=3D i3cboardinfo->static_addr) + continue; + } =20 i3cdev->boardinfo =3D i3cboardinfo; i3cdev->info.static_addr =3D i3cboardinfo->static_addr; @@ -2296,8 +2315,12 @@ i3c_master_search_i3c_dev_duplicate(struct i3c_dev_d= esc *refdev) struct i3c_master_controller *master =3D i3c_dev_get_master(refdev); struct i3c_dev_desc *i3cdev; =20 + if (!refdev->info.pid) + return NULL; + i3c_bus_for_each_i3cdev(&master->bus, i3cdev) { - if (i3cdev !=3D refdev && i3cdev->info.pid =3D=3D refdev->info.pid) + if (i3cdev !=3D refdev && i3cdev->info.pid && + i3cdev->info.pid =3D=3D refdev->info.pid) return i3cdev; } =20 @@ -2582,9 +2605,15 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_contr= oller *master, =20 boardinfo->pid =3D ((u64)reg[1] << 32) | reg[2]; =20 - if ((boardinfo->pid & GENMASK_ULL(63, 48)) || - I3C_PID_RND_LOWER_32BITS(boardinfo->pid)) - return -EINVAL; + /* For SETAASA devices, validate the static address instead of PID */ + if (boardinfo->static_addr_method & I3C_ADDR_METHOD_SETAASA) { + if (!boardinfo->static_addr) + return -EINVAL; + } else { + if ((boardinfo->pid & GENMASK_ULL(63, 48)) || + I3C_PID_RND_LOWER_32BITS(boardinfo->pid)) + return -EINVAL; + } =20 boardinfo->init_dyn_addr =3D init_dyn_addr; boardinfo->fwnode =3D fwnode_handle_get(fwnode); @@ -2607,10 +2636,10 @@ static int i3c_master_add_of_dev(struct i3c_master_= controller *master, return ret; =20 /* - * The manufacturer ID can't be 0. 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Allow such devices to be matched through Device Tree or ACPI Signed-off-by: Akhil R --- drivers/i3c/master.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 0cce75bb05b0..ef96518558fb 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -342,15 +343,32 @@ static int i3c_device_match(struct device *dev, const= struct device_driver *drv) { struct i3c_device *i3cdev; const struct i3c_driver *i3cdrv; + u8 static_addr_method =3D 0; =20 if (dev->type !=3D &i3c_device_type) return 0; =20 i3cdev =3D dev_to_i3cdev(dev); i3cdrv =3D drv_to_i3cdrv(drv); - if (i3c_device_match_id(i3cdev, i3cdrv->id_table)) + + if (i3cdev->desc && i3cdev->desc->boardinfo) + static_addr_method =3D i3cdev->desc->boardinfo->static_addr_method; + + /* + * SETAASA based device need not always have a matching ID since + * it is not mandatory for such devices to implement deviceinfo + * CCC commands. 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Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 08/12] i3c: dw-i3c-master: Add SETAASA as supported CCC Date: Wed, 18 Mar 2026 22:57:21 +0530 Message-ID: <20260318172820.13771-9-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E84:EE_|CH3PR12MB9732:EE_ X-MS-Office365-Filtering-Correlation-Id: 884ae3a2-6a78-40cf-b49d-08de851412af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|82310400026|1800799024|921020|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: QfMX2ZejuDAvnFte4SMVZoL3NJYAjhhEibjKGFnva4AT3zBYB8iI/xmzL7f73/6EqD/G24DmfciNpQ6rx6n+CKbDrvN8I+oBJd7IaQg575k+e8KLdF4Ovp12IaKTgm2jMl/VePCeUf2YYsMjsLLpysTBMN7zYpmUrGY5vMqvnpH+5RLr200YnEYlbi0hJ/aIf4RkM5d7PXkfcGW5/71cVRq/98vf99e0sEp+a7YFaVPg6fFXI9n8SeH7samm2XQCeVDfUyp8H5OI3/bRX33BUUBynfDycSE6zw5iISnUdwAaGKkegeiqd89evZ3KIbtdVmyvbJuwWxCqZCPPJ004YffnjTWB6aeI59G91bLJ9bg1ZqyEHbXUp56NY4gU0drV0k/wd34u0VNteuoXTuZ1S8hkMqz10PQpLoxKTj3nmGGQ/c60h9YgpIJC5iuWw42ZpseVjTGaXPAPTqU7gSXkwFoJoza7WiwtuF4H6DwqVCQNppWG+wt/frpOxWXIKfVCqUmxBDuP5nv/si5p0SZQhI3FEaXJnhBOL4HWtidfUzoMuB0nP2Kwbe/jdkcE2qzgr12rNbdirq27vkGbHvO5BZ6IgCTNhawhPisySuSVOngubpvRtfpwGqYS+GivEJd1mlLcYoMKTIchwFsNA40sk0kiRYuVeWhTGFFhqTJEGTz376DwcvFFjuMXGa5EF+5QTm5zsnEgyTG/3c8kZm/xgmlKHBOewt+S19zxPhefeWsBd2MuKrJdRUya5AiZAe0/P7G0gSVEgaZMYtXkDdTv83K/1nnarcMmDIob/XDBcmj0DQta4VFqsRD7jY7x6Qgw X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(7416014)(376014)(82310400026)(1800799024)(921020)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: z3IQgpGVQvfsYQlxYy8MKHuhuaXCXbwT/32lnsVCEXC/9HNKUaQVrp+X5Il8hVDZkbZHkKT/QANT8RvPI9N0z+B6UuQk9vvpLTD8pOxOrDFtTeo60NyKIu9OrXX3FRw1BG0BSF07HAKMOuzElMLewj627iuxUw6oEIva4SM5K+3JBumoFVWYRc0wOetiCE8YkRHSCkdMC+FvBhX93CRZn1q+wyC/83eIMMNcRljaLm3hW64JSbnL4DEaMbsLDUYnq/h+NGf1QKHw5TvwkTlXmCUbRVWhTj6vrTedJGpNkeGlNStymIaBxlb2mfr2I0R8eZfli3dae0vF7IAJLPkdLpKNCF5P7nkqWbXHIKQFbZYjTj8nhzAZS81gd/oZAyJz3z7oYAImwRCIfzeGG0+5d7CtJoG89CKFwM1C/HIUZXJlTA4ekqoaMJyC9slzyD+l X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:30:39.1499 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 884ae3a2-6a78-40cf-b49d-08de851412af X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E84.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9732 Content-Type: text/plain; charset="utf-8" Add SETAASA and SETHID to the supported list of CCC commands for DesignWare I3C host controller. SETAASA is a broadcast command that assigns predefined static addresses to all I3C devices on the bus. SETHID stops HID bit flipping by the SPD Hub on which the SPD devices are connected. It is a prerequisite command to be sent before SETAASA as recommended by JESD300-5 and JESD403 sideband bus specifications. Signed-off-by: Akhil R --- drivers/i3c/master/dw-i3c-master.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index d6bdb32397fb..05ccdf177b6d 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -308,6 +308,8 @@ static bool dw_i3c_master_supports_ccc_cmd(struct i3c_m= aster_controller *m, case I3C_CCC_GETSTATUS: case I3C_CCC_GETMXDS: case I3C_CCC_GETHDRCAP: + case I3C_CCC_SETAASA: + case I3C_CCC_VENDOR(0, true): /* SETHID */ return true; default: return false; --=20 2.50.1 From nobody Mon Apr 6 16:28:11 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013005.outbound.protection.outlook.com [40.107.201.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA1E93101A7; Wed, 18 Mar 2026 17:30:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 09/12] i3c: dw-i3c-master: Add a quirk to skip clock and reset Date: Wed, 18 Mar 2026 22:57:22 +0530 Message-ID: <20260318172820.13771-10-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC9:EE_|BL1PR12MB5780:EE_ X-MS-Office365-Filtering-Correlation-Id: bfafbbe6-e565-47db-5f2d-08de851418c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|82310400026|36860700016|921020|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: b+GaeNpmgpYp1qF80LYMDsZXBHx38qxiGexE+h3CdxXBmevtzFnBX3xfA5YYqwpf0hbozuVuG/NlhKpBFnLchKEx9jz5X6fSzyu2ky1TvwRJificrkDO3MHmNlH7xu7ceZQ7Wy9H/jFMLT34B0jb+UCUw4yLxJD/S+ylQ9aGDDyMw6B7IY7B9Lg0eh7CbMT0LlHc0tjfRmPoSvoSUXBINOeLHKgRoHlRRHW+Qw6gIuKBHOoMFVxKyMAq7ZW5jOm3wFbpGF39HPmZsqV68QLZOP1j69SQMzXUSGo3RuJAF2ben5ePzwMb1b3ZcS8YbVkF/Dy5E5D91A6FEIcnOrY9dKJuGuaIKrDGUgt/gX7qWlM5LOJ52C2EVz4pneJWRTUAPGoHa8mSuMhCUPSI7fJxmQ34NIBylVXM7pn5m9O+pRpGj9SiUnbQpdUWnXUBpoVNGWsK8u93Pz+7GxigSLkP2S9k/RHaO1CVUq+rUnLyEavgt0+diEIT1g4QXlJllYKqT9LiipycIEUMfHFcdV2kKXkVRdVVBp623GYwIsAIYvfhZH2Kor4dAHDjzuboh8UIHnVnVOp5bIJGgg34fQjpspv5o1g5fac+ci9iS9f9pDPP4XfvON4wdoUvwxfuMBM3k8LDqddAgmmGkICM4BbC/VCj11789nRHp2JcDzeLcKNjGp6tWgnmDYvvKsRDbCgK9f/7Yp0hbxCXraTFL2C/ODh7tGIlalP6V0rnS4rKrL0wGwovmuGxU6g4y4/sWmet8IV4xfEk57XnFuVdNFRre/OzLEBbvhKDCDZNmoDLpBIvqQudAL+C5yrtCEwGIQEl X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(82310400026)(36860700016)(921020)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rZ6UIEnzdKdO2AOddqTqGeGw/dUWYkS+2kyMPnf4TTu5Lksky1BunkQ/wBFliENJcHsB1nDPPGMvUZe+rXzaKB/zN2l1oBdQ7qMh5Qw9x1kkKiyclQ/ikMgaH5Fqdso458wjT2EsN3qUsScdTyJd+wWDeBpaQlGf//w3djWFQ+WZIyJw5ebpQftKHUOx1vP5z2VtSwDTewnuxdJevTnjAet0Xl6oOnuPHSvmm3tszqn/esgJ/48F7xZgzhGFPXgPwPX8X/Z0HOB0I7qEBQthCiV0NlBzkGHhUcVeRzCJl6wKJ5fP2YwafB39/Bdo/XiHWfece/82GeAp7V1IP85piGYgWDuSAtadZjOvVF2ww3Xzhncj3Jg47gLsVojH+lkVqog6J9DzH5GP75zMHVgGiVnJJBzYSJh4bqe6eo4MRr9z15D8P8qXAPgs+EHyz3ZI X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:30:49.3335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bfafbbe6-e565-47db-5f2d-08de851418c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5780 Content-Type: text/plain; charset="utf-8" Some ACPI-enumerated devices like Tegra410 do not have clock and reset resources exposed via the clk/reset frameworks. Add a match data for such devices to skip acquiring clock and reset controls during probe. Move match data parsing before clock/reset acquisition so the quirk is available early enough. When the quirk is set, fall back to reading the clock rate from the "clock-frequency" device property instead. Signed-off-by: Akhil R --- drivers/i3c/master/dw-i3c-master.c | 57 +++++++++++++++++++----------- 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 05ccdf177b6d..2dae63983303 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -241,6 +241,7 @@ /* List of quirks */ #define AMD_I3C_OD_PP_TIMING BIT(1) #define DW_I3C_DISABLE_RUNTIME_PM_QUIRK BIT(2) +#define DW_I3C_ACPI_SKIP_CLK_RST BIT(3) =20 struct dw_i3c_cmd { u32 cmd_lo; @@ -560,13 +561,26 @@ static void dw_i3c_master_set_intr_regs(struct dw_i3c= _master *master) writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); } =20 +static unsigned long dw_i3c_master_get_core_rate(struct dw_i3c_master *mas= ter) +{ + unsigned int core_rate_prop; + + if (!(master->quirks & DW_I3C_ACPI_SKIP_CLK_RST)) + return clk_get_rate(master->core_clk); + + if (device_property_read_u32(master->dev, "clock-frequency", &core_rate_p= rop)) + return 0; + + return core_rate_prop; +} + static int dw_i3c_clk_cfg(struct dw_i3c_master *master) { unsigned long core_rate, core_period; u32 scl_timing; u8 hcnt, lcnt; =20 - core_rate =3D clk_get_rate(master->core_clk); + core_rate =3D dw_i3c_master_get_core_rate(master); if (!core_rate) return -EINVAL; =20 @@ -619,7 +633,7 @@ static int dw_i2c_clk_cfg(struct dw_i3c_master *master) u16 hcnt, lcnt; u32 scl_timing; =20 - core_rate =3D clk_get_rate(master->core_clk); + core_rate =3D dw_i3c_master_get_core_rate(master); if (!core_rate) return -EINVAL; =20 @@ -1600,21 +1614,31 @@ int dw_i3c_common_probe(struct dw_i3c_master *maste= r, if (IS_ERR(master->regs)) return PTR_ERR(master->regs); =20 - master->core_clk =3D devm_clk_get_enabled(&pdev->dev, NULL); - if (IS_ERR(master->core_clk)) - return PTR_ERR(master->core_clk); + if (has_acpi_companion(&pdev->dev)) { + quirks =3D (unsigned long)device_get_match_data(&pdev->dev); + } else if (pdev->dev.of_node) { + drvdata =3D device_get_match_data(&pdev->dev); + if (drvdata) + quirks =3D drvdata->flags; + } + master->quirks =3D quirks; + + if (!(master->quirks & DW_I3C_ACPI_SKIP_CLK_RST)) { + master->core_clk =3D devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(master->core_clk)) + return PTR_ERR(master->core_clk); + + master->core_rst =3D devm_reset_control_get_optional_exclusive(&pdev->de= v, + "core_rst"); + if (IS_ERR(master->core_rst)) + return PTR_ERR(master->core_rst); + reset_control_deassert(master->core_rst); + } =20 master->pclk =3D devm_clk_get_optional_enabled(&pdev->dev, "pclk"); if (IS_ERR(master->pclk)) return PTR_ERR(master->pclk); =20 - master->core_rst =3D devm_reset_control_get_optional_exclusive(&pdev->dev, - "core_rst"); - if (IS_ERR(master->core_rst)) - return PTR_ERR(master->core_rst); - - reset_control_deassert(master->core_rst); - spin_lock_init(&master->xferqueue.lock); INIT_LIST_HEAD(&master->xferqueue.list); =20 @@ -1647,15 +1671,6 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, master->maxdevs =3D ret >> 16; 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Wed, 18 Mar 2026 10:30:35 -0700 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 18 Mar 2026 10:30:35 -0700 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 18 Mar 2026 10:30:28 -0700 From: Akhil R To: Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J . Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 10/12] i3c: dw-i3c-master: Add ACPI ID for Tegra410 Date: Wed, 18 Mar 2026 22:57:23 +0530 Message-ID: <20260318172820.13771-11-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC6:EE_|IA1PR12MB9499:EE_ X-MS-Office365-Filtering-Correlation-Id: f48e201c-7399-48fb-e945-08de85141d2b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|7416014|1800799024|22082099003|56012099003|18002099003|921020; X-Microsoft-Antispam-Message-Info: r/IfTjPUOLAGbixcfG5xmL3CX/JjvbfJBjgRakYTkkkVFNiPiMHZNY1NmmtQTGAp8DQx1JDia5OTX1ktejHkd7dcb+ctDF+mqPzWtkbyKEpO1GQyqH7OLd0+/LQRpGitTpGzhJF0FSNjy6QMbvUW+LJKk+Xd2JBOMomwLNaChdhnneH/5sHpUUazqlNdiQiO/u72uUI6D1CZZ5VjuyyWMKV0dlxDJTYXQYhRTwuoQXJ2UGy3jrUhB4CmmCPcyflyPfPQ7tZ3vcKBTSlX1NNts8ohjXMcPTtK2kvIhDtzCcYLmFRrsuFjfK+BgZxzO7iwMw8UeJtP+BNhXZZenpvz0L41X/PeLE1BWVQe918KZP6B/Zob9NrZUV/W9gTSVKOLB1G+pDPVYuLcGHlue14YwSaOI6bTZWGUOqONhDfbgRgV4ejPfthJWoOXYFW+je/VAQrBO5kG7PcNqI/6/fhx83SXmGVRSM77jgkn47QhfW4NQ+PAbYrBcO2NZzo28BNlgIO5nNxFvJLYmI3diYrfNUAHbcQLgjyoT4WvEAtIgch8D7pQfG6FlkRfeR5fwb6CdzTuOfV3RXjwhUMbRwYb5GyC8chFO6+2mY/HmhJRY7d90G0QJE6b9NVuqRhG72cPD2o1ae0cdJsLNgRLcYmHi3Bllz0hY4WDs5M5lPC3BUZHS9pExgdJwxNQmEVw7+PfwTblSzekfE1J8Iehi3LOVPHFe1qfwo9utGw/63Cstf88wFUONyrGblZiGuvLFB8LRuIq6UN+xnfbP32xdfrld837UmdDFdXnn62I0jzw/CDoKziMHMKJzxJZ+C9hAdMI X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(7416014)(1800799024)(22082099003)(56012099003)(18002099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9AZgzQE6UhrStKZH6G/gMNEjQQ6mH4wXBdoYniyabRHzs81U2/2bMhNiOv1Uo+MfbJgAuSnOVzaKJTViugiKwWwFJmduLfG/cuOtCmERLZAjO8n2f//YyKgPYK4w1MRW8Eq5a1MT3Ln7UpvHzNuJZBStN4VipKHfcRcupZTFgFue+imYKaCnvF+KMDfsEC9F+PMSmTPDfWZNhZ/6crZU0ZwhxGYVxCfJz02v7uAIIF+NUreeeo4MQXjEkrypHfXxi+WRgkpoAk4jiQwqsYeSaIaJtNfic0sZLU/SyIwN01NYo/1XYHr3D2R4j8PeCF5mQ4tkgLHabaju0IXwOfuvFlRKiP8v9TACdiYbnqRtYt6uj4QoECXb+GD6poh3qCU2PUHzN/eJuHcF3kM0thU4V0r8XPZIQx4pwO9icuFmn1ERYR8PwImrmkIniVhikv7+ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:30:56.6993 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f48e201c-7399-48fb-e945-08de85141d2b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9499 Content-Type: text/plain; charset="utf-8" Update variable names to generic names and add Tegra410 ACPI ID to support the I3C controller in Tegra410 which is a DesignWare I3C host controller. Signed-off-by: Akhil R --- drivers/i3c/master/dw-i3c-master.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 2dae63983303..684499ad2047 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -1866,11 +1866,12 @@ static const struct of_device_id dw_i3c_master_of_m= atch[] =3D { }; MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); =20 -static const struct acpi_device_id amd_i3c_device_match[] =3D { +static const struct acpi_device_id dw_i3c_master_acpi_match[] =3D { { "AMDI0015", AMD_I3C_OD_PP_TIMING }, + { "NVDA2018", DW_I3C_ACPI_SKIP_CLK_RST }, { } }; -MODULE_DEVICE_TABLE(acpi, amd_i3c_device_match); +MODULE_DEVICE_TABLE(acpi, dw_i3c_master_acpi_match); =20 static struct platform_driver dw_i3c_driver =3D { .probe =3D dw_i3c_probe, @@ -1879,7 +1880,7 @@ static struct platform_driver dw_i3c_driver =3D { .driver =3D { .name =3D "dw-i3c-master", .of_match_table =3D dw_i3c_master_of_match, - .acpi_match_table =3D amd_i3c_device_match, + .acpi_match_table =3D dw_i3c_master_acpi_match, .pm =3D &dw_i3c_pm_ops, }, }; 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Wed, 18 Mar 2026 10:30:41 -0700 From: Akhil R To: Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J . Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 11/12] hwmon: spd5118: Add I3C support Date: Wed, 18 Mar 2026 22:57:24 +0530 Message-ID: <20260318172820.13771-12-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC2:EE_|SJ0PR12MB7065:EE_ X-MS-Office365-Filtering-Correlation-Id: e42a1def-1e8b-4349-3e75-08de8514278d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700016|1800799024|56012099003|22082099003|18002099003|921020; X-Microsoft-Antispam-Message-Info: NunfodOLx3bFHF5dBR9JbioaSlvqxddrnb91llFFwfi+ZhD3+CmbKoRrZqzXKtlYKD8wwg+hiqZMulAg3uXN+d45Tgmmf3+nECfy5jDtl6KzW9KhtTlX8VjRGLGP+BORxQS0cmM1LoL6NZFm85ey9Cik+L1ccWlLV2QVYxRZfHQvoz2Trb3AQ9LxXj2RU9NhIUT7UdATSSPfuMNIxrgV9MQJKM3rK9bhBhQSKRhploCrpxIkc9gw4RPyoKodx7PkISU1tXnqX8UrhrDJaVESrIKxyD5BH7lRppUy+tuGNnkAtZDiJ8sLvzbr7tBIBzEErWG9DemQ71lCsI1bBdt0RVTbMoOL3slBSaZNVd2aPY0mcsbHtlKsV9HwJJ/xePap6nzxBEGQw6EVxufG4zE856leUulsRgAHiQA71SPjXLy1PYT7Jcyhqeely6wP3S+JvXYzdqXYWCK0vDdcQLmxXa/UEiYkEPO77DYG0dUMJraCaMPTPbMXAZcbUNSFmge2xSPHl5SVwswy1JVFM0rvyWcYrr74CUl3G/eWsy0gxgCZwN5L0LsAkHDRbafphz/YSUIsnrA8D9AG2TCiKquOWJBgn349prKr5arHDiVg4AVzggiR7K+YhvNFFeUXlcYNZ3UES/v0ZpfNqvYXZrVD9DFDK8yf/VbSYJ7BBuxsoLror7pKtUGrfiQ2rbYhefr+5fpMNT0BC9nYUztr9XDAC3yiuc+R6O6yjBLB8juru8ZlABL0AyhhzDcVODeyPMvev8ucWu74UTi3D0mFU1f6nAGzDK8MCXz6ejskJyKvUn+8UAJ+EJX97DwZeD1Mw3uW X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700016)(1800799024)(56012099003)(22082099003)(18002099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: n6jvyDjR2rCdiPNcZrjxzPiViE4q6+DN+6niIfjcQnuom66IaFG65SeIYAd37ADpf26uZhLkE9IbCoK9W+nyG4e3p4IFCKjqmrQ+Pmc9xu1IMZC/yGdJpWhywLmLyygkSsWg9+cs9xxyojaVG7LJbaFsFRQbCSrZSSQ4p+Wv4rHQv2sTrxlkTVw6UUFDuoFMjuhBb3p7opXbKl49lj8ibYmX2rKY6HZ81+NVs2HwbgAo3AEYKHPC/a8RlPcC/+PTlaQoZQIe5nBXX/QOoXQL+POPl7FJr6HjyGrA1jDE9Ag8k87d3BukYuVt9WqtHvZ6GLnVmEZuE4bE5gMao3u90XGCvlT3p2c6OgUx1pPU/QIzfGGe4IdOyp88tj7uIH/GTAyMdMI3cCnrBicJUoRH16UjCglB4v+zsxmu8uiH+jZdKOyWEU6RQmBPz/0VXMOI X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:31:14.1167 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e42a1def-1e8b-4349-3e75-08de8514278d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7065 Add a regmap config and a probe function to support for I3C based communication to SPD5118 devices. On an I3C bus, SPD5118 are enumerated via SETAASA and always require an ACPI or device tree entry. The device matching is hence through the OF match tables only and do not need an I3C class match table. The device identity is verified in the type registers before proceeding to the common probe function. Signed-off-by: Akhil R --- drivers/hwmon/Kconfig | 7 +++-- drivers/hwmon/spd5118.c | 66 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 70 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 8af80e17d25e..23604c05ad22 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -2300,10 +2300,13 @@ config SENSORS_SPD5118 tristate "SPD5118 Compliant Temperature Sensors" depends on I2C select REGMAP_I2C + select REGMAP_I3C if I3C help If you say yes here you get support for SPD5118 (JEDEC JESD300) - compliant temperature sensors. Such sensors are found on DDR5 memory - modules. + compliant temperature sensors using I2C or I3C bus interface. + Such sensors are found on DDR5 memory modules. + + This driver supports both I2C and I3C interfaces. =20 This driver can also be built as a module. If so, the module will be called spd5118. diff --git a/drivers/hwmon/spd5118.c b/drivers/hwmon/spd5118.c index 5da44571b6a0..d70123e10616 100644 --- a/drivers/hwmon/spd5118.c +++ b/drivers/hwmon/spd5118.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -482,6 +483,25 @@ static const struct regmap_config spd5118_regmap16_con= fig =3D { .cache_type =3D REGCACHE_MAPLE, }; =20 +/* + * I3C uses 2-byte register addressing - + * Byte 1: MemReg | BlkAddr[0] | Address[5:0] + * Byte 2: 0000 | BlkAddr[4:1] + * + * The low byte carries the register/NVM address and the high byte carries= the + * upper block address bits, so little-endian format is required. No range + * config is needed since I3C does not use MR11 page switching. + */ +static const struct regmap_config spd5118_regmap_i3c_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x7ff, + .reg_format_endian =3D REGMAP_ENDIAN_LITTLE, + .writeable_reg =3D spd5118_writeable_reg, + .volatile_reg =3D spd5118_volatile_reg, + .cache_type =3D REGCACHE_MAPLE, +}; + static int spd5118_suspend(struct device *dev) { struct spd5118_data *data =3D dev_get_drvdata(dev); @@ -770,7 +790,51 @@ static struct i2c_driver spd5118_i2c_driver =3D { .address_list =3D IS_ENABLED(CONFIG_SENSORS_SPD5118_DETECT) ? normal_i2c = : NULL, }; =20 -module_i2c_driver(spd5118_i2c_driver); +/* I3C */ + +static int spd5118_i3c_probe(struct i3c_device *i3cdev) +{ + struct device *dev =3D i3cdev_to_dev(i3cdev); + struct regmap *regmap; + unsigned int regval; + int err; + + regmap =3D devm_regmap_init_i3c(i3cdev, &spd5118_regmap_i3c_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n"); + + /* Verify this is a SPD5118 device */ + err =3D regmap_read(regmap, SPD5118_REG_TYPE, ®val); + if (err) + return err; + + if (regval !=3D 0x51) { + dev_err(dev, "unexpected device type 0x%02x, expected 0x51\n", regval); + return -ENODEV; + } + + err =3D regmap_read(regmap, SPD5118_REG_TYPE + 1, ®val); + if (err) + return err; + + if (regval !=3D 0x18) { + dev_err(dev, "unexpected device type 0x%02x, expected 0x18\n", regval); + return -ENODEV; + } + + return spd5118_common_probe(dev, regmap, false); +} + +static struct i3c_driver spd5118_i3c_driver =3D { + .driver =3D { + .name =3D "spd5118_i3c", + .of_match_table =3D spd5118_of_ids, + .pm =3D pm_sleep_ptr(&spd5118_pm_ops), + }, + .probe =3D spd5118_i3c_probe, +}; + +module_i3c_i2c_driver(spd5118_i3c_driver, &spd5118_i2c_driver); =20 MODULE_AUTHOR("Ren=C3=A9 Rebe "); MODULE_AUTHOR("Guenter Roeck "); --=20 2.50.1 From nobody Mon Apr 6 16:28:11 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011058.outbound.protection.outlook.com [40.93.194.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A448231ED91; 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Wysocki" , Robert Moore , "Len Brown" , Guenter Roeck , Philipp Zabel , Eric Biggers , "Fredrik Markstrom" , Miquel Raynal , Thierry Reding , "Jon Hunter" , Suresh Mangipudi , , , , , , , CC: Akhil R Subject: [PATCH 12/12] arm64: defconfig: Enable I3C and SPD5118 hwmon Date: Wed, 18 Mar 2026 22:57:25 +0530 Message-ID: <20260318172820.13771-13-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318172820.13771-1-akhilrajeev@nvidia.com> References: <20260318172820.13771-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E83:EE_|CY8PR12MB7194:EE_ X-MS-Office365-Filtering-Correlation-Id: db6cd285-21cc-42a0-4399-08de85142b13 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|7416014|1800799024|22082099003|18002099003|56012099003|921020; X-Microsoft-Antispam-Message-Info: EVZ7asWHPxrLMG0dLfLDWOa9qTY7WNaE+RRzHojwufeJKRHqDmdQb6iu9M9jQ0hQvOJ/fwqr1KIqrTlFhDf2qdJRlLSO38KtynLceWNcPghMgBneeu4mv0xP2zg+2LWYtV5wPCwo8h+70QWGB7i7ZWO+IODBumxV5IIU4hxfIEyDYZqhiwqs9VTC96UHMBdXHU1wdVnRZOmDo5ZB0C34zjTBxCtx2H3wCo6KfQCJz6Pu0I/2ksjYXTPq4t1McYQfa0nvrg9pYBSGu+tg6wHoJRLd/PtdLDQx02ieqTDoXzIT2HkzOdikoOIuni5lBdVcOIG2hDsU1rwTOjjtWV+tuGz4wApNCenCrZlvkiM790BFfxoOyiqXrAYHTMh+F3JKF6wFBIuXwOr+nGvBb1xPdHYPCVREf8m72DIFbpLIGk3XlQGJciWL3sPNIxXC+Q8cyS3oVc+MbgwX+JpV0Qm2fVtSwVSz4JqmtR4PJTc4MHSjBPTecCuYv5zZZOqI/82w1QQPvDCz5C7FHsR2BPpW+uNrlEXxAJpMZadSh6U6EItE8AEorcUM/84CTpEn0PxTCQskm9Mf2SnBbQ62ut8DczZflCJTN6UNKcj2X6JdMhG8tEdEox6Ju7Lt8ykwtaMyyN1K3oyeP440sfwJbhxumqW4YZHQmSmE+HdC10KoG18SHWhCJiGJkU1pRf9EXMQf4yMwUfxQxSb2jtcTIS6W03Hqzrq63HFaYowrzn3EAEwmgNk9wEpKPERua77n7vvWx+12K7cayWVoDCGoh6tOyxczgbm6U+JnM0IGaJjBDdD6JRS2XQdQJYKP4e84BySP X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(7416014)(1800799024)(22082099003)(18002099003)(56012099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gt8b+Gmpq2EqZ5ko6gsIM7IF3TzXPmUFD7qqHtAmjVKargiVUeJ5eaRgZBjCwwye/lUVAnNIsbCt2dK3redH5tIGPIlK/gjg1sZI7I6OM0+DOgAGlEuhkeK9gQ9X66jEg9YO34BKJwjNU6PFR6FwnlNFX2ctVxazH7+V6QY5m6ws1fgQdFBNHdDUl2/Yf50wYKVzZg/D0pAvh2cR02NXGaC8EpJY7IK/Qw70bs39anli2/PCw2wn1G83hxjbiCPTiBFItr2n4oVeYv1BAUyF/Eusl5Ogqo/6/KDo4uUXPGuKainhdGwXjRF4BJuCy0p9VK+EO/aYrHM+q0q5Re5kd1/rWFgqqGQZeBZyhhQGJgRj1yeVao0vL+6l0ugMauVyyLhKOYwnlPSbHA1gz7fih+Yk7N7ZRBmuGmKZuVikuALtE09oEsvA+/CYenW/92B4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2026 17:31:20.0733 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db6cd285-21cc-42a0-4399-08de85142b13 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E83.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7194 Content-Type: text/plain; charset="utf-8" Add I3C subsystem support, DesignWare I3C master controller, and SPD5118 hwmon sensor as modules to the defconfig. Signed-off-by: Akhil R --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 18881bd239f9..5dde063822cb 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -582,6 +582,8 @@ CONFIG_I2C_UNIPHIER_F=3Dy CONFIG_I2C_XILINX=3Dm CONFIG_I2C_RCAR=3Dy CONFIG_I2C_CROS_EC_TUNNEL=3Dy +CONFIG_I3C=3Dm +CONFIG_DW_I3C_MASTER=3Dm CONFIG_SPI=3Dy CONFIG_SPI_APPLE=3Dm CONFIG_SPI_ARMADA_3700=3Dy @@ -761,6 +763,7 @@ CONFIG_SENSORS_SL28CPLD=3Dm CONFIG_SENSORS_AMC6821=3Dm CONFIG_SENSORS_INA2XX=3Dm CONFIG_SENSORS_INA3221=3Dm +CONFIG_SENSORS_SPD5118=3Dm CONFIG_SENSORS_TMP102=3Dm CONFIG_MISC_RP1=3Dm CONFIG_THERMAL_GOV_POWER_ALLOCATOR=3Dy --=20 2.50.1