From nobody Mon Apr 6 17:24:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 818F53E6DEF; Wed, 18 Mar 2026 15:13:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773846788; cv=none; b=FjjArnK+OalU3OUYbQ8xezMT3LgyMuKapCWuD0zVol1MJFAhuDFBVliO2vNE11EjkAY/vWILcUnYviOxTWswdDAe1X3pCoD0HrybvW7he5HEujyfx3KfN/OCO4+kaoWCKL60JhWvar9RR59VD/hvhXpFSZ2m77sIjWifSymeKnI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773846788; c=relaxed/simple; bh=A2HPRLU22tLaQPROKcuT+EewNl+vqKrAxH13T8m/A6Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P88hgtCywn0VOCq7VEecx/+XpVw9JCpr1nDrwNnU1AH5Co+cGOB92Z1yqcvr6Gd2EgCUo+qA4CvKIOm1RDe9UnPQtv2HD5mno+lxrw2prSblRZNruStAol7S+u6pbFPEC1pgTb4z2LcIuagRp6kdYetKWzog9sLSfGLVv306aVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Q+2bQMXz; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Q+2bQMXz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773846786; x=1805382786; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A2HPRLU22tLaQPROKcuT+EewNl+vqKrAxH13T8m/A6Q=; b=Q+2bQMXzPez1zWI6Dm7gpWa6y6n8pO+8W+M2V9VUD4jM7Um9Fkt6CJN3 RPxCPi2cahZv2bcwefcd5j2Fdguud9Lr3iEHUjW9/kDAp7GdnyfiE0I2I YCpyAEdk4/dP+cBIAE9xUAFz7BuWMXEX3sZ52uf3MQ6lxOOCsH1o086TN ASt8zYdGjjRCGCE7hg9KkWz+3VdlIYao0UFrl7XnXMHefuj4T8gb4L/4R 9AHVEiA4kuMp0Bg7WT61owUMmDnsmz1WF0p9gcjIr+5VoOTejHiO33tsA x83FvoryVB3JNS1zqn3eW4YDxhZ5mm9qoYU05/ItcZs2iOK7IG8KIol86 w==; X-CSE-ConnectionGUID: CZbIpzhXS3WdAJonZcsLmQ== X-CSE-MsgGUID: rQsnxEUXRJ6M++3H8upC9w== X-IronPort-AV: E=McAfee;i="6800,10657,11733"; a="75084544" X-IronPort-AV: E=Sophos;i="6.23,127,1770624000"; d="scan'208";a="75084544" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2026 08:13:02 -0700 X-CSE-ConnectionGUID: 2j/rT7HTTxKkpDDexNPmqQ== X-CSE-MsgGUID: K0fmXP2uSQqVvqzpQrwwpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,127,1770624000"; d="scan'208";a="247122454" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 18 Mar 2026 08:12:59 -0700 Received: by black.igk.intel.com (Postfix, from userid 1003) id 10A2C9B; Wed, 18 Mar 2026 16:12:58 +0100 (CET) From: Andy Shevchenko To: Mika Westerberg , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v1 1/5] pinctrl: intel: Improve capability support Date: Wed, 18 Mar 2026 16:10:15 +0100 Message-ID: <20260318151256.2590375-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318151256.2590375-1-andriy.shevchenko@linux.intel.com> References: <20260318151256.2590375-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The register space of a certain capability starts at the offset just after the respective node in the capability list. It means that there are no fixed offsets for them from SoC to SoC generation and they have to be calculated at run-time. Improve capability support by adding the respective calculation algorithm and in the result enable PWM on more platforms that currently may use the wrong register. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/= pinctrl-intel.c index 9d32bb8bc13a..adaa37a42754 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -53,8 +53,6 @@ #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) #define PADOWN_GPP(p) ((p) / 8) =20 -#define PWMC 0x204 - /* Offset from pad_regs */ #define PADCFG0 0x000 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) @@ -1549,8 +1547,10 @@ static int intel_pinctrl_pm_init(struct intel_pinctr= l *pctrl) } =20 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, - struct intel_community *community) + struct intel_community *community, + unsigned short capability_offset) { + void __iomem *base =3D community->regs + capability_offset + 4; static const struct pwm_lpss_boardinfo info =3D { .clk_rate =3D 19200000, .npwm =3D 1, @@ -1564,7 +1564,7 @@ static int intel_pinctrl_probe_pwm(struct intel_pinct= rl *pctrl, if (!IS_REACHABLE(CONFIG_PWM_LPSS)) return 0; =20 - chip =3D devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); + chip =3D devm_pwm_lpss_probe(pctrl->dev, base, &info); return PTR_ERR_OR_ZERO(chip); } =20 @@ -1595,6 +1595,7 @@ int intel_pinctrl_probe(struct platform_device *pdev, =20 for (i =3D 0; i < pctrl->ncommunities; i++) { struct intel_community *community =3D &pctrl->communities[i]; + unsigned short capability_offset[6]; void __iomem *regs; u32 offset; u32 value; @@ -1622,15 +1623,19 @@ int intel_pinctrl_probe(struct platform_device *pde= v, switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) { case CAPLIST_ID_GPIO_HW_INFO: community->features |=3D PINCTRL_FEATURE_GPIO_HW_INFO; + capability_offset[CAPLIST_ID_GPIO_HW_INFO] =3D offset; break; case CAPLIST_ID_PWM: community->features |=3D PINCTRL_FEATURE_PWM; + capability_offset[CAPLIST_ID_PWM] =3D offset; break; case CAPLIST_ID_BLINK: community->features |=3D PINCTRL_FEATURE_BLINK; + capability_offset[CAPLIST_ID_BLINK] =3D offset; break; case CAPLIST_ID_EXP: community->features |=3D PINCTRL_FEATURE_EXP; + capability_offset[CAPLIST_ID_EXP] =3D offset; break; default: break; @@ -1653,7 +1658,7 @@ int intel_pinctrl_probe(struct platform_device *pdev, if (ret) return ret; =20 - ret =3D intel_pinctrl_probe_pwm(pctrl, community); + ret =3D intel_pinctrl_probe_pwm(pctrl, community, capability_offset[CAPL= IST_ID_PWM]); if (ret) return ret; } --=20 2.50.1 From nobody Mon Apr 6 17:24:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 372883E2777; Wed, 18 Mar 2026 15:13:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773846785; cv=none; b=R4u5ud30GhqKxVDjNqKzNjaUrlf7fSwYdwmaSRl/7iv9Nf1k4KSggdA8WUfydTQtJiY6CbZcyBy3UuurORytoD7JGjqTHEF4HpT9gZL0gatJtQPbvSlQOVXHmUgUFi+Utpr6lU4ppXRXNGQjNsY5XHscTK8lybfp/W8FDQoU+5s= ARC-Message-Signature: i=1; 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d="scan'208";a="247122453" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 18 Mar 2026 08:12:59 -0700 Received: by black.igk.intel.com (Postfix, from userid 1003) id 147009D; Wed, 18 Mar 2026 16:12:58 +0100 (CET) From: Andy Shevchenko To: Mika Westerberg , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v1 2/5] pinctrl: intel: Fix the revision for new features (1kOhm PD, HW debouncer) Date: Wed, 18 Mar 2026 16:10:16 +0100 Message-ID: <20260318151256.2590375-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318151256.2590375-1-andriy.shevchenko@linux.intel.com> References: <20260318151256.2590375-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 1kOhm pull down and hardware debouncer are features of the revision 0.92 of the Chassis specification. Fix that in the code accordingly. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/= pinctrl-intel.c index adaa37a42754..a5a264ba6fbb 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1611,7 +1611,7 @@ int intel_pinctrl_probe(struct platform_device *pdev, value =3D readl(regs + REVID); if (value =3D=3D ~0u) return -ENODEV; - if (((value & REVID_MASK) >> REVID_SHIFT) >=3D 0x94) { + if (((value & REVID_MASK) >> REVID_SHIFT) >=3D 0x92) { community->features |=3D PINCTRL_FEATURE_DEBOUNCE; community->features |=3D PINCTRL_FEATURE_1K_PD; } --=20 2.50.1 From nobody Mon Apr 6 17:24:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 875DB3E63BD; Wed, 18 Mar 2026 15:13:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773846787; cv=none; b=gDjQyCY+PBSETpplXuSxdlc1mLpEcJGG38iFgQ5iBUhnpz221Y96duE/dmJsw61gv94x9MyLAhk0oFyCaPprVkeiO0bjKUPru4OqJnyYuBV3OFv18aZj60n6XC+lHLKK3CgoQm9PtJ2jUDHQ5k3e4mZGd7H+0YQiwYLnRR0TNu8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773846787; c=relaxed/simple; bh=7mKQR6uTf2Wsf//NUwbsAaj+ayneo7o3k7ijJkC7Gqg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aW/rdSJ9hYcSPF2H61i/ieIcYNESCXjoIoxICzKbaNyHldlHnGa49qkQhdI/AIRjNco9GtF2YVHDDmmWGZyF2Qy4n78XoFk07yaDn4JHt+Fj6aeuJ8zBjSMpMpL0dnrxT96nPUlghA88vq8wCYG7wHK8UV5fkKnWzVnQK9TRAoM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=T8B1/GOa; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="T8B1/GOa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773846785; x=1805382785; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7mKQR6uTf2Wsf//NUwbsAaj+ayneo7o3k7ijJkC7Gqg=; b=T8B1/GOa1rP8YrMgJaka5wgxyhUZ9StNopJ+CvPn6qZ+P6KSMB+mMCQ1 MoiI/9KyMvYuTf5sDyrjohI8bI4AEEE0qrPpFTvzI4k6nwPl57gfHAdAw wgFskzRK7vwCQyKnA1hyemQExLNX3W5M6BFoMbWNK4mOsPPNEaNRg73WK t4WToOa+KYG69MkklY+AbUgiXWX5dbkqO46En1EIekFPxBbM2KaJmNaTv qHS6FnFKNf1MnTCWI/Cat2N9I/BDv9vTIeHOIMQZONbXJGbRMI9owehsF WfAlGgTIB46FX2l3hwt63GMohLBNbolQO3xiAbnYOhunD7PWxC9hH1MBH w==; X-CSE-ConnectionGUID: bKzhH/+vQHmSjo0pN0JwtQ== X-CSE-MsgGUID: Xr+4GNUSSfiQgeVs6bjfvw== X-IronPort-AV: E=McAfee;i="6800,10657,11733"; a="75084542" X-IronPort-AV: E=Sophos;i="6.23,127,1770624000"; d="scan'208";a="75084542" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2026 08:13:02 -0700 X-CSE-ConnectionGUID: AUdx3uOuRc63fPqVlBQQuQ== X-CSE-MsgGUID: kXsgylgVS++3PGq6F02fCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,127,1770624000"; d="scan'208";a="247122452" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 18 Mar 2026 08:12:59 -0700 Received: by black.igk.intel.com (Postfix, from userid 1003) id 18AFD9E; Wed, 18 Mar 2026 16:12:58 +0100 (CET) From: Andy Shevchenko To: Mika Westerberg , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v1 3/5] pinctrl: intel: Enable 3-bit PAD_OWN feature Date: Wed, 18 Mar 2026 16:10:17 +0100 Message-ID: <20260318151256.2590375-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318151256.2590375-1-andriy.shevchenko@linux.intel.com> References: <20260318151256.2590375-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Starting from revision 1.1 of the Chassis specification the PAD_OWN is represented by 3 bits instead of 2 bits in the previous revisions. Update the driver to support this feature. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 21 ++++++++++++++++----- drivers/pinctrl/intel/pinctrl-intel.h | 1 + 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/= pinctrl-intel.c index a5a264ba6fbb..97bf5ec78db4 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -203,19 +203,25 @@ static bool intel_pad_owned_by_host(const struct inte= l_pinctrl *pctrl, unsigned community =3D intel_get_community(pctrl, pin); if (!community) return false; - if (!community->padown_offset) + + /* If padown_offset is not provided, assume host ownership */ + padown =3D community->regs + community->padown_offset; + if (padown =3D=3D community->regs) return true; =20 + /* New HW generations have extended PAD_OWN registers */ + if (community->features & PINCTRL_FEATURE_3BIT_PAD_OWN) + return !(readl(padown + pin_to_padno(community, pin) * 4) & 7); + padgrp =3D intel_community_get_padgroup(community, pin); if (!padgrp) return false; =20 gpp_offset =3D padgroup_offset(padgrp, pin); gpp =3D PADOWN_GPP(gpp_offset); - offset =3D community->padown_offset + padgrp->padown_num * 4 + gpp * 4; - padown =3D community->regs + offset; + offset =3D padgrp->padown_num * 4 + gpp * 4; =20 - return !(readl(padown) & PADOWN_MASK(gpp_offset)); + return !(readl(padown + offset) & PADOWN_MASK(gpp_offset)); } =20 static bool intel_pad_acpi_mode(const struct intel_pinctrl *pctrl, unsigne= d int pin) @@ -1597,6 +1603,7 @@ int intel_pinctrl_probe(struct platform_device *pdev, struct intel_community *community =3D &pctrl->communities[i]; unsigned short capability_offset[6]; void __iomem *regs; + u32 revision; u32 offset; u32 value; =20 @@ -1611,10 +1618,14 @@ int intel_pinctrl_probe(struct platform_device *pde= v, value =3D readl(regs + REVID); if (value =3D=3D ~0u) return -ENODEV; - if (((value & REVID_MASK) >> REVID_SHIFT) >=3D 0x92) { + + revision =3D (value & REVID_MASK) >> REVID_SHIFT; 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charset="utf-8" Refactor intel_gpio_add_pin_ranges() to make it shorter in binary and source formats. Function old new delta intel_gpio_add_pin_ranges 219 215 -4 Total: Before=3D15522, After=3D15518, chg -0.03% Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/= pinctrl-intel.c index 97bf5ec78db4..7311b787dfc6 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1361,16 +1361,15 @@ static int intel_gpio_irq_init_hw(struct gpio_chip = *gc) int intel_gpio_add_pin_ranges(struct gpio_chip *gc) { struct intel_pinctrl *pctrl =3D gpiochip_get_data(gc); + const struct device *dev =3D pctrl->dev; const struct intel_community *community; const struct intel_padgroup *grp; int ret; =20 for_each_intel_gpio_group(pctrl, community, grp) { - ret =3D gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), - grp->gpio_base, grp->base, - grp->size); + ret =3D gpiochip_add_pin_range(gc, dev_name(dev), grp->gpio_base, grp->b= ase, grp->size); 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18 Mar 2026 08:13:01 -0700 Received: by black.igk.intel.com (Postfix, from userid 1003) id 219E7A2; Wed, 18 Mar 2026 16:12:58 +0100 (CET) From: Andy Shevchenko To: Mika Westerberg , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v1 5/5] pinctrl: intel: define iterator variables inside for-loop Date: Wed, 18 Mar 2026 16:10:19 +0100 Message-ID: <20260318151256.2590375-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260318151256.2590375-1-andriy.shevchenko@linux.intel.com> References: <20260318151256.2590375-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reduce the scope of the iterator variables by defining them inside the respective for-loops. This makes code more robust against reuse of the same variable in the future, which might lead to some mistakes. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 44 ++++++++++++--------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/= pinctrl-intel.c index 7311b787dfc6..c506f9f343c3 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -431,7 +431,6 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pct= ldev, { struct intel_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); const struct intel_pingroup *grp =3D &pctrl->soc->groups[group]; - int i; =20 guard(raw_spinlock_irqsave)(&pctrl->lock); =20 @@ -439,13 +438,13 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *p= ctldev, * All pins in the groups needs to be accessible and writable * before we can enable the mux for this group. */ - for (i =3D 0; i < grp->grp.npins; i++) { + for (unsigned int i =3D 0; i < grp->grp.npins; i++) { if (!intel_pad_usable(pctrl, grp->grp.pins[i])) return -EBUSY; } =20 /* Now enable the mux setting for each pin in the group */ - for (i =3D 0; i < grp->grp.npins; i++) { + for (unsigned int i =3D 0; i < grp->grp.npins; i++) { void __iomem *padcfg0; u32 value, pmode; =20 @@ -909,12 +908,12 @@ static int intel_config_set(struct pinctrl_dev *pctld= ev, unsigned int pin, unsigned long *configs, unsigned int nconfigs) { struct intel_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); - int i, ret; + int ret; =20 if (!intel_pad_usable(pctrl, pin)) return -ENOTSUPP; =20 - for (i =3D 0; i < nconfigs; i++) { + for (unsigned int i =3D 0; i < nconfigs; i++) { switch (pinconf_to_config_param(configs[i])) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: @@ -1323,9 +1322,8 @@ static void intel_gpio_irq_init(struct intel_pinctrl = *pctrl) =20 for_each_intel_pin_community(pctrl, community) { void __iomem *reg, *is; - unsigned int gpp; =20 - for (gpp =3D 0; gpp < community->ngpps; gpp++) { + for (unsigned int gpp =3D 0; gpp < community->ngpps; gpp++) { reg =3D community->regs + community->ie_offset + gpp * 4; is =3D community->regs + community->is_offset + gpp * 4; =20 @@ -1436,14 +1434,14 @@ static int intel_pinctrl_add_padgroups_by_gpps(stru= ct intel_pinctrl *pctrl, struct intel_community *community) { struct intel_padgroup *gpps; + unsigned int ngpps =3D community->ngpps; unsigned int padown_num =3D 0; - size_t i, ngpps =3D community->ngpps; =20 gpps =3D devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); if (!gpps) return -ENOMEM; =20 - for (i =3D 0; i < ngpps; i++) { + for (unsigned int i =3D 0; i < ngpps; i++) { gpps[i] =3D community->gpps[i]; =20 if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE) @@ -1476,18 +1474,18 @@ static int intel_pinctrl_add_padgroups_by_size(stru= ct intel_pinctrl *pctrl, struct intel_community *community) { struct intel_padgroup *gpps; - unsigned int npins =3D community->npins; + unsigned int npins =3D community->npins, ngpps; unsigned int padown_num =3D 0; - size_t i, ngpps =3D DIV_ROUND_UP(npins, community->gpp_size); =20 if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE) return -EINVAL; =20 + ngpps =3D DIV_ROUND_UP(npins, community->gpp_size); gpps =3D devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); if (!gpps) return -ENOMEM; =20 - for (i =3D 0; i < ngpps; i++) { + for (unsigned int i =3D 0; i < ngpps; i++) { unsigned int gpp_size =3D community->gpp_size; =20 gpps[i].reg_num =3D i; @@ -1513,7 +1511,6 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl= *pctrl) const struct intel_pinctrl_soc_data *soc =3D pctrl->soc; struct intel_community_context *communities; struct intel_pad_context *pads; - int i; =20 pads =3D devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); if (!pads) @@ -1525,7 +1522,7 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl= *pctrl) return -ENOMEM; =20 =20 - for (i =3D 0; i < pctrl->ncommunities; i++) { + for (unsigned int i =3D 0; i < pctrl->ncommunities; i++) { struct intel_community *community =3D &pctrl->communities[i]; u32 *intmask, *hostown; =20 @@ -1578,7 +1575,7 @@ int intel_pinctrl_probe(struct platform_device *pdev, { struct device *dev =3D &pdev->dev; struct intel_pinctrl *pctrl; - int i, ret, irq; + int ret, irq; =20 pctrl =3D devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) @@ -1598,7 +1595,7 @@ int intel_pinctrl_probe(struct platform_device *pdev, if (!pctrl->communities) return -ENOMEM; =20 - for (i =3D 0; i < pctrl->ncommunities; i++) { + for (unsigned int i =3D 0; i < pctrl->ncommunities; i++) { struct intel_community *community =3D &pctrl->communities[i]; unsigned short capability_offset[6]; void __iomem *regs; @@ -1806,10 +1803,9 @@ static int intel_pinctrl_suspend_noirq(struct device= *dev) struct intel_pinctrl *pctrl =3D dev_get_drvdata(dev); struct intel_community_context *communities; struct intel_pad_context *pads; - int i; =20 pads =3D pctrl->context.pads; - for (i =3D 0; i < pctrl->soc->npins; i++) { + for (unsigned int i =3D 0; i < pctrl->soc->npins; i++) { const struct pinctrl_pin_desc *desc =3D &pctrl->soc->pins[i]; void __iomem *padcfg; u32 val; @@ -1828,7 +1824,7 @@ static int intel_pinctrl_suspend_noirq(struct device = *dev) } =20 communities =3D pctrl->context.communities; - for (i =3D 0; i < pctrl->ncommunities; i++) { + for (unsigned int i =3D 0; i < pctrl->ncommunities; i++) { struct intel_community *community =3D &pctrl->communities[i]; void __iomem *base; unsigned int gpp; @@ -1915,13 +1911,12 @@ static int intel_pinctrl_resume_noirq(struct device= *dev) struct intel_pinctrl *pctrl =3D dev_get_drvdata(dev); const struct intel_community_context *communities; const struct intel_pad_context *pads; - int i; =20 /* Mask all interrupts */ intel_gpio_irq_init(pctrl); =20 pads =3D pctrl->context.pads; - for (i =3D 0; i < pctrl->soc->npins; i++) { + for (unsigned int i =3D 0; i < pctrl->soc->npins; i++) { const struct pinctrl_pin_desc *desc =3D &pctrl->soc->pins[i]; =20 if (!(intel_pinctrl_should_save(pctrl, desc->number) || @@ -1938,17 +1933,16 @@ static int intel_pinctrl_resume_noirq(struct device= *dev) } =20 communities =3D pctrl->context.communities; - for (i =3D 0; i < pctrl->ncommunities; i++) { + for (unsigned int i =3D 0; i < pctrl->ncommunities; i++) { struct intel_community *community =3D &pctrl->communities[i]; void __iomem *base; - unsigned int gpp; =20 base =3D community->regs + community->ie_offset; - for (gpp =3D 0; gpp < community->ngpps; gpp++) + for (unsigned int gpp =3D 0; gpp < community->ngpps; gpp++) intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); =20 base =3D community->regs + community->hostown_offset; - for (gpp =3D 0; gpp < community->ngpps; gpp++) + for (unsigned int gpp =3D 0; gpp < community->ngpps; gpp++) intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); } =20 --=20 2.50.1