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Wed, 18 Mar 2026 05:45:11 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Claudiu Beznea , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang Cc: John Madieu , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 4/5] PCI: rzg3s-host: Prepare System Controller handling for multiple PCIe channels Date: Wed, 18 Mar 2026 12:44:49 +0000 Message-ID: <20260318124450.163471-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Prepare the driver to handle multiple PCIe channels with distinct System Controller register sets, as required by RZ/V2H(P). The current design stores a single sysc_info structure per SoC, which is insufficient for multi-channel configurations. Introduce channel identifiers and extend struct rzg3s_pcie_soc_data to hold a sysc_info array indexed per PCIe channel. Add a channel field to struct rzg3s_pcie_host and select the appropriate System Controller information during probe based on the channel. Keep existing single-channel SoCs functionally unchanged while preparing the driver for RZ/V2H(P) multi-channel support. Signed-off-by: Lad Prabhakar --- drivers/pci/controller/pcie-rzg3s-host.c | 48 ++++++++++++++++-------- 1 file changed, 33 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index c61e011f8302..a629e861bbd0 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -241,6 +241,18 @@ struct rzg3s_pcie_msi { int irq; }; =20 +/** + * enum rzg3s_pcie_channel_id - RZ/G3S PCIe channel IDs + * @RZG3S_PCIE_CHANNEL_ID_0: PCIe channel 0 + * @RZG3S_PCIE_CHANNEL_ID_1: PCIe channel 1 + * @RZG3S_PCIE_CHANNEL_ID_MAX: Max PCIe channels + */ +enum rzg3s_pcie_channel_id { + RZG3S_PCIE_CHANNEL_ID_0, + RZG3S_PCIE_CHANNEL_ID_1, + RZG3S_PCIE_CHANNEL_ID_MAX, +}; + struct rzg3s_pcie_host; =20 /** @@ -253,7 +265,7 @@ struct rzg3s_pcie_host; * power-on * @cfg_resets: array with the resets that need to be de-asserted after * configuration - * @sysc_info: SYSC info + * @sysc_info: System Controller info for each PCIe channel * @num_power_resets: number of power resets * @num_cfg_resets: number of configuration resets */ @@ -264,7 +276,7 @@ struct rzg3s_pcie_soc_data { int (*config_deinit)(struct rzg3s_pcie_host *host); const char * const *power_resets; const char * const *cfg_resets; - struct rzg3s_sysc_info sysc_info; + struct rzg3s_sysc_info sysc_info[RZG3S_PCIE_CHANNEL_ID_MAX]; u8 num_power_resets; u8 num_cfg_resets; }; @@ -296,6 +308,7 @@ struct rzg3s_pcie_port { * @hw_lock: lock for access to the HW resources * @intx_irqs: INTx interrupts * @max_link_speed: maximum supported link speed + * @channel_id: PCIe channel identifier, used for System Controller access */ struct rzg3s_pcie_host { void __iomem *axi; @@ -311,6 +324,7 @@ struct rzg3s_pcie_host { raw_spinlock_t hw_lock; int intx_irqs[PCI_NUM_INTX]; int max_link_speed; + enum rzg3s_pcie_channel_id channel_id; }; =20 #define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host,= msi) @@ -1698,7 +1712,7 @@ static int rzg3s_pcie_probe(struct platform_device *p= dev) return -ENOMEM; =20 sysc =3D host->sysc; - sysc->info =3D &host->data->sysc_info; + sysc->info =3D &host->data->sysc_info[host->channel_id]; =20 host->axi =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(host->axi)) @@ -1891,10 +1905,12 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_d= ata =3D { .config_deinit =3D rzg3s_pcie_config_deinit, .init_phy =3D rzg3s_soc_pcie_init_phy, .sysc_info =3D { - .functions =3D { - [RZG3S_SYSC_FUNC_ID_RST_RSM_B] =3D { - .offset =3D 0xd74, - .mask =3D BIT(0), + [RZG3S_PCIE_CHANNEL_ID_0] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_RST_RSM_B] =3D { + .offset =3D 0xd74, + .mask =3D BIT(0), + }, }, }, }, @@ -1909,14 +1925,16 @@ static const struct rzg3s_pcie_soc_data rzg3e_soc_d= ata =3D { .config_post_init =3D rzg3e_pcie_config_post_init, .config_deinit =3D rzg3e_pcie_config_deinit, .sysc_info =3D { - .functions =3D { - [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { - .offset =3D 0x1020, - .mask =3D BIT(0), - }, - [RZG3S_SYSC_FUNC_ID_MODE] =3D { - .offset =3D 0x1024, - .mask =3D BIT(0), + [RZG3S_PCIE_CHANNEL_ID_0] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { + .offset =3D 0x1020, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_MODE] =3D { + .offset =3D 0x1024, + .mask =3D BIT(0), + }, }, }, }, --=20 2.53.0