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Wed, 18 Mar 2026 05:45:06 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Claudiu Beznea , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang Cc: John Madieu , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/5] dt-bindings: pci: renesas,r9a08g045-pcie: Add RZ/V2N support Date: Wed, 18 Mar 2026 12:44:46 +0000 Message-ID: <20260318124450.163471-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Document the Renesas RZ/V2N PCIe host controller, which is compatible with the RZ/G3E PCIe IP and therefore uses it as a fallback compatible. The only difference is that it uses device ID 0x003B. Make the binding title generic to avoid extending the title for each new SoC, and update the description to list the supported SoCs and their capabilities. Signed-off-by: Lad Prabhakar --- .../bindings/pci/renesas,r9a08g045-pcie.yaml | 23 ++++++++++++------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.y= aml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml index a67108c48feb..858ec02e6d62 100644 --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml @@ -4,21 +4,27 @@ $id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Renesas RZ/G3S PCIe host controller +title: Renesas RZ/G3S PCIe host controller (and similar SoCs) =20 maintainers: - Claudiu Beznea =20 -description: - Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe - Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and - up to 8 GT/s (Gen3) for RZ/G3E. +description: | + PCIe host controller found in Renesas RZ/G3S and similar SoCs complies + with PCIe Base Specification 4.0 and supports different link speeds + depending on the SoC variant: + - Gen2 (5 GT/s): RZ/G3S + - Gen3 (8 GT/s): RZ/G3E, RZ/V2N =20 properties: compatible: - enum: - - renesas,r9a08g045-pcie # RZ/G3S - - renesas,r9a09g047-pcie # RZ/G3E + oneOf: + - enum: + - renesas,r9a08g045-pcie # RZ/G3S + - renesas,r9a09g047-pcie # RZ/G3E + - items: + - const: renesas,r9a09g056-pcie # RZ/V2N + - const: renesas,r9a09g047-pcie =20 reg: maxItems: 1 @@ -152,6 +158,7 @@ patternProperties: enum: - 0x0033 - 0x0039 + - 0x003B =20 clocks: items: --=20 2.53.0 From nobody Mon Apr 6 18:27:13 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72D763D75AA for ; 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Wed, 18 Mar 2026 05:45:09 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:5f14:a98b:b4be:efbd]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b518985f6sm7888162f8f.25.2026.03.18.05.45.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 05:45:08 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Claudiu Beznea , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang Cc: John Madieu , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/5] dt-bindings: pci: renesas,r9a08g045-pcie: Add RZ/V2H(P) support Date: Wed, 18 Mar 2026 12:44:47 +0000 Message-ID: <20260318124450.163471-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for the PCIe controller found on the RZ/V2H(P) SoC. The RZ/V2H(P) controller is similar to the RZ/G3E variant but includes additional registers and configuration bits for PCIe lane control, and supports multilink operation selectable between a single x4 port or two independent x2 ports. The RZ/V2H(P) SoC supports multilink operation, in which it provides two independent PCIe channels (channel 0 and channel 1). To correctly configure the multilink mode and per-channel PCIe settings in the SYS registers, make the "linux,pci-domain" and "num-lanes" properties mandatory for this SoC and restrict their values as per the SoC requirements. Signed-off-by: Lad Prabhakar --- .../bindings/pci/renesas,r9a08g045-pcie.yaml | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.y= aml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml index 858ec02e6d62..57807d0abd9a 100644 --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml @@ -14,7 +14,7 @@ description: | with PCIe Base Specification 4.0 and supports different link speeds depending on the SoC variant: - Gen2 (5 GT/s): RZ/G3S - - Gen3 (8 GT/s): RZ/G3E, RZ/V2N + - Gen3 (8 GT/s): RZ/G3E, RZ/V2H(P), RZ/V2N =20 properties: compatible: @@ -22,6 +22,7 @@ properties: - enum: - renesas,r9a08g045-pcie # RZ/G3S - renesas,r9a09g047-pcie # RZ/G3E + - renesas,r9a09g057-pcie # RZ/V2H(P) - items: - const: renesas,r9a09g056-pcie # RZ/V2N - const: renesas,r9a09g047-pcie @@ -220,7 +221,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a09g047-pcie + enum: + - renesas,r9a09g047-pcie + - renesas,r9a09g057-pcie then: properties: interrupts: @@ -236,6 +239,21 @@ allOf: reset-names: maxItems: 1 =20 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-pcie + then: + properties: + linux,pci-domain: + enum: [0, 1] + num-lanes: + enum: [2, 4] + required: + - linux,pci-domain + - num-lanes + unevaluatedProperties: false =20 examples: --=20 2.53.0 From nobody Mon Apr 6 18:27:13 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E5F13D6CCA for ; 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Wed, 18 Mar 2026 05:45:10 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:5f14:a98b:b4be:efbd]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b518985f6sm7888162f8f.25.2026.03.18.05.45.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 05:45:09 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Claudiu Beznea , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang Cc: John Madieu , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/5] PCI: rzg3s-host: Use shared reset controls for power domain resets Date: Wed, 18 Mar 2026 12:44:48 +0000 Message-ID: <20260318124450.163471-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Use shared reset controls for PCIe power resets to prepare for RZ/V2H(P) support, where multiple PCIe channels share the same reset line. Signed-off-by: Lad Prabhakar --- drivers/pci/controller/pcie-rzg3s-host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index bfc210e696ed..c61e011f8302 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -1276,9 +1276,9 @@ static int rzg3s_pcie_resets_prepare_and_get(struct r= zg3s_pcie_host *host) for (i =3D 0; i < data->num_cfg_resets; i++) host->cfg_resets[i].id =3D data->cfg_resets[i]; =20 - ret =3D devm_reset_control_bulk_get_exclusive(host->dev, - data->num_power_resets, - host->power_resets); + ret =3D devm_reset_control_bulk_get_shared(host->dev, + data->num_power_resets, + host->power_resets); if (ret) return ret; =20 --=20 2.53.0 From nobody Mon Apr 6 18:27:13 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A6D43D6682 for ; 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Wed, 18 Mar 2026 05:45:11 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:5f14:a98b:b4be:efbd]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b518985f6sm7888162f8f.25.2026.03.18.05.45.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 05:45:11 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Claudiu Beznea , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang Cc: John Madieu , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 4/5] PCI: rzg3s-host: Prepare System Controller handling for multiple PCIe channels Date: Wed, 18 Mar 2026 12:44:49 +0000 Message-ID: <20260318124450.163471-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Prepare the driver to handle multiple PCIe channels with distinct System Controller register sets, as required by RZ/V2H(P). The current design stores a single sysc_info structure per SoC, which is insufficient for multi-channel configurations. Introduce channel identifiers and extend struct rzg3s_pcie_soc_data to hold a sysc_info array indexed per PCIe channel. Add a channel field to struct rzg3s_pcie_host and select the appropriate System Controller information during probe based on the channel. Keep existing single-channel SoCs functionally unchanged while preparing the driver for RZ/V2H(P) multi-channel support. Signed-off-by: Lad Prabhakar --- drivers/pci/controller/pcie-rzg3s-host.c | 48 ++++++++++++++++-------- 1 file changed, 33 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index c61e011f8302..a629e861bbd0 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -241,6 +241,18 @@ struct rzg3s_pcie_msi { int irq; }; =20 +/** + * enum rzg3s_pcie_channel_id - RZ/G3S PCIe channel IDs + * @RZG3S_PCIE_CHANNEL_ID_0: PCIe channel 0 + * @RZG3S_PCIE_CHANNEL_ID_1: PCIe channel 1 + * @RZG3S_PCIE_CHANNEL_ID_MAX: Max PCIe channels + */ +enum rzg3s_pcie_channel_id { + RZG3S_PCIE_CHANNEL_ID_0, + RZG3S_PCIE_CHANNEL_ID_1, + RZG3S_PCIE_CHANNEL_ID_MAX, +}; + struct rzg3s_pcie_host; =20 /** @@ -253,7 +265,7 @@ struct rzg3s_pcie_host; * power-on * @cfg_resets: array with the resets that need to be de-asserted after * configuration - * @sysc_info: SYSC info + * @sysc_info: System Controller info for each PCIe channel * @num_power_resets: number of power resets * @num_cfg_resets: number of configuration resets */ @@ -264,7 +276,7 @@ struct rzg3s_pcie_soc_data { int (*config_deinit)(struct rzg3s_pcie_host *host); const char * const *power_resets; const char * const *cfg_resets; - struct rzg3s_sysc_info sysc_info; + struct rzg3s_sysc_info sysc_info[RZG3S_PCIE_CHANNEL_ID_MAX]; u8 num_power_resets; u8 num_cfg_resets; }; @@ -296,6 +308,7 @@ struct rzg3s_pcie_port { * @hw_lock: lock for access to the HW resources * @intx_irqs: INTx interrupts * @max_link_speed: maximum supported link speed + * @channel_id: PCIe channel identifier, used for System Controller access */ struct rzg3s_pcie_host { void __iomem *axi; @@ -311,6 +324,7 @@ struct rzg3s_pcie_host { raw_spinlock_t hw_lock; int intx_irqs[PCI_NUM_INTX]; int max_link_speed; + enum rzg3s_pcie_channel_id channel_id; }; =20 #define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host,= msi) @@ -1698,7 +1712,7 @@ static int rzg3s_pcie_probe(struct platform_device *p= dev) return -ENOMEM; =20 sysc =3D host->sysc; - sysc->info =3D &host->data->sysc_info; + sysc->info =3D &host->data->sysc_info[host->channel_id]; =20 host->axi =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(host->axi)) @@ -1891,10 +1905,12 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_d= ata =3D { .config_deinit =3D rzg3s_pcie_config_deinit, .init_phy =3D rzg3s_soc_pcie_init_phy, .sysc_info =3D { - .functions =3D { - [RZG3S_SYSC_FUNC_ID_RST_RSM_B] =3D { - .offset =3D 0xd74, - .mask =3D BIT(0), + [RZG3S_PCIE_CHANNEL_ID_0] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_RST_RSM_B] =3D { + .offset =3D 0xd74, + .mask =3D BIT(0), + }, }, }, }, @@ -1909,14 +1925,16 @@ static const struct rzg3s_pcie_soc_data rzg3e_soc_d= ata =3D { .config_post_init =3D rzg3e_pcie_config_post_init, .config_deinit =3D rzg3e_pcie_config_deinit, .sysc_info =3D { - .functions =3D { - [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { - .offset =3D 0x1020, - .mask =3D BIT(0), - }, - [RZG3S_SYSC_FUNC_ID_MODE] =3D { - .offset =3D 0x1024, - .mask =3D BIT(0), + [RZG3S_PCIE_CHANNEL_ID_0] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { + .offset =3D 0x1020, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_MODE] =3D { + .offset =3D 0x1024, + .mask =3D BIT(0), + }, }, }, }, --=20 2.53.0 From nobody Mon Apr 6 18:27:13 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 281763D75BC for ; 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Wed, 18 Mar 2026 05:45:12 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:5f14:a98b:b4be:efbd]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b518985f6sm7888162f8f.25.2026.03.18.05.45.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 05:45:12 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Claudiu Beznea , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang Cc: John Madieu , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 5/5] PCI: rzg3s-host: Add support for RZ/V2H(P) SoC Date: Wed, 18 Mar 2026 12:44:50 +0000 Message-ID: <20260318124450.163471-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for the RZ/V2H(P) SoC PCIe controller to the rzg3s-host driver. The RZ/V2H(P) SoC features two independent PCIe channels that share physical lanes. The hardware supports two configuration modes: single x4 mode where one controller uses all four lanes, or dual x2 mode where both controllers use two lanes each. Introduce configure_lanes() function pointer to configure the PCIe lanes based on the number of channels enabled. Implement rzv2h_pcie_configure_lanes() to detect the active PCIe channels at boot time and program the lane mode via the system controller using the new RZG3S_SYSC_FUNC_ID_LINK_MASTER function ID. Signed-off-by: Lad Prabhakar --- drivers/pci/controller/pcie-rzg3s-host.c | 142 +++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index a629e861bbd0..d1bf1e750d9b 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -179,6 +179,16 @@ /* Timeouts experimentally determined */ #define RZG3S_REQ_ISSUE_TIMEOUT_US 2500 =20 +/** + * enum rzg3s_sysc_link_mode - PCIe link configuration modes + * @RZG3S_SYSC_LINK_MODE_SINGLE_X4: Single port with x4 lanes + * @RZG3S_SYSC_LINK_MODE_DUAL_X2: Dual ports with x2 lanes each + */ +enum rzg3s_sysc_link_mode { + RZG3S_SYSC_LINK_MODE_SINGLE_X4 =3D 1, + RZG3S_SYSC_LINK_MODE_DUAL_X2 =3D 3, +}; + /** * struct rzg3s_sysc_function - System Controller function descriptor * @offset: Register offset from the System Controller base address @@ -194,12 +204,14 @@ struct rzg3s_sysc_function { * @RZG3S_SYSC_FUNC_ID_RST_RSM_B: RST_RSM_B SYSC function ID * @RZG3S_SYSC_FUNC_ID_L1_ALLOW: L1 allow SYSC function ID * @RZG3S_SYSC_FUNC_ID_MODE: Mode SYSC function ID + * @RZG3S_SYSC_FUNC_ID_LINK_MASTER: Link master SYSC function ID * @RZG3S_SYSC_FUNC_ID_MAX: Max SYSC function ID */ enum rzg3s_sysc_func_id { RZG3S_SYSC_FUNC_ID_RST_RSM_B, RZG3S_SYSC_FUNC_ID_L1_ALLOW, RZG3S_SYSC_FUNC_ID_MODE, + RZG3S_SYSC_FUNC_ID_LINK_MASTER, RZG3S_SYSC_FUNC_ID_MAX, }; =20 @@ -261,6 +273,7 @@ struct rzg3s_pcie_host; * @config_pre_init: Optional callback for SoC-specific pre-configuration * @config_post_init: Callback for SoC-specific post-configuration * @config_deinit: Callback for SoC-specific de-initialization + * @setup_lanes: Callback for setting up the number of lanes * @power_resets: array with the resets that need to be de-asserted after * power-on * @cfg_resets: array with the resets that need to be de-asserted after @@ -268,17 +281,20 @@ struct rzg3s_pcie_host; * @sysc_info: System Controller info for each PCIe channel * @num_power_resets: number of power resets * @num_cfg_resets: number of configuration resets + * @num_channels: number of PCIe channels */ struct rzg3s_pcie_soc_data { int (*init_phy)(struct rzg3s_pcie_host *host); void (*config_pre_init)(struct rzg3s_pcie_host *host); int (*config_post_init)(struct rzg3s_pcie_host *host); int (*config_deinit)(struct rzg3s_pcie_host *host); + int (*setup_lanes)(struct rzg3s_pcie_host *host); const char * const *power_resets; const char * const *cfg_resets; struct rzg3s_sysc_info sysc_info[RZG3S_PCIE_CHANNEL_ID_MAX]; u8 num_power_resets; u8 num_cfg_resets; + u8 num_channels; }; =20 /** @@ -309,6 +325,7 @@ struct rzg3s_pcie_port { * @intx_irqs: INTx interrupts * @max_link_speed: maximum supported link speed * @channel_id: PCIe channel identifier, used for System Controller access + * @num_lanes: The number of lanes */ struct rzg3s_pcie_host { void __iomem *axi; @@ -325,6 +342,7 @@ struct rzg3s_pcie_host { int intx_irqs[PCI_NUM_INTX]; int max_link_speed; enum rzg3s_pcie_channel_id channel_id; + u8 num_lanes; }; =20 #define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host,= msi) @@ -1155,6 +1173,13 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_= host *host) rzg3s_pcie_update_bits(host->pcie, PCI_CLASS_REVISION, mask, field_prep(mask, PCI_CLASS_BRIDGE_PCI_NORMAL)); =20 + if (host->num_lanes) { + rzg3s_pcie_update_bits(host->pcie + RZG3S_PCI_CFG_PCIEC, + PCI_EXP_LNKCAP, PCI_EXP_LNKCAP_MLW, + FIELD_PREP(PCI_EXP_LNKCAP_MLW, + host->num_lanes)); + } + /* Disable access control to the CFGU */ writel_relaxed(0, host->axi + RZG3S_PCI_PERM); =20 @@ -1687,6 +1712,63 @@ rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host, return ret; } =20 +static int rzg3s_pcie_get_controller_id(struct rzg3s_pcie_host *host) +{ + struct device_node *np =3D host->dev->of_node; + u32 domain; + int ret; + + if (host->data->num_channels =3D=3D 1) + return 0; + + ret =3D of_property_read_u32(np, "linux,pci-domain", &domain); + if (ret) + return ret; + + if (domain >=3D host->data->num_channels) + return -EINVAL; + + host->channel_id =3D domain; + + return 0; +} + +static int rzv2h_pcie_setup_lanes(struct rzg3s_pcie_host *host) +{ + struct device_node *np =3D host->dev->of_node; + static u8 rzv2h_num_total_lanes; + u32 num_lanes; + int ret; + + ret =3D of_property_read_u32(np, "num-lanes", &num_lanes); + if (ret) + return ret; + + /* + * RZ/V2H(P) supports up to 4 lanes, but only in single x4 mode. + * Dual x2 mode is only supported with 2 total lanes. Validate + * the configuration to avoid conflicts with other host, if any. + */ + if (num_lanes !=3D 4 && num_lanes !=3D 2) + return -EINVAL; + + if (rzv2h_num_total_lanes =3D=3D 2 && num_lanes !=3D 2) + return -EINVAL; + + if (rzv2h_num_total_lanes =3D=3D 4) + return -EINVAL; + + rzv2h_num_total_lanes +=3D num_lanes; + + host->num_lanes =3D num_lanes; + + return rzg3s_sysc_config_func(host->sysc, + RZG3S_SYSC_FUNC_ID_LINK_MASTER, + num_lanes =3D=3D 2 ? + RZG3S_SYSC_LINK_MODE_DUAL_X2 : + RZG3S_SYSC_LINK_MODE_SINGLE_X4); +} + static int rzg3s_pcie_probe(struct platform_device *pdev) { struct pci_host_bridge *bridge; @@ -1711,6 +1793,10 @@ static int rzg3s_pcie_probe(struct platform_device *= pdev) if (!host->sysc) return -ENOMEM; =20 + ret =3D rzg3s_pcie_get_controller_id(host); + if (ret) + return ret; + sysc =3D host->sysc; sysc->info =3D &host->data->sysc_info[host->channel_id]; =20 @@ -1740,6 +1826,12 @@ static int rzg3s_pcie_probe(struct platform_device *= pdev) if (ret) goto port_refclk_put; =20 + if (host->data->setup_lanes) { + ret =3D host->data->setup_lanes(host); + if (ret) + goto sysc_signal_restore; + } + ret =3D rzg3s_pcie_resets_prepare_and_get(host); if (ret) goto sysc_signal_restore; @@ -1901,6 +1993,7 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_dat= a =3D { .num_power_resets =3D ARRAY_SIZE(rzg3s_soc_power_resets), .cfg_resets =3D rzg3s_soc_cfg_resets, .num_cfg_resets =3D ARRAY_SIZE(rzg3s_soc_cfg_resets), + .num_channels =3D 1, .config_post_init =3D rzg3s_pcie_config_post_init, .config_deinit =3D rzg3s_pcie_config_deinit, .init_phy =3D rzg3s_soc_pcie_init_phy, @@ -1921,6 +2014,7 @@ static const char * const rzg3e_soc_power_resets[] = =3D { "aresetn" }; static const struct rzg3s_pcie_soc_data rzg3e_soc_data =3D { .power_resets =3D rzg3e_soc_power_resets, .num_power_resets =3D ARRAY_SIZE(rzg3e_soc_power_resets), + .num_channels =3D 1, .config_pre_init =3D rzg3e_pcie_config_pre_init, .config_post_init =3D rzg3e_pcie_config_post_init, .config_deinit =3D rzg3e_pcie_config_deinit, @@ -1940,6 +2034,50 @@ static const struct rzg3s_pcie_soc_data rzg3e_soc_da= ta =3D { }, }; =20 +static const struct rzg3s_pcie_soc_data rzv2h_soc_data =3D { + .power_resets =3D rzg3e_soc_power_resets, + .num_power_resets =3D ARRAY_SIZE(rzg3e_soc_power_resets), + .num_channels =3D 2, + .config_pre_init =3D rzg3e_pcie_config_pre_init, + .config_post_init =3D rzg3e_pcie_config_post_init, + .config_deinit =3D rzg3e_pcie_config_deinit, + .setup_lanes =3D rzv2h_pcie_setup_lanes, + .sysc_info =3D { + [RZG3S_PCIE_CHANNEL_ID_0] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { + .offset =3D 0x1020, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_MODE] =3D { + .offset =3D 0x1024, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_LINK_MASTER] =3D { + .offset =3D 0x1060, + .mask =3D GENMASK(9, 8), + }, + }, + }, + [RZG3S_PCIE_CHANNEL_ID_1] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { + .offset =3D 0x1050, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_MODE] =3D { + .offset =3D 0x1054, + .mask =3D BIT(0), + }, + [RZG3S_SYSC_FUNC_ID_LINK_MASTER] =3D { + .offset =3D 0x1060, + .mask =3D GENMASK(9, 8), + }, + }, + }, + }, +}; + static const struct of_device_id rzg3s_pcie_of_match[] =3D { { .compatible =3D "renesas,r9a08g045-pcie", @@ -1949,6 +2087,10 @@ static const struct of_device_id rzg3s_pcie_of_match= [] =3D { .compatible =3D "renesas,r9a09g047-pcie", .data =3D &rzg3e_soc_data, }, + { + .compatible =3D "renesas,r9a09g057-pcie", + .data =3D &rzv2h_soc_data, + }, {} }; =20 --=20 2.53.0