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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c0e53b5fa1sm4454521eec.10.2026.03.18.05.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 05:41:20 -0700 (PDT) From: Gopikrishna Garmidi To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sibi.sankar@oss.qualcomm.com, pankaj.patil@oss.qualcomm.com, rajendra.nayak@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, Gopikrishna Garmidi , Raviteja Laggyshetty , Kamal Wadhwa , Manaf Meethalavalappu Pallikunhi Subject: [PATCH v2 3/3] arm64: dts: qcom: Add Mahua SoC and CRD Date: Wed, 18 Mar 2026 05:41:00 -0700 Message-Id: <20260318124100.212992-4-gopikrishna.garmidi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260318124100.212992-1-gopikrishna.garmidi@oss.qualcomm.com> References: <20260318124100.212992-1-gopikrishna.garmidi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=bIcb4f+Z c=1 sm=1 tr=0 ts=69ba9d72 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=4nuuKY_MPYQNcC36K5wA:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: aznbPCqq7yOuALLaTJJar25rKXEr8eJy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDEwOCBTYWx0ZWRfX4y12AOPvikMP lF7Q7PEiWkvW9v4mDP3+uV/XDfu4/ooc4xynUwYa2d9a/gmhGMgUd/h0uzQNfOsplHsei5J6QMv /e8HpXHpeLw/CMKzhf3X9ZJISFnE7jp9gIXNJ8aLCSTvpQZ14VcCtplTLiAv71jKJJRFA7ZIWUE jzmJrOGImvLFaLGXLuYE0EXoWfFTBPWHP9GJIGDG5F9egWi7GscyY7e6H783+hYxv+uP7ITFxDI vsMenrrihVSEu3kksV48SxLr1BHBVrlS+Bq2nUMb1z7zdUqeqVrkOC3SBL9XbYMFFGczoPOB73k 1k7NNLKkbfGgU+1gAfdSxQTZWn2xMhPPloR05nHnnIxv6hqjMRVJrUmIow3VV0wRxW4OVUKuGIB wj2tii7i/9b+zfZpnHc5Lsdn3GsDaH5IcpP0CiBsZMDqDSCObyXUsVE4hNDsEKggFAiE/dBtpaj 6HpYXwF5hGvxwCl8aDA== X-Proofpoint-GUID: aznbPCqq7yOuALLaTJJar25rKXEr8eJy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-18_01,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180108 Content-Type: text/plain; charset="utf-8" Introduce support for the Mahua SoC and the CRD based on it. Some of the notable differences are the absent CPU cluster, interconnect, TLMM, thermal zones and adjusted PCIe west clocks. Everything else should work as-is. Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Gopikrishna Garmidi Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 ++ arch/arm64/boot/dts/qcom/mahua.dtsi | 299 +++++++++++++++++++ arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +- 6 files changed, 325 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 317af937d038..e85ff36012f1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -44,6 +44,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera.dtb lemans-evk-el2-dtbs :=3D lemans-evk.dtb lemans-el2.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index e269cec7942c..4e0b44af073e 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -282,7 +282,7 @@ core5 { }; }; =20 - cluster2 { + cpu_map_cluster2: cluster2 { core0 { cpu =3D <&cpu12>; }; diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/q= com/mahua-crd.dts new file mode 100644 index 000000000000..9c8244e892dd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "mahua.dtsi" +#include "glymur-crd.dtsi" + +/delete-node/ &pmcx0102_d_e0; +/delete-node/ &pmcx0102_d0_thermal; +/delete-node/ &pmh0104_i_e0; +/delete-node/ &pmh0104_i0_thermal; +/delete-node/ &pmh0104_j_e0; +/delete-node/ &pmh0104_j0_thermal; + +/ { + model =3D "Qualcomm Technologies, Inc. Mahua CRD"; + compatible =3D "qcom,mahua-crd", "qcom,mahua"; +}; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi new file mode 100644 index 000000000000..7aa8d26b2b3a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* Mahua is heavily based on Glymur, with some meaningful differences */ +#include "glymur.dtsi" + +/delete-node/ &cluster2_pd; +/delete-node/ &cpu_map_cluster2; +/delete-node/ &cpu12; +/delete-node/ &cpu13; +/delete-node/ &cpu14; +/delete-node/ &cpu15; +/delete-node/ &cpu16; +/delete-node/ &cpu17; +/delete-node/ &cpu_pd12; +/delete-node/ &cpu_pd13; +/delete-node/ &cpu_pd14; +/delete-node/ &cpu_pd15; +/delete-node/ &cpu_pd16; +/delete-node/ &cpu_pd17; +/delete-node/ &tsens6; +/delete-node/ &tsens7; + +&aggre1_noc { + compatible =3D "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc"; +}; + +&aggre2_noc { + compatible =3D "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc"; +}; + +&aggre3_noc { + compatible =3D "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc"; +}; + +&aggre4_noc { + compatible =3D "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc"; +}; + +&clk_virt { + compatible =3D "qcom,mahua-clk-virt", "qcom,glymur-clk-virt"; +}; + +&cnoc_main { + compatible =3D "qcom,mahua-cnoc-main", "qcom,glymur-cnoc-main"; +}; + +&config_noc { + compatible =3D "qcom,mahua-cnoc-cfg"; +}; + +&hsc_noc { + compatible =3D "qcom,mahua-hscnoc"; +}; + +&lpass_ag_noc { + compatible =3D "qcom,mahua-lpass-ag-noc", "qcom,glymur-lpass-ag-noc"; +}; + +&lpass_lpiaon_noc { + compatible =3D "qcom,mahua-lpass-lpiaon-noc", "qcom,glymur-lpass-lpiaon-n= oc"; +}; + +&lpass_lpicx_noc { + compatible =3D "qcom,mahua-lpass-lpicx-noc", "qcom,glymur-lpass-lpicx-noc= "; +}; + +&mc_virt { + compatible =3D "qcom,mahua-mc-virt"; +}; + +&mmss_noc { + compatible =3D "qcom,mahua-mmss-noc", "qcom,glymur-mmss-noc"; +}; + +&nsi_noc { + compatible =3D "qcom,mahua-nsinoc", "qcom,glymur-nsinoc"; +}; + +&nsp_noc { + compatible =3D "qcom,mahua-nsp-noc", "qcom,glymur-nsp-noc"; +}; + +&oobm_ss_noc { + compatible =3D "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; +}; + +&pcie_east_anoc { + compatible =3D "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; +}; + +&pcie_east_slv_noc { + compatible =3D "qcom,mahua-pcie-east-slv-noc", "qcom,glymur-pcie-east-slv= -noc"; +}; + +&pcie_west_anoc { + compatible =3D "qcom,mahua-pcie-west-anoc"; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; +}; + +&pcie_west_slv_noc { + compatible =3D "qcom,mahua-pcie-west-slv-noc"; +}; + +&system_noc { + compatible =3D "qcom,mahua-system-noc", "qcom,glymur-system-noc"; +}; + +&tlmm { + compatible =3D "qcom,mahua-tlmm"; +}; + +&thermal_zones { + /delete-node/ aoss-6-thermal; + /delete-node/ aoss-7-thermal; + /delete-node/ cpu-2-0-0-thermal; + /delete-node/ cpu-2-0-1-thermal; + /delete-node/ cpu-2-1-0-thermal; + /delete-node/ cpu-2-1-1-thermal; + /delete-node/ cpu-2-2-0-thermal; + /delete-node/ cpu-2-2-1-thermal; + /delete-node/ cpu-2-3-0-thermal; + /delete-node/ cpu-2-3-1-thermal; + /delete-node/ cpu-2-4-0-thermal; + /delete-node/ cpu-2-4-1-thermal; + /delete-node/ cpu-2-5-0-thermal; + /delete-node/ cpu-2-5-1-thermal; + /delete-node/ cpullc-2-0-thermal; + /delete-node/ cpuillc-2-1-thermal; + /delete-node/ ddr-2-thermal; + /delete-node/ gpu-3-0-thermal; + /delete-node/ gpu-3-1-thermal; + /delete-node/ gpu-3-2-thermal; + /delete-node/ qmx-2-0-thermal; + /delete-node/ qmx-2-1-thermal; + /delete-node/ qmx-2-2-thermal; + /delete-node/ qmx-2-3-thermal; + /delete-node/ qmx-2-4-thermal; + /delete-node/ video-1-thermal; + + ddr-1-thermal { + thermal-sensors =3D <&tsens1 7>; + }; + + video-0-thermal { + thermal-sensors =3D <&tsens1 8>; + }; + + nsphvx-0-thermal { + thermal-sensors =3D <&tsens4 1>; + }; + + nsphvx-1-thermal { + thermal-sensors =3D <&tsens4 2>; + }; + + nsphvx-2-thermal { + thermal-sensors =3D <&tsens4 3>; + }; + + nsphvx-3-thermal { + thermal-sensors =3D <&tsens4 4>; + }; + + nsphmx-0-thermal { + thermal-sensors =3D <&tsens4 5>; + }; + + nsphmx-1-thermal { + thermal-sensors =3D <&tsens4 6>; + }; + + nsphmx-2-thermal { + thermal-sensors =3D <&tsens4 7>; + }; + + nsphmx-3-thermal { + thermal-sensors =3D <&tsens4 8>; + }; + + camera-0-thermal { + thermal-sensors =3D <&tsens4 9>; + }; + + camera-1-thermal { + thermal-sensors =3D <&tsens4 10>; + }; + + gpu-0-0-thermal { + thermal-sensors =3D <&tsens5 1>; + }; + + gpu-0-1-thermal { + thermal-sensors =3D <&tsens5 2>; + }; + + gpu-0-2-thermal { + thermal-sensors =3D <&tsens5 3>; + }; + + gpu-1-0-thermal { + thermal-sensors =3D <&tsens5 4>; + }; + + gpu-1-1-thermal { + thermal-sensors =3D <&tsens5 5>; + }; + + gpu-1-2-thermal { + thermal-sensors =3D <&tsens5 6>; + }; + + gpu-2-0-thermal { + thermal-sensors =3D <&tsens5 7>; + }; + + gpu-2-1-thermal { + thermal-sensors =3D <&tsens5 8>; + }; + + gpu-2-2-thermal { + thermal-sensors =3D <&tsens5 9>; + }; + + gpuss-0-thermal { + thermal-sensors =3D <&tsens5 10>; + }; + + gpuss-1-thermal { + thermal-sensors =3D <&tsens5 11>; + }; + + gpuss-2-thermal { + thermal-sensors =3D <&tsens5 12>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-3-thermal { + thermal-sensors =3D <&tsens5 13>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-4-thermal { + thermal-sensors =3D <&tsens5 14>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; +}; + +&tsens4 { + #qcom,sensors =3D <11>; +}; + +&tsens5 { + #qcom,sensors =3D <15>; +}; + diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/q= com/pmcx0102.dtsi index c3ccd2b75609..db2da9ef4f01 100644 --- a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi +++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi @@ -46,7 +46,7 @@ trip1 { }; }; =20 - pmcx0102-d0-thermal { + pmcx0102_d0_thermal: pmcx0102-d0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmcx0102_d_e0_temp_alarm>; =20 diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot= /dts/qcom/pmh0104-glymur.dtsi index d89cceda53a3..7a1e5f355c17 100644 --- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -8,7 +8,7 @@ =20 /{ thermal_zones { - pmh0104-i0-thermal { + pmh0104_i0_thermal: pmh0104-i0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmh0104_i_e0_temp_alarm>; =20 @@ -27,7 +27,7 @@ trip1 { }; }; =20 - pmh0104-j0-thermal { + pmh0104_j0_thermal: pmh0104-j0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmh0104_j_e0_temp_alarm>; =20 --=20 2.34.1