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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c0e53b5fa1sm4454521eec.10.2026.03.18.05.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 05:41:15 -0700 (PDT) From: Gopikrishna Garmidi To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sibi.sankar@oss.qualcomm.com, pankaj.patil@oss.qualcomm.com, rajendra.nayak@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, Gopikrishna Garmidi , Krzysztof Kozlowski Subject: [PATCH v2 1/3] dt-bindings: arm: qcom: Document Mahua SoC and board Date: Wed, 18 Mar 2026 05:40:58 -0700 Message-Id: <20260318124100.212992-2-gopikrishna.garmidi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260318124100.212992-1-gopikrishna.garmidi@oss.qualcomm.com> References: <20260318124100.212992-1-gopikrishna.garmidi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDEwOCBTYWx0ZWRfX886zRVYn5x5w ReI5HHWt6dOO/q7V33sHT1Cg5bd6hm/GuP7ea65iPgPl0QWTSZAPR1/V5hYp2+jWwPDbCUVa5CC Ig7G9KsfpNSKXmt95vuMJ3Ij2/yENVJTs5xqPi7Hgxx2beqC1euZXVP8Vbh806SBm2XqZ5R++5r Il24VoU0yuL5gDLuNwq5h8o12nROFoHzGw3YW3oz5l90qpsGclZCQUult8qHNoi3KR4M3lL8fm9 KY5ytOx2HlJ9tzJQBdy7DvmcuU0vO/M3NxXuEK4ZD/2ASN3jHqPMMi4C80VxA2DPFRS261btC+o Ohtr/cly/CzzhiryAuf1blSfzFLkxyYs+fBsCifBrS2SqKb8uLzC9IVLXNCYq8aFP2aJE1wy6LB 51h/K4VSHe4+tRFIrBrrIeuON7cSdSDDza7scx23Txb6/hL2ozup5bwOVcAkVEutCMK5PSp3xLd FuV2OlC4E4dW1xcQqmA== X-Proofpoint-ORIG-GUID: -84WmIfi3KqZwx3vztmIWk7hrqoYn2oH X-Proofpoint-GUID: -84WmIfi3KqZwx3vztmIWk7hrqoYn2oH X-Authority-Analysis: v=2.4 cv=dM+rWeZb c=1 sm=1 tr=0 ts=69ba9d6d cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=QEbT8_BQrpgYwvZUqSkA:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-18_01,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180108 Content-Type: text/plain; charset="utf-8" Mahua is a derivative of Glymur SoC with the third CPU cluster disabled. Document the compatible strings for the Mahua SoC and the Compute Reference Device (CRD) board based on it. Signed-off-by: Gopikrishna Garmidi Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 34a19e664556..be104b4be7a0 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -66,6 +66,11 @@ properties: - qcom,glymur-crd - const: qcom,glymur =20 + - items: + - enum: + - qcom,mahua-crd + - const: qcom,mahua + - items: - enum: - fairphone,fp6 --=20 2.34.1 From nobody Mon Apr 6 18:24:14 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 029623D6CCD for ; Wed, 18 Mar 2026 12:41:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c0e53b5fa1sm4454521eec.10.2026.03.18.05.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 05:41:17 -0700 (PDT) From: Gopikrishna Garmidi To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sibi.sankar@oss.qualcomm.com, pankaj.patil@oss.qualcomm.com, rajendra.nayak@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, Gopikrishna Garmidi Subject: [PATCH v2 2/3] arm64: dts: qcom: Commonize Glymur CRD DTSI Date: Wed, 18 Mar 2026 05:40:59 -0700 Message-Id: <20260318124100.212992-3-gopikrishna.garmidi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260318124100.212992-1-gopikrishna.garmidi@oss.qualcomm.com> References: <20260318124100.212992-1-gopikrishna.garmidi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 9UkgEqVAOYWzK6XJ1eQYwHbvW_JZlV3o X-Proofpoint-GUID: 9UkgEqVAOYWzK6XJ1eQYwHbvW_JZlV3o X-Authority-Analysis: v=2.4 cv=U4ifzOru c=1 sm=1 tr=0 ts=69ba9d6f cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=Lx9aQ9xY3w96JebXmp4A:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDEwOCBTYWx0ZWRfXwqNiV0kYIsmN +6YMEo7YCjg/ywxxH3+N5PBpm+mTAXyVCHxhQMy7AYJa69uAohm0CA0EA0NWlRdh8OgiX4MVrNX ZRI4UJq3KhonJRhgkVuiLo+ubuaxQcxtBaYorm5tTboWpTMykKMJN6Mj4xorKuSfpuIouVnq+Sj N5gGi6AEBn0CR+P4uGB+0rvw7y0uJlgPtBC9Tx63qLBovpY3doT0DmSGaz9epUzyBIDWbQ9xYUZ TlOfZwUnQwoDu605IQ6DDkeccHE23vW+/rmYpYQiNLOY+XxGb68doikPLXoFfCI2bTt/ySWPGoU upi5+p4sH+lNpVw6YDm2DfppXV4+T/MYVuiuT4X9fCTn7hJbEafUfsnPlRlltlM2YgyUqyrUsQI WJQtBFSDN8DhNmJs+HPViKAovoYklBhyfZ1Ut9TPyShenT8faD63GrZh+QGzZ78mfvfgfsX00K5 wYNgIQBN8awMnfjND9g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-18_01,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180108 Content-Type: text/plain; charset="utf-8" Commonize the existing Glymur CRD DTSI to allow reuse with Mahua CRDs. Leave the PCIe3b nodes disabled by default, since the UEFI has the instance disabled to avoid boot delays due to link failures. Signed-off-by: Gopikrishna Garmidi Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 586 +----------------- .../qcom/{glymur-crd.dts =3D> glymur-crd.dtsi} | 7 - 2 files changed, 1 insertion(+), 592 deletions(-) copy arch/arm64/boot/dts/qcom/{glymur-crd.dts =3D> glymur-crd.dtsi} (99%) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 877945319012..0efd9e27c82f 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -6,593 +6,9 @@ /dts-v1/; =20 #include "glymur.dtsi" -#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ -#include "pmh0101.dtsi" /* SPMI0: SID-1 */ -#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ -#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ -#include "pmk8850.dtsi" /* SPMI0: SID-0 */ -#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ +#include "glymur-crd.dtsi" =20 / { model =3D "Qualcomm Technologies, Inc. Glymur CRD"; compatible =3D "qcom,glymur-crd", "qcom,glymur"; - - aliases { - serial0 =3D &uart21; - serial1 =3D &uart14; - i2c0 =3D &i2c0; - i2c1 =3D &i2c4; - i2c2 =3D &i2c5; - spi0 =3D &spi18; - }; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - clocks { - xo_board: xo-board { - compatible =3D "fixed-clock"; - clock-frequency =3D <38400000>; - #clock-cells =3D <0>; - }; - - sleep_clk: sleep-clk { - compatible =3D "fixed-clock"; - clock-frequency =3D <32000>; - #clock-cells =3D <0>; - }; - }; - - gpio-keys { - compatible =3D "gpio-keys"; - - pinctrl-0 =3D <&key_vol_up_default>; - pinctrl-names =3D "default"; - - key-volume-up { - label =3D "Volume Up"; - linux,code =3D ; - gpios =3D <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; - debounce-interval =3D <15>; - linux,can-disable; - wakeup-source; - }; - }; - - vreg_nvme: regulator-nvme { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_NVME_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&nvme_reg_en>; - pinctrl-names =3D "default"; - - regulator-boot-on; - }; - - vreg_nvmesec: regulator-nvmesec { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_NVME_SEC_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&nvme_sec_reg_en>; - pinctrl-names =3D "default"; - - regulator-boot-on; - }; - - vreg_wlan: regulator-wlan { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_WLAN_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&tlmm 94 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&wlan_reg_en>; - pinctrl-names =3D "default"; - - regulator-boot-on; - }; - - vreg_wwan: regulator-wwan { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_WWAN_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&tlmm 246 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&wwan_reg_en>; - pinctrl-names =3D "default"; - }; -}; - -&apps_rsc { - regulators-0 { - compatible =3D "qcom,pmh0101-rpmh-regulators"; - qcom,pmic-id =3D "B_E0"; - - vreg_bob1_e0: bob1 { - regulator-name =3D "vreg_bob1_e0"; - regulator-min-microvolt =3D <2200000>; - regulator-max-microvolt =3D <4224000>; - regulator-initial-mode =3D ; - }; - - vreg_bob2_e0: bob2 { - regulator-name =3D "vreg_bob2_e0"; - regulator-min-microvolt =3D <2540000>; - regulator-max-microvolt =3D <3600000>; - regulator-initial-mode =3D ; - }; - - vreg_l1b_e0_1p8: ldo1 { - regulator-name =3D "vreg_l1b_e0_1p8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vreg_l2b_e0_2p9: ldo2 { - regulator-name =3D "vreg_l2b_e0_2p9"; - regulator-min-microvolt =3D <2904000>; - regulator-max-microvolt =3D <2904000>; - regulator-initial-mode =3D ; - }; - - vreg_l7b_e0_2p79: ldo7 { - regulator-name =3D "vreg_l7b_e0_2p79"; - regulator-min-microvolt =3D <2790000>; - regulator-max-microvolt =3D <2792000>; - regulator-initial-mode =3D ; - }; - - vreg_l8b_e0_1p50: ldo8 { - regulator-name =3D "vreg_l8b_e0_1p50"; - regulator-min-microvolt =3D <1504000>; - regulator-max-microvolt =3D <1504000>; - regulator-initial-mode =3D ; - }; - - vreg_l9b_e0_2p7: ldo9 { - regulator-name =3D "vreg_l9b_e0_2p7"; - regulator-min-microvolt =3D <2704000>; - regulator-max-microvolt =3D <2704000>; - regulator-initial-mode =3D ; - }; - - vreg_l10b_e0_1p8: ldo10 { - regulator-name =3D "vreg_l10b_e0_1p8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vreg_l11b_e0_1p2: ldo11 { - regulator-name =3D "vreg_l11b_e0_1p2"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - - vreg_l12b_e0_1p14: ldo12 { - regulator-name =3D "vreg_l12b_e0_1p14"; - regulator-min-microvolt =3D <1144000>; - regulator-max-microvolt =3D <1144000>; - regulator-initial-mode =3D ; - }; - - vreg_l15b_e0_1p8: ldo15 { - regulator-name =3D "vreg_l15b_e0_1p8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vreg_l17b_e0_2p4: ldo17 { - regulator-name =3D "vreg_l17b_e0_2p4"; - regulator-min-microvolt =3D <2400000>; - regulator-max-microvolt =3D <2700000>; - regulator-initial-mode =3D ; - }; - - vreg_l18b_e0_1p2: ldo18 { - regulator-name =3D "vreg_l18b_e0_1p2"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-1 { - compatible =3D "qcom,pmcx0102-rpmh-regulators"; - qcom,pmic-id =3D "C_E1"; - - vreg_l1c_e1_0p82: ldo1 { - regulator-name =3D "vreg_l1c_e1_0p82"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l2c_e1_1p14: ldo2 { - regulator-name =3D "vreg_l2c_e1_1p14"; - regulator-min-microvolt =3D <1144000>; - regulator-max-microvolt =3D <1144000>; - regulator-initial-mode =3D ; - }; - - vreg_l3c_e1_0p89: ldo3 { - regulator-name =3D "vreg_l3c_e1_0p89"; - regulator-min-microvolt =3D <890000>; - regulator-max-microvolt =3D <980000>; - regulator-initial-mode =3D ; - }; - - vreg_l4c_e1_0p72: ldo4 { - regulator-name =3D "vreg_l4c_e1_0p72"; - regulator-min-microvolt =3D <720000>; - regulator-max-microvolt =3D <720000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-2 { - compatible =3D "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id =3D "F_E0"; - - vreg_s7f_e0_1p32: smps7 { - regulator-name =3D "vreg_s7f_e0_1p32"; - regulator-min-microvolt =3D <1320000>; - regulator-max-microvolt =3D <1352000>; - regulator-initial-mode =3D ; - }; - - vreg_s8f_e0_0p95: smps8 { - regulator-name =3D "vreg_s8f_e0_0p95"; - regulator-min-microvolt =3D <952000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - - vreg_s9f_e0_1p9: smps9 { - regulator-name =3D "vreg_s9f_e0_1p9"; - regulator-min-microvolt =3D <1900000>; - regulator-max-microvolt =3D <2000000>; - regulator-initial-mode =3D ; - }; - - vreg_l2f_e0_0p82: ldo2 { - regulator-name =3D "vreg_l2f_e0_0p82"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l3f_e0_0p72: ldo3 { - regulator-name =3D "vreg_l3f_e0_0p72"; - regulator-min-microvolt =3D <720000>; - regulator-max-microvolt =3D <720000>; - regulator-initial-mode =3D ; - }; - - vreg_l4f_e0_0p3: ldo4 { - regulator-name =3D "vreg_l4f_e0_0p3"; - regulator-min-microvolt =3D <1080000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-3 { - compatible =3D "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id =3D "F_E1"; - - vreg_s7f_e1_0p3: smps7 { - regulator-name =3D "vreg_s7f_e1_0p3"; - regulator-min-microvolt =3D <300000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - - vreg_l1f_e1_0p82: ldo1 { - regulator-name =3D "vreg_l1f_e1_0p82"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l2f_e1_0p83: ldo2 { - regulator-name =3D "vreg_l2f_e1_0p83"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l4f_e1_1p08: ldo4 { - regulator-name =3D "vreg_l4f_e1_1p08"; - regulator-min-microvolt =3D <1080000>; - regulator-max-microvolt =3D <1320000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-4 { - compatible =3D "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id =3D "H_E0"; - - vreg_l1h_e0_0p89: ldo1 { - regulator-name =3D "vreg_l1h_e0_0p89"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l2h_e0_0p72: ldo2 { - regulator-name =3D "vreg_l2h_e0_0p72"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l3h_e0_0p32: ldo3 { - regulator-name =3D "vreg_l3h_e0_0p32"; - regulator-min-microvolt =3D <320000>; - regulator-max-microvolt =3D <2000000>; - regulator-initial-mode =3D ; - }; - - vreg_l4h_e0_1p2: ldo4 { - regulator-name =3D "vreg_l4h_e0_1p2"; - regulator-min-microvolt =3D <1080000>; - regulator-max-microvolt =3D <1320000>; - regulator-initial-mode =3D ; - }; - }; -}; - -&pcie3b { - vddpe-3v3-supply =3D <&vreg_nvmesec>; - - pinctrl-0 =3D <&pcie3b_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie3b_phy { - vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; - vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; - - status =3D "okay"; -}; - -&pcie3b_port0 { - reset-gpios =3D <&tlmm 155 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 157 GPIO_ACTIVE_LOW>; -}; - -&pcie4 { - vddpe-3v3-supply =3D <&vreg_wlan>; - - pinctrl-0 =3D <&pcie4_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie4_phy { - vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; - vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; - - status =3D "okay"; -}; - -&pcie4_port0 { - reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; -}; - -&pcie5 { - vddpe-3v3-supply =3D <&vreg_nvme>; - - pinctrl-0 =3D <&pcie5_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie5_phy { - vdda-phy-supply =3D <&vreg_l2f_e0_0p82>; - vdda-pll-supply =3D <&vreg_l4h_e0_1p2>; - - status =3D "okay"; -}; - -&pcie5_port0 { - reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; -}; - -&pcie6 { - vddpe-3v3-supply =3D <&vreg_wwan>; - - pinctrl-0 =3D <&pcie6_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie6_phy { - vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; - vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; - - status =3D "okay"; -}; - -&pcie6_port0 { - reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; -}; - -&pmh0101_gpios { - nvme_reg_en: nvme-reg-en-state { - pins =3D "gpio14"; - function =3D "normal"; - bias-disable; - }; -}; - -&pmh0110_f_e1_gpios { - nvme_sec_reg_en: nvme-reg-en-state { - pins =3D "gpio14"; - function =3D "normal"; - bias-disable; - }; -}; - -&pmh0101_gpios { - key_vol_up_default: key-vol-up-default-state { - pins =3D "gpio6"; - function =3D "normal"; - output-disable; - bias-pull-up; - }; -}; - -&pmk8850_rtc { - qcom,no-alarm; -}; - -&pon_resin { - linux,code =3D ; - status =3D "okay"; -}; - -&tlmm { - gpio-reserved-ranges =3D <4 4>, /* EC TZ Secure I3C */ - <10 2>, /* OOB UART */ - <44 4>; /* Security SPI (TPM) */ - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins =3D "gpio147"; - function =3D "pcie4_clk_req_n"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio146"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio148"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - pcie5_default: pcie5-default-state { - clkreq-n-pins { - pins =3D "gpio153"; - function =3D "pcie5_clk_req_n"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio152"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio154"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - pcie6_default: pcie6-default-state { - clkreq-n-pins { - pins =3D "gpio150"; - function =3D "pcie6_clk_req_n"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio149"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio151"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - pcie3b_default: pcie3b-default-state { - clkreq-n-pins { - pins =3D "gpio156"; - function =3D "pcie3b_clk"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio155"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio157"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - wlan_reg_en: wlan-reg-en-state { - pins =3D "gpio94"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wwan_reg_en: wwan-reg-en-state { - pins =3D "gpio246"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; }; diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dtsi similarity index 99% copy from arch/arm64/boot/dts/qcom/glymur-crd.dts copy to arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 877945319012..abc6cc8bb0a8 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -3,9 +3,6 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 -/dts-v1/; - -#include "glymur.dtsi" #include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ #include "pmh0101.dtsi" /* SPMI0: SID-1 */ #include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ @@ -372,15 +369,11 @@ &pcie3b { =20 pinctrl-0 =3D <&pcie3b_default>; pinctrl-names =3D "default"; - - status =3D "okay"; }; =20 &pcie3b_phy { vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c0e53b5fa1sm4454521eec.10.2026.03.18.05.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 05:41:20 -0700 (PDT) From: Gopikrishna Garmidi To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sibi.sankar@oss.qualcomm.com, pankaj.patil@oss.qualcomm.com, rajendra.nayak@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, Gopikrishna Garmidi , Raviteja Laggyshetty , Kamal Wadhwa , Manaf Meethalavalappu Pallikunhi Subject: [PATCH v2 3/3] arm64: dts: qcom: Add Mahua SoC and CRD Date: Wed, 18 Mar 2026 05:41:00 -0700 Message-Id: <20260318124100.212992-4-gopikrishna.garmidi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260318124100.212992-1-gopikrishna.garmidi@oss.qualcomm.com> References: <20260318124100.212992-1-gopikrishna.garmidi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=bIcb4f+Z c=1 sm=1 tr=0 ts=69ba9d72 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=4nuuKY_MPYQNcC36K5wA:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: aznbPCqq7yOuALLaTJJar25rKXEr8eJy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDEwOCBTYWx0ZWRfX4y12AOPvikMP lF7Q7PEiWkvW9v4mDP3+uV/XDfu4/ooc4xynUwYa2d9a/gmhGMgUd/h0uzQNfOsplHsei5J6QMv /e8HpXHpeLw/CMKzhf3X9ZJISFnE7jp9gIXNJ8aLCSTvpQZ14VcCtplTLiAv71jKJJRFA7ZIWUE jzmJrOGImvLFaLGXLuYE0EXoWfFTBPWHP9GJIGDG5F9egWi7GscyY7e6H783+hYxv+uP7ITFxDI vsMenrrihVSEu3kksV48SxLr1BHBVrlS+Bq2nUMb1z7zdUqeqVrkOC3SBL9XbYMFFGczoPOB73k 1k7NNLKkbfGgU+1gAfdSxQTZWn2xMhPPloR05nHnnIxv6hqjMRVJrUmIow3VV0wRxW4OVUKuGIB wj2tii7i/9b+zfZpnHc5Lsdn3GsDaH5IcpP0CiBsZMDqDSCObyXUsVE4hNDsEKggFAiE/dBtpaj 6HpYXwF5hGvxwCl8aDA== X-Proofpoint-GUID: aznbPCqq7yOuALLaTJJar25rKXEr8eJy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-18_01,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180108 Content-Type: text/plain; charset="utf-8" Introduce support for the Mahua SoC and the CRD based on it. Some of the notable differences are the absent CPU cluster, interconnect, TLMM, thermal zones and adjusted PCIe west clocks. Everything else should work as-is. Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Gopikrishna Garmidi Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 ++ arch/arm64/boot/dts/qcom/mahua.dtsi | 299 +++++++++++++++++++ arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +- 6 files changed, 325 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 317af937d038..e85ff36012f1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -44,6 +44,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera.dtb lemans-evk-el2-dtbs :=3D lemans-evk.dtb lemans-el2.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index e269cec7942c..4e0b44af073e 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -282,7 +282,7 @@ core5 { }; }; =20 - cluster2 { + cpu_map_cluster2: cluster2 { core0 { cpu =3D <&cpu12>; }; diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/q= com/mahua-crd.dts new file mode 100644 index 000000000000..9c8244e892dd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "mahua.dtsi" +#include "glymur-crd.dtsi" + +/delete-node/ &pmcx0102_d_e0; +/delete-node/ &pmcx0102_d0_thermal; +/delete-node/ &pmh0104_i_e0; +/delete-node/ &pmh0104_i0_thermal; +/delete-node/ &pmh0104_j_e0; +/delete-node/ &pmh0104_j0_thermal; + +/ { + model =3D "Qualcomm Technologies, Inc. Mahua CRD"; + compatible =3D "qcom,mahua-crd", "qcom,mahua"; +}; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi new file mode 100644 index 000000000000..7aa8d26b2b3a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* Mahua is heavily based on Glymur, with some meaningful differences */ +#include "glymur.dtsi" + +/delete-node/ &cluster2_pd; +/delete-node/ &cpu_map_cluster2; +/delete-node/ &cpu12; +/delete-node/ &cpu13; +/delete-node/ &cpu14; +/delete-node/ &cpu15; +/delete-node/ &cpu16; +/delete-node/ &cpu17; +/delete-node/ &cpu_pd12; +/delete-node/ &cpu_pd13; +/delete-node/ &cpu_pd14; +/delete-node/ &cpu_pd15; +/delete-node/ &cpu_pd16; +/delete-node/ &cpu_pd17; +/delete-node/ &tsens6; +/delete-node/ &tsens7; + +&aggre1_noc { + compatible =3D "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc"; +}; + +&aggre2_noc { + compatible =3D "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc"; +}; + +&aggre3_noc { + compatible =3D "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc"; +}; + +&aggre4_noc { + compatible =3D "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc"; +}; + +&clk_virt { + compatible =3D "qcom,mahua-clk-virt", "qcom,glymur-clk-virt"; +}; + +&cnoc_main { + compatible =3D "qcom,mahua-cnoc-main", "qcom,glymur-cnoc-main"; +}; + +&config_noc { + compatible =3D "qcom,mahua-cnoc-cfg"; +}; + +&hsc_noc { + compatible =3D "qcom,mahua-hscnoc"; +}; + +&lpass_ag_noc { + compatible =3D "qcom,mahua-lpass-ag-noc", "qcom,glymur-lpass-ag-noc"; +}; + +&lpass_lpiaon_noc { + compatible =3D "qcom,mahua-lpass-lpiaon-noc", "qcom,glymur-lpass-lpiaon-n= oc"; +}; + +&lpass_lpicx_noc { + compatible =3D "qcom,mahua-lpass-lpicx-noc", "qcom,glymur-lpass-lpicx-noc= "; +}; + +&mc_virt { + compatible =3D "qcom,mahua-mc-virt"; +}; + +&mmss_noc { + compatible =3D "qcom,mahua-mmss-noc", "qcom,glymur-mmss-noc"; +}; + +&nsi_noc { + compatible =3D "qcom,mahua-nsinoc", "qcom,glymur-nsinoc"; +}; + +&nsp_noc { + compatible =3D "qcom,mahua-nsp-noc", "qcom,glymur-nsp-noc"; +}; + +&oobm_ss_noc { + compatible =3D "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; +}; + +&pcie_east_anoc { + compatible =3D "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; +}; + +&pcie_east_slv_noc { + compatible =3D "qcom,mahua-pcie-east-slv-noc", "qcom,glymur-pcie-east-slv= -noc"; +}; + +&pcie_west_anoc { + compatible =3D "qcom,mahua-pcie-west-anoc"; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; +}; + +&pcie_west_slv_noc { + compatible =3D "qcom,mahua-pcie-west-slv-noc"; +}; + +&system_noc { + compatible =3D "qcom,mahua-system-noc", "qcom,glymur-system-noc"; +}; + +&tlmm { + compatible =3D "qcom,mahua-tlmm"; +}; + +&thermal_zones { + /delete-node/ aoss-6-thermal; + /delete-node/ aoss-7-thermal; + /delete-node/ cpu-2-0-0-thermal; + /delete-node/ cpu-2-0-1-thermal; + /delete-node/ cpu-2-1-0-thermal; + /delete-node/ cpu-2-1-1-thermal; + /delete-node/ cpu-2-2-0-thermal; + /delete-node/ cpu-2-2-1-thermal; + /delete-node/ cpu-2-3-0-thermal; + /delete-node/ cpu-2-3-1-thermal; + /delete-node/ cpu-2-4-0-thermal; + /delete-node/ cpu-2-4-1-thermal; + /delete-node/ cpu-2-5-0-thermal; + /delete-node/ cpu-2-5-1-thermal; + /delete-node/ cpullc-2-0-thermal; + /delete-node/ cpuillc-2-1-thermal; + /delete-node/ ddr-2-thermal; + /delete-node/ gpu-3-0-thermal; + /delete-node/ gpu-3-1-thermal; + /delete-node/ gpu-3-2-thermal; + /delete-node/ qmx-2-0-thermal; + /delete-node/ qmx-2-1-thermal; + /delete-node/ qmx-2-2-thermal; + /delete-node/ qmx-2-3-thermal; + /delete-node/ qmx-2-4-thermal; + /delete-node/ video-1-thermal; + + ddr-1-thermal { + thermal-sensors =3D <&tsens1 7>; + }; + + video-0-thermal { + thermal-sensors =3D <&tsens1 8>; + }; + + nsphvx-0-thermal { + thermal-sensors =3D <&tsens4 1>; + }; + + nsphvx-1-thermal { + thermal-sensors =3D <&tsens4 2>; + }; + + nsphvx-2-thermal { + thermal-sensors =3D <&tsens4 3>; + }; + + nsphvx-3-thermal { + thermal-sensors =3D <&tsens4 4>; + }; + + nsphmx-0-thermal { + thermal-sensors =3D <&tsens4 5>; + }; + + nsphmx-1-thermal { + thermal-sensors =3D <&tsens4 6>; + }; + + nsphmx-2-thermal { + thermal-sensors =3D <&tsens4 7>; + }; + + nsphmx-3-thermal { + thermal-sensors =3D <&tsens4 8>; + }; + + camera-0-thermal { + thermal-sensors =3D <&tsens4 9>; + }; + + camera-1-thermal { + thermal-sensors =3D <&tsens4 10>; + }; + + gpu-0-0-thermal { + thermal-sensors =3D <&tsens5 1>; + }; + + gpu-0-1-thermal { + thermal-sensors =3D <&tsens5 2>; + }; + + gpu-0-2-thermal { + thermal-sensors =3D <&tsens5 3>; + }; + + gpu-1-0-thermal { + thermal-sensors =3D <&tsens5 4>; + }; + + gpu-1-1-thermal { + thermal-sensors =3D <&tsens5 5>; + }; + + gpu-1-2-thermal { + thermal-sensors =3D <&tsens5 6>; + }; + + gpu-2-0-thermal { + thermal-sensors =3D <&tsens5 7>; + }; + + gpu-2-1-thermal { + thermal-sensors =3D <&tsens5 8>; + }; + + gpu-2-2-thermal { + thermal-sensors =3D <&tsens5 9>; + }; + + gpuss-0-thermal { + thermal-sensors =3D <&tsens5 10>; + }; + + gpuss-1-thermal { + thermal-sensors =3D <&tsens5 11>; + }; + + gpuss-2-thermal { + thermal-sensors =3D <&tsens5 12>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-3-thermal { + thermal-sensors =3D <&tsens5 13>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-4-thermal { + thermal-sensors =3D <&tsens5 14>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; +}; + +&tsens4 { + #qcom,sensors =3D <11>; +}; + +&tsens5 { + #qcom,sensors =3D <15>; +}; + diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/q= com/pmcx0102.dtsi index c3ccd2b75609..db2da9ef4f01 100644 --- a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi +++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi @@ -46,7 +46,7 @@ trip1 { }; }; =20 - pmcx0102-d0-thermal { + pmcx0102_d0_thermal: pmcx0102-d0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmcx0102_d_e0_temp_alarm>; =20 diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot= /dts/qcom/pmh0104-glymur.dtsi index d89cceda53a3..7a1e5f355c17 100644 --- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -8,7 +8,7 @@ =20 /{ thermal_zones { - pmh0104-i0-thermal { + pmh0104_i0_thermal: pmh0104-i0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmh0104_i_e0_temp_alarm>; =20 @@ -27,7 +27,7 @@ trip1 { }; }; =20 - pmh0104-j0-thermal { + pmh0104_j0_thermal: pmh0104-j0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmh0104_j_e0_temp_alarm>; =20 --=20 2.34.1