From nobody Mon Apr 6 18:29:07 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD41139EF02 for ; Wed, 18 Mar 2026 10:51:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831099; cv=none; b=ElyX2W6e2KWPEcJE09n/Grt3r2OStDoqrCzwP4CnBwJQv1ZHR9jGxhUuwDSxheqwY2Ux95gOg4cOtMoK+fOcapxjaT3mjy4oB6PNJ6p/gNH7uDHUcYyytY+ECGl7oI/93nZHtX3ioMSeClYWyoHdIXsD+CMyn9MLzDOOuCjr/JI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831099; c=relaxed/simple; bh=fY7ASz0zWeUR8O66cYDJopAwvXuoXz2od4ZmbubNWsE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OcgSXuujBhAVL+7Fitd4f3QguGXCD53kOj2C8JE9aoXnDGVqOypqlU+QoXc8VXvID+DGOKrpfGwVtdthmIbBZe0TqV2mGuBwnmbsX4RXYCSoLIcXxlWitYo8v5cGiFmnVpm13bH54KRkIMIdFJxMQ8IF6syAKa3mCrjoOMz3Cn0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1w2oUn-0001WJ-F0; Wed, 18 Mar 2026 11:51:25 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac] helo=dude04) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1w2oUn-000tSN-00; Wed, 18 Mar 2026 11:51:25 +0100 Received: from ore by dude04 with local (Exim 4.98.2) (envelope-from ) id 1w2oUm-00000003RII-3uSv; Wed, 18 Mar 2026 11:51:24 +0100 From: Oleksij Rempel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue Cc: David Jander , stable@vger.kernel.org, Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v1 1/7] ARM: dts: stm32: stm32mp15x-mecio1-io: Enable internal ADC reference Date: Wed, 18 Mar 2026 11:51:17 +0100 Message-ID: <20260318105123.819807-2-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260318105123.819807-1-o.rempel@pengutronix.de> References: <20260318105123.819807-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: David Jander Switch the ADC reference supply from the general 3.3V rail to the internal 2.5V VREFBUF regulator. The ADC circuits on this board are designed for the internal 2.5V reference. Without this change, all ADC measurement values are incorrect. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants= ") Cc: Signed-off-by: David Jander Co-developed-by: Oleksij Rempel Signed-off-by: Oleksij Rempel --- arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot= /dts/st/stm32mp15x-mecio1-io.dtsi index 915ba2526f45..1ce01bac9814 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -95,7 +95,7 @@ &adc { pinctrl-names =3D "default"; vdd-supply =3D <&v3v3>; vdda-supply =3D <&v3v3>; - vref-supply =3D <&v3v3>; + vref-supply =3D <&vrefbuf>; status =3D "okay"; }; =20 @@ -412,6 +412,13 @@ &usbphyc_port1 { phy-supply =3D <&v3v3>; }; =20 +&vrefbuf { + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + vdda-supply =3D <&v3v3>; + status =3D "okay"; +}; + &pinctrl { adc12_pins_mecsbc: adc12-ain-mecsbc-0 { pins { --=20 2.47.3 From nobody Mon Apr 6 18:29:07 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A76FE3806C7 for ; Wed, 18 Mar 2026 10:51:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831096; cv=none; b=hYnTEUeynkvlx5fMhA9vDKhvG5Za5Gst6cZ1j/WAhHTQgdZltsUCzROl9XiENtcvPGJgzHYv64q6R1SH8HmYK89NngBS5zgVMgKRt2etAxg7mNWJPa3D+98qAWuXzZwhMWxNrccOtaIyRva0IJ2vwxO5lGfNNDR0p2HDo0aMAnA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831096; c=relaxed/simple; bh=thnm6PEYhA6tWFCd44xDPHzccXm1OIwwLMjKMACRj+0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qrJayRUTfzXb/d9cgANQ6TI3HOP+vuO6ZAghY28uyp+zAIdoeaOK77FZFJNiTKvuRqocIUxlMdRWyqHDe1SMl1kf14P7i+lDjVO6ZUW9QdAxzmWauDIWESK6bjL51BR8nyAqeUfMzXtm9uQnycfbZlp79pG9igyDWA8fg3vW1Hk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1w2oUn-0001WK-F0; Wed, 18 Mar 2026 11:51:25 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac] helo=dude04) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1w2oUn-000tSO-06; Wed, 18 Mar 2026 11:51:25 +0100 Received: from ore by dude04 with local (Exim 4.98.2) (envelope-from ) id 1w2oUm-00000003RIS-41UW; Wed, 18 Mar 2026 11:51:24 +0100 From: Oleksij Rempel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue Cc: David Jander , stable@vger.kernel.org, Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v1 2/7] ARM: dts: stm32: stm32mp15x-mecio1-io: Fix ADC sampling times Date: Wed, 18 Mar 2026 11:51:18 +0100 Message-ID: <20260318105123.819807-3-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260318105123.819807-1-o.rempel@pengutronix.de> References: <20260318105123.819807-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: David Jander Increase the minimum ADC sample times for all configured channels on ADC1 and ADC2 to ensure measurement accuracy meets specifications. The default 5us sample time is insufficient for the internal sampling capacitor to fully charge. Increase the default time to 20us to relax the input impedance requirements. Additionally, the phint0_ain and phint1_ain channels require a much longer sampling period due to their specific circuit design. Increase their sample times to 200us. Remove stale comments regarding clock cycles that no longer match the updated timings. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants= ") Cc: Signed-off-by: David Jander Co-developed-by: Oleksij Rempel Signed-off-by: Oleksij Rempel --- .../arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 32 +++++++++---------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot= /dts/st/stm32mp15x-mecio1-io.dtsi index 1ce01bac9814..1b1299770ca0 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -104,80 +104,79 @@ &adc1 { =20 channel@0 { reg =3D <0>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "p24v_stp"; }; =20 channel@1 { reg =3D <1>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "p24v_hpdcm"; }; =20 channel@2 { reg =3D <2>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "ain0"; }; =20 channel@3 { reg =3D <3>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "hpdcm1_i2"; }; =20 channel@5 { reg =3D <5>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "hpout1_i"; }; =20 channel@6 { reg =3D <6>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "ain1"; }; =20 channel@9 { reg =3D <9>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "hpout0_i"; }; =20 channel@10 { reg =3D <10>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <200000>; label =3D "phint0_ain"; }; =20 channel@13 { reg =3D <13>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <200000>; label =3D "phint1_ain"; }; =20 channel@15 { reg =3D <15>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "hpdcm0_i1"; }; =20 channel@16 { reg =3D <16>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "lsin"; }; =20 channel@18 { reg =3D <18>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "hpdcm0_i2"; }; =20 channel@19 { reg =3D <19>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "hpdcm1_i1"; }; }; @@ -187,14 +186,13 @@ &adc2 { =20 channel@2 { reg =3D <2>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "ain2"; }; =20 channel@6 { reg =3D <6>; - st,min-sample-time-ns =3D <5000>; + st,min-sample-time-ns =3D <20000>; label =3D "ain3"; }; }; --=20 2.47.3 From nobody Mon Apr 6 18:29:07 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 297C8391851 for ; Wed, 18 Mar 2026 10:51:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1w2oUn-0001WM-F3; Wed, 18 Mar 2026 11:51:25 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac] helo=dude04) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1w2oUn-000tSP-0E; Wed, 18 Mar 2026 11:51:25 +0100 Received: from ore by dude04 with local (Exim 4.98.2) (envelope-from ) id 1w2oUm-00000003RIc-47vz; Wed, 18 Mar 2026 11:51:24 +0100 From: Oleksij Rempel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue Cc: David Jander , stable@vger.kernel.org, Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v1 3/7] ARM: dts: stm32: stm32mp15x-mecio1-io: Move divergent mecio1 ADC channels to board files Date: Wed, 18 Mar 2026 11:51:19 +0100 Message-ID: <20260318105123.819807-4-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260318105123.819807-1-o.rempel@pengutronix.de> References: <20260318105123.819807-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: David Jander Move the divergent adc1 channel definitions out of the common mecio1-io.dtsi file and into the specific Revision 0 and Revision 1 board files. The original common file contained incorrect schematic labels for the Revision 0 hardware (e.g., labeling ana0 as p24v_hpdcm instead of ain_aux0) and failed to account for physical signal routing changes between the board revisions. Retain only the strictly shared channels in the common include file. Map the correct channels and schematic labels directly within stm32mp151c-mecio1r0.dts and stm32mp153c-mecio1r1.dts. Crucially, ensure that the required 200us sample time follows the phint1_ain signal to its new physical location on channel 3 for the Revision 1 hardware. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants= ") Cc: Signed-off-by: David Jander Co-developed-by: Oleksij Rempel Signed-off-by: Oleksij Rempel --- arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts | 50 +++++++++++++++++++ arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts | 50 +++++++++++++++++++ .../arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 50 +------------------ 3 files changed, 101 insertions(+), 49 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts b/arch/arm/boot/= dts/st/stm32mp151c-mecio1r0.dts index a5ea1431c399..4e795ad42928 100644 --- a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts +++ b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts @@ -36,6 +36,56 @@ led-1 { }; }; =20 +&adc1 { + channel@0 { + reg =3D <0>; + st,min-sample-time-ns =3D <20000>; + label =3D "ain_aux0"; + }; + + channel@1 { + reg =3D <1>; + st,min-sample-time-ns =3D <20000>; + label =3D "ain_aux1"; + }; + + channel@3 { + reg =3D <3>; + st,min-sample-time-ns =3D <20000>; + label =3D "hpdcm1_i2"; + }; + + channel@5 { + reg =3D <5>; + st,min-sample-time-ns =3D <20000>; + label =3D "pout1_i"; + }; + + channel@9 { + reg =3D <9>; + st,min-sample-time-ns =3D <20000>; + label =3D "pout0_i"; + }; + + channel@13 { + reg =3D <13>; + st,min-sample-time-ns =3D <200000>; + label =3D "phint1_ain"; + }; + + channel@15 { + reg =3D <15>; + st,min-sample-time-ns =3D <20000>; + label =3D "hpdcm0_i1"; + }; + + channel@18 { + reg =3D <18>; + st,min-sample-time-ns =3D <20000>; + label =3D "hpdcm0_i2"; + }; +}; + &clk_hse { clock-frequency =3D <25000000>; }; diff --git a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts b/arch/arm/boot/= dts/st/stm32mp153c-mecio1r1.dts index 16b814c19350..d32816093e47 100644 --- a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts +++ b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts @@ -36,6 +36,56 @@ led-1 { }; }; =20 +&adc1 { + channel@0 { + reg =3D <0>; + st,min-sample-time-ns =3D <20000>; + label =3D "p24v_hpdcm"; + }; + + channel@1 { + reg =3D <1>; + st,min-sample-time-ns =3D <20000>; + label =3D "p24v_stp"; + }; + + channel@3 { + reg =3D <3>; + st,min-sample-time-ns =3D <200000>; + label =3D "phint1_ain"; + }; + + channel@5 { + reg =3D <5>; + st,min-sample-time-ns =3D <20000>; + label =3D "hpout1_i"; + }; + + channel@9 { + reg =3D <9>; + st,min-sample-time-ns =3D <20000>; + label =3D "hpout0_i"; + }; + + channel@13 { + reg =3D <13>; + st,min-sample-time-ns =3D <20000>; + label =3D "hpdcm0_i2"; + }; + + channel@15 { + reg =3D <15>; + st,min-sample-time-ns =3D <20000>; + label =3D "hpdcm1_i2"; + }; + + channel@18 { + reg =3D <18>; + st,min-sample-time-ns =3D <20000>; + label =3D "hpdcm0_i1"; + }; +}; + &clk_hse { clock-frequency =3D <24000000>; }; diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot= /dts/st/stm32mp15x-mecio1-io.dtsi index 1b1299770ca0..f91b3d1f037b 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -90,7 +90,7 @@ v5v: regulator-v5v { }; =20 &adc { - /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ + /* ANA0, ANA1 are dedicated pins and don't need pinctrl. */ pinctrl-0 =3D <&adc12_pins_mecsbc>; pinctrl-names =3D "default"; vdd-supply =3D <&v3v3>; @@ -102,78 +102,30 @@ &adc { &adc1 { status =3D "okay"; =20 - channel@0 { - reg =3D <0>; - st,min-sample-time-ns =3D <20000>; - label =3D "p24v_stp"; - }; - - channel@1 { - reg =3D <1>; - st,min-sample-time-ns =3D <20000>; - label =3D "p24v_hpdcm"; - }; - channel@2 { reg =3D <2>; st,min-sample-time-ns =3D <20000>; label =3D "ain0"; }; =20 - channel@3 { - reg =3D <3>; - st,min-sample-time-ns =3D <20000>; - label =3D "hpdcm1_i2"; - }; - - channel@5 { - reg =3D <5>; - st,min-sample-time-ns =3D <20000>; - label =3D "hpout1_i"; - }; - channel@6 { reg =3D <6>; st,min-sample-time-ns =3D <20000>; label =3D "ain1"; }; =20 - channel@9 { - reg =3D <9>; - st,min-sample-time-ns =3D <20000>; - label =3D "hpout0_i"; - }; - channel@10 { reg =3D <10>; st,min-sample-time-ns =3D <200000>; label =3D "phint0_ain"; }; =20 - channel@13 { - reg =3D <13>; - st,min-sample-time-ns =3D <200000>; - label =3D "phint1_ain"; - }; - - channel@15 { - reg =3D <15>; - st,min-sample-time-ns =3D <20000>; - label =3D "hpdcm0_i1"; - }; - channel@16 { reg =3D <16>; st,min-sample-time-ns =3D <20000>; label =3D "lsin"; }; =20 - channel@18 { - reg =3D <18>; - st,min-sample-time-ns =3D <20000>; - label =3D "hpdcm0_i2"; - }; - channel@19 { reg =3D <19>; st,min-sample-time-ns =3D <20000>; --=20 2.47.3 From nobody Mon Apr 6 18:29:07 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 402C039281B for ; Wed, 18 Mar 2026 10:51:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831096; 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Wed, 18 Mar 2026 11:51:25 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac] helo=dude04) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1w2oUn-000tSR-0H; Wed, 18 Mar 2026 11:51:25 +0100 Received: from ore by dude04 with local (Exim 4.98.2) (envelope-from ) id 1w2oUn-00000003RIm-01bL; Wed, 18 Mar 2026 11:51:25 +0100 From: Oleksij Rempel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue Cc: David Jander , stable@vger.kernel.org, Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v1 4/7] ARM: dts: stm32: stm32mp15x-mecio1-io: Fix GPIO names typo Date: Wed, 18 Mar 2026 11:51:20 +0100 Message-ID: <20260318105123.819807-5-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260318105123.819807-1-o.rempel@pengutronix.de> References: <20260318105123.819807-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: David Jander The reset pins for the LPOUT lines were incorrectly prefixed with "GPOUT" instead of "LPOUT" in the gpio-line-names array. Fix these typos so the pin names consistently match the LPOUT0-4 signals they belong to. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants= ") Cc: Signed-off-by: David Jander Co-developed-by: Oleksij Rempel Signed-off-by: Oleksij Rempel --- arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot= /dts/st/stm32mp15x-mecio1-io.dtsi index f91b3d1f037b..e50e9ae085e8 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -185,14 +185,14 @@ &gpiod { &gpioe { gpio-line-names =3D "HPOUT0_RESETN", "HPOUT1", "HPOUT1_ALERTN", "", "", "", "HPOUT1_RESETN", - "LPOUT0", "LPOUT0_ALERTN", "GPOUT0_RESETN", - "LPOUT1", "LPOUT1_ALERTN", "GPOUT1_RESETN", - "LPOUT2", "LPOUT2_ALERTN", "GPOUT2_RESETN"; + "LPOUT0", "LPOUT0_ALERTN", "LPOUT0_RESETN", + "LPOUT1", "LPOUT1_ALERTN", "LPOUT1_RESETN", + "LPOUT2", "LPOUT2_ALERTN", "LPOUT2_RESETN"; }; =20 &gpiof { - gpio-line-names =3D "LPOUT3", "LPOUT3_ALERTN", "GPOUT3_RESETN", - "LPOUT4", "LPOUT4_ALERTN", "GPOUT4_RESETN", + gpio-line-names =3D "LPOUT3", "LPOUT3_ALERTN", "LPOUT3_RESETN", + "LPOUT4", "LPOUT4_ALERTN", "LPOUT4_RESETN", "", "", "", "", "", "", "", "", "", ""; --=20 2.47.3 From nobody Mon Apr 6 18:29:07 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D6973976BF for ; Wed, 18 Mar 2026 10:51:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831098; cv=none; b=fd1s/qQ3px7pK+nJQQV0P+go2DX/Kgraf0fLUkLPnn3uUQbdUyKaMjfP+RqcxhP8dmSmeIZoV+J/4tGcJeR/1bS/OjL6m3PJ72tbLFhR8uYBkCyt4ne3pLYC4LTTOnPjwkuqQ07DLdz/hS789+Wn4P4ihoc1tE87gHsbBOhYCf0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831098; c=relaxed/simple; bh=sXHeTCFrpD90P88yW7lbek8HGJ62ZnhzE1iwIXxHDi4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Oo9o97c0ER3x2PaNzljKPATiT2QgYpve5bkTMiJOwJx8G/Ia4s0vi8OfMWJGk/WYNmfVLhoxtGoPIpXRbVO9KQpcu01bATDe5BLhU70sgW4Y2fuho/3ujkqwfQvnYv5GmnVf1i2gDXimDau0EHrreF28wfzB3CSZJOKEH/28soY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1w2oUn-0001WN-F1; Wed, 18 Mar 2026 11:51:25 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac] helo=dude04) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1w2oUn-000tSU-0P; Wed, 18 Mar 2026 11:51:25 +0100 Received: from ore by dude04 with local (Exim 4.98.2) (envelope-from ) id 1w2oUn-00000003RIw-07Gb; Wed, 18 Mar 2026 11:51:25 +0100 From: Oleksij Rempel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue Cc: David Jander , stable@vger.kernel.org, Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v1 5/7] ARM: dts: stm32: stm32mp15x-mecio1-io: Move gpio-line-names to board files Date: Wed, 18 Mar 2026 11:51:21 +0100 Message-ID: <20260318105123.819807-6-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260318105123.819807-1-o.rempel@pengutronix.de> References: <20260318105123.819807-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: David Jander Move the gpio-line-names properties out of the common mecio1-io.dtsi file and into the specific board dts files. The pinout originally defined in the common include file belonged to the mecio1r0 (Revision 0) hardware. This is moved 1:1 into the stm32mp151c-mecio1r0.dts file without any modifications. A large number of GPIO pins are swapped on the mecio1r1 (Revision 1) hardware, so a new, board-specific gpio-line-names mapping is added to stm32mp153c-mecio1r1.dts to reflect those hardware changes. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants= ") Cc: Signed-off-by: David Jander Co-developed-by: Oleksij Rempel Signed-off-by: Oleksij Rempel --- arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts | 64 +++++++++++++++ arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts | 80 +++++++++++++++++++ .../arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 63 --------------- 3 files changed, 144 insertions(+), 63 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts b/arch/arm/boot/= dts/st/stm32mp151c-mecio1r0.dts index 4e795ad42928..06ab77465816 100644 --- a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts +++ b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts @@ -96,3 +96,67 @@ ðernet0 { assigned-clock-rates =3D <125000000>; /* Clock PLL3 to 625Mhz in tf-a. */ st,eth-clk-sel; }; + +&gpiod { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "", "", "", "", + "STP_RESETN", "STP_ENABLEN", "HPOUT0", "HPOUT0_ALERTN"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog_d_mecsbc>; +}; + +&gpioe { + gpio-line-names =3D "HPOUT0_RESETN", "HPOUT1", "HPOUT1_ALERTN", "", + "", "", "HPOUT1_RESETN", + "LPOUT0", "LPOUT0_ALERTN", "LPOUT0_RESETN", + "LPOUT1", "LPOUT1_ALERTN", "LPOUT1_RESETN", + "LPOUT2", "LPOUT2_ALERTN", "LPOUT2_RESETN"; +}; + +&gpiof { + gpio-line-names =3D "LPOUT3", "LPOUT3_ALERTN", "LPOUT3_RESETN", + "LPOUT4", "LPOUT4_ALERTN", "LPOUT4_RESETN", + "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names =3D "LPOUT5", "LPOUT5_ALERTN", "", "LPOUT5_RESETN", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpioh { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "GPIO0_RESETN", "", "", "", + "", "", "", ""; +}; + +&gpioi { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "HPDCM0_SLEEPN", "HPDCM1_SLEEPN", "GPIO1_RESETN", "", + "", "", "", ""; +}; + +&gpioj { + gpio-line-names =3D "HSIN10", "HSIN11", "HSIN12", "HSIN13", + "HSIN14", "HSIN15", "", "", + "", "", "", "", + "", "RTD_RESETN", "", ""; +}; + +&gpiok { + gpio-line-names =3D "", "", "HSIN0", "HSIN1", + "HSIN2", "HSIN3", "HSIN4", "HSIN5"; +}; + +&gpioz { + gpio-line-names =3D "", "", "", "HSIN6", + "HSIN7", "HSIN8", "HSIN9", ""; +}; + diff --git a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts b/arch/arm/boot/= dts/st/stm32mp153c-mecio1r1.dts index d32816093e47..2b3989303cd1 100644 --- a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts +++ b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts @@ -90,6 +90,86 @@ &clk_hse { clock-frequency =3D <24000000>; }; =20 +&gpioa { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "", "", "GPIO1_RESETN", "", + "", "", "", "LPOUT5"; +}; + +&gpiob { + gpio-line-names =3D "", "", "", "", + "LPOUT4_RESETN", "", "", "", + "", "LPOUT4_ALERTN", "", "", + "", "", "", ""; +}; + +&gpioc { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "", "LPOUT4", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names =3D "LPOUT2", "", "LPOUT3_RESETN", "", + "LPOUT2_ALERTN", "", "MECIO_ADDR0", "", + "HPOUT1_ALERTN", "HPOUT1_RESETN", "", "", + "", "", "HPOUT0", "HPOUT1"; +}; + +&gpioe { + gpio-line-names =3D "LPOUT0_RESETN", "", "", "", + "", "LPOUT3", "LPOUT5_ALERTN", "", + "", "", "", "", + "", "", "", "HSIN_RESETN"; +}; + +&gpiof { + gpio-line-names =3D "LPOUT5_RESETN", "", "", "HPOUT0_ALERTN", + "", "LPOUT1", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names =3D "", "", "", "HPOUT0_RESETN", + "", "", "LPOUT3_ALERTN", "", + "", "", "GPIO0_RESETN", "", + "", "", "", "LPOUT2_RESETN"; +}; + +&gpioh { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "", "LPOUT0", "", "", + "", "LPOUT0_ALERTN", "STP_ENABLEN", "STP_RESETN"; +}; + +&gpioi { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "", "", "SPE_RESETN", "", + "HPDCM0_SLEEPN", "", "", ""; +}; + +&gpioj { + gpio-line-names =3D "", "", "", "", + "", "", "", "MECIO_ADDR1", + "", "", "", "", + "", "", "", "LPOUT1_RESETN"; +}; + +&gpiok { + gpio-line-names =3D "", "", "RTD_RESETN", "", + "", "LPOUT1_ALERTN", "", ""; +}; + +&gpioz { + gpio-line-names =3D "", "", "", "", + "HPDCM1_SLEEPN", "", "", ""; +}; + &m_can1 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&m_can1_pins_b>; diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot= /dts/st/stm32mp15x-mecio1-io.dtsi index e50e9ae085e8..69a502ec36d4 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -173,69 +173,6 @@ phy0: ethernet-phy@8 { }; }; =20 -&gpiod { - gpio-line-names =3D "", "", "", "", - "", "", "", "", - "", "", "", "", - "STP_RESETN", "STP_ENABLEN", "HPOUT0", "HPOUT0_ALERTN"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_hog_d_mecsbc>; -}; - -&gpioe { - gpio-line-names =3D "HPOUT0_RESETN", "HPOUT1", "HPOUT1_ALERTN", "", - "", "", "HPOUT1_RESETN", - "LPOUT0", "LPOUT0_ALERTN", "LPOUT0_RESETN", - "LPOUT1", "LPOUT1_ALERTN", "LPOUT1_RESETN", - "LPOUT2", "LPOUT2_ALERTN", "LPOUT2_RESETN"; -}; - -&gpiof { - gpio-line-names =3D "LPOUT3", "LPOUT3_ALERTN", "LPOUT3_RESETN", - "LPOUT4", "LPOUT4_ALERTN", "LPOUT4_RESETN", - "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiog { - gpio-line-names =3D "LPOUT5", "LPOUT5_ALERTN", "", "LPOUT5_RESETN", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpioh { - gpio-line-names =3D "", "", "", "", - "", "", "", "", - "GPIO0_RESETN", "", "", "", - "", "", "", ""; -}; - -&gpioi { - gpio-line-names =3D "", "", "", "", - "", "", "", "", - "HPDCM0_SLEEPN", "HPDCM1_SLEEPN", "GPIO1_RESETN", "", - "", "", "", ""; -}; - -&gpioj { - gpio-line-names =3D "HSIN10", "HSIN11", "HSIN12", "HSIN13", - "HSIN14", "HSIN15", "", "", - "", "", "", "", - "", "RTD_RESETN", "", ""; -}; - -&gpiok { - gpio-line-names =3D "", "", "HSIN0", "HSIN1", - "HSIN2", "HSIN3", "HSIN4", "HSIN5"; -}; - -&gpioz { - gpio-line-names =3D "", "", "", "HSIN6", - "HSIN7", "HSIN8", "HSIN9", ""; -}; - &i2c2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c2_pins_a>; --=20 2.47.3 From nobody Mon Apr 6 18:29:07 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECB42381B09 for ; Wed, 18 Mar 2026 10:51:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831096; cv=none; b=BniLvgkvjY4IRRPJMulku3R49Znd4dtU5VMKY3JbrtDu/xMcUi2MC1Ggw4Pl3q4N7ESlE5f8FFsLwclnFk/fqDkkh8gVsYa+YoSJnBFpMbSzHcJVYS5Y1AhZQaWu9L2P906f92vKeohCutSUh1VfWzsE8cTd8Hb+DnrQR0W3mNo= ARC-Message-Signature: i=1; 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SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: David Jander Fix a copy-paste error in the GPIO line names for the TCA6416 expander (gpio@20). The common mecio1-io include file was originally defined using the mecio1r1 (Revision 1) hardware layout, but incorrectly labeled pin 13 as "HSIN9_BIAS" instead of the actual "HSIN7_BIAS" present in the schematics. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants= ") Cc: stable@vger.kernel.org Signed-off-by: David Jander Co-developed-by: Oleksij Rempel Signed-off-by: Oleksij Rempel --- arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot= /dts/st/stm32mp15x-mecio1-io.dtsi index 69a502ec36d4..1808289f8193 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -186,7 +186,7 @@ gpio0: gpio@20 { #gpio-cells =3D <2>; gpio-line-names =3D "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIA= S", "", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL", - "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN9_BIAS", + "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS", "", "", "", ""; }; =20 --=20 2.47.3 From nobody Mon Apr 6 18:29:07 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 236AC395D85 for ; Wed, 18 Mar 2026 10:51:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831097; cv=none; b=oXiu/LEUcvE4ZenyaRj4hv9T3CpwSyqgWOirYwG0U0Vh76s7ch/sgwottt4RxrNml2BXHQMsvZX/+cDigdQxE43lvevHVg4NmWfnev3ZT9fZaAtAJJwnP30Qi4F1EvmFBFnVhvO2p+rtINZXxbhaUYvIY/5V8FfrpLw/tcwmEMM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831097; c=relaxed/simple; bh=UE8DLg0OmVNUS8QhDZnhmGITW1Sio+cYfmRHHPQL4sM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tmJSkKwXGwcvYIU1rbo96/J/YPga2y4pL8eA8m08VjGjND0JsDc4zchgcIriM2Fuytj+bFe3hh2Ehik544+gbFDhnvZhz1rMccD/vD3u/vexBV3W0m1hhKuue0bBkxeRpagDjflQP+wtYdqRae25hvVao2QnvBr+3uQXtEaHID8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1w2oUn-0001WP-Ey; Wed, 18 Mar 2026 11:51:25 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac] helo=dude04) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1w2oUn-000tSY-0X; Wed, 18 Mar 2026 11:51:25 +0100 Received: from ore by dude04 with local (Exim 4.98.2) (envelope-from ) id 1w2oUn-00000003RJI-0IbV; Wed, 18 Mar 2026 11:51:25 +0100 From: Oleksij Rempel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue Cc: David Jander , stable@vger.kernel.org, Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v1 7/7] ARM: dts: stm32: stm32mp15x-mecio1-io: Move expander gpio-line-names to board files Date: Wed, 18 Mar 2026 11:51:23 +0100 Message-ID: <20260318105123.819807-8-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260318105123.819807-1-o.rempel@pengutronix.de> References: <20260318105123.819807-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: David Jander Move the gpio-line-names properties for the I2C GPIO expanders (gpio0 and gpio1) out of the common mecio1-io.dtsi file and into the specific board dts files. The layout originally defined in the common include file belonged to the mecio1r1 (Revision 1) hardware. This layout is moved 1:1 into the stm32mp153c-mecio1r1.dts file. The mecio1r0 (Revision 0) hardware utilizes a completely different pinout for these expanders. A new, accurate mapping reflecting the Revision 0 schematics is added to stm32mp151c-mecio1r0.dts. Fixes: 8267753c891c ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants= ") Cc: stable@vger.kernel.org Signed-off-by: David Jander Co-developed-by: Oleksij Rempel Signed-off-by: Oleksij Rempel --- arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts | 14 ++++++++++++++ arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts | 14 ++++++++++++++ arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 8 -------- 3 files changed, 28 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts b/arch/arm/boot/= dts/st/stm32mp151c-mecio1r0.dts index 06ab77465816..862782d20d10 100644 --- a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts +++ b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts @@ -97,6 +97,20 @@ ðernet0 { st,eth-clk-sel; }; =20 +&gpio0 { + gpio-line-names =3D "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS= ", + "HSIN4_BIAS", "", "STP_VREF0_LVL", "HSIN_VREF0_LVL", + "STP0_FB_BIAS", "STP1_FB_BIAS", "STP2_FB_BIAS", "STP3_FB_BIAS", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names =3D "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS", "HSIN8_BIAS= ", + "HSIN9_BIAS", "", "STP_VREF1_LVL", "HSIN_VREF1_LVL", + "STP4_FB_BIAS", "STP5_FB_BIAS", "STP6_FB_BIAS", "", + "", "", "LSIN8_BIAS", "LSIN9_BIAS"; +}; + &gpiod { gpio-line-names =3D "", "", "", "", "", "", "", "", diff --git a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts b/arch/arm/boot/= dts/st/stm32mp153c-mecio1r1.dts index 2b3989303cd1..739cc18c3d3a 100644 --- a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts +++ b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts @@ -90,6 +90,20 @@ &clk_hse { clock-frequency =3D <24000000>; }; =20 +&gpio0 { + gpio-line-names =3D "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS= ", + "", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL", + "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names =3D "HSIN8_BIAS", "HSIN9_BIAS", "HSIN10_BIAS", "HSIN11_BI= AS", + "", "", "HSIN_VREF2_LVL", "HSIN_VREF3_LVL", + "HSIN12_BIAS", "HSIN13_BIAS", "HSIN14_BIAS", "HSIN15_BIAS", + "", "", "LSIN8_BIAS", "LSIN9_BIAS"; +}; + &gpioa { gpio-line-names =3D "", "", "", "", "", "", "", "", diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot= /dts/st/stm32mp15x-mecio1-io.dtsi index 1808289f8193..1a4f5a523eb3 100644 --- a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -184,10 +184,6 @@ gpio0: gpio@20 { reg =3D <0x20>; gpio-controller; #gpio-cells =3D <2>; - gpio-line-names =3D "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIA= S", - "", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL", - "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS", - "", "", "", ""; }; =20 gpio1: gpio@21 { @@ -195,10 +191,6 @@ gpio1: gpio@21 { reg =3D <0x21>; gpio-controller; #gpio-cells =3D <2>; - gpio-line-names =3D "HSIN8_BIAS", "HSIN9_BIAS", "HSIN10_BIAS", "HSIN11_B= IAS", - "", "", "HSIN_VREF2_LVL", "HSIN_VREF3_LVL", - "HSIN12_BIAS", "HSIN13_BIAS", "HSIN14_BIAS", "HSIN15_BIAS", - "", "", "LSIN8_BIAS", "LSIN9_BIAS"; }; }; =20 --=20 2.47.3