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Wed, 18 Mar 2026 01:42:00 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v5 6/9] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC Date: Wed, 18 Mar 2026 08:41:41 +0000 Message-ID: <20260318084151.122674-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260318084151.122674-1-biju.das.jz@bp.renesas.com> References: <20260318084151.122674-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add the initial DTSI for the RZ/G3L SoC. The files in this commit have the following meaning: - r9a08g046.dtsi: RZ/G3L family SoC common parts - r9a08g046l48.dtsi: RZ/G3L R9A08G046L48 SoC-specific parts Add placeholders to reuse the code for the Renesas SMARC II carrier board. Signed-off-by: Biju Das --- v4->v5: * No change v3->v4: * Fixed typo R0A08G046L->R9A08G046L in commit description * Dropped R9A08G046L46 from commit description * Dropped unused audio_clk{1,2} andcan_clk device nodes * Reordered i2c device node and updated reg entries by using lower-case hexadecimal number * Added placeholder in pinctrl node * Dropped unused DMAC device node * Added pcie node with placeholder v2->v3: * No change. v1->v2: * Added external clocks eth{0,1}_txc_tx_clk and eth{0,1}_rxc_rx_clk as it needed for cpg as it is a clock source for mux. * Updated cpg node --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 215 ++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi | 13 ++ 2 files changed, 228 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi new file mode 100644 index 000000000000..20efe09d441e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3L SoC + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible =3D "renesas,r9a08g046"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a55"; + reg =3D <0>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu1: cpu@100 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu2: cpu@200 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu3: cpu@300 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible =3D "cache"; + cache-unified; + cache-size =3D <0x80000>; + cache-level =3D <3>; + }; + }; + + eth0_txc_tx_clk: eth0-txc-tx-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + eth0_rxc_rx_clk: eth0-rxc-rx-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + eth1_txc_tx_clk: eth1-txc-tx-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + eth1_rxc_rx_clk: eth1-rxc-rx-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + extal_clk: extal-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board. */ + clock-frequency =3D <0>; + }; + + psci { + compatible =3D "arm,psci-1.0", "arm,psci-0.2"; + method =3D "smc"; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + scif0: serial@100ac000 { + compatible =3D "renesas,scif-r9a08g046", "renesas,scif-r9a07g044"; + reg =3D <0 0x100ac000 0 0x400>; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks =3D <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>; + clock-names =3D "fck"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>; + status =3D "disabled"; + }; + + i2c0: i2c@100ae000 { + reg =3D <0 0x100ae000 0 0x400>; + #address-cells =3D <1>; + #size-cells =3D <0>; + /* placeholder */ + }; + + canfd: can@100c0000 { + reg =3D <0 0x100c0000 0 0x20000>; + /* placeholder */ + }; + + cpg: clock-controller@11010000 { + compatible =3D "renesas,r9a08g046-cpg"; + reg =3D <0 0x11010000 0 0x10000>; + clocks =3D <&extal_clk>, + <ð0_txc_tx_clk>, <ð0_rxc_rx_clk>, + <ð1_txc_tx_clk>, <ð1_rxc_rx_clk>; + clock-names =3D "extal", + "eth0_txc_tx_clk", "eth0_rxc_rx_clk", + "eth1_txc_tx_clk", "eth1_rxc_rx_clk"; + #clock-cells =3D <2>; + #reset-cells =3D <1>; + #power-domain-cells =3D <0>; + }; + + sysc: system-controller@11020000 { + compatible =3D "renesas,r9a08g046-sysc"; + reg =3D <0 0x11020000 0 0x10000>; + interrupts =3D , + , + , + ; + interrupt-names =3D "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + }; + + pinctrl: pinctrl@11030000 { + reg =3D <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + /* placeholder */ + }; + + sdhi1: mmc@11c10000 { + reg =3D <0x0 0x11c10000 0 0x10000>; + /* placeholder */ + }; + + pcie: pcie@11e40000 { + reg =3D <0 0x11e40000 0 0x10000>; + ranges =3D <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; + /* Map all possible DRAM ranges (4 GB). */ + dma-ranges =3D <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>; + bus-range =3D <0x0 0xff>; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + /* placeholder */ + + pcie_port0: pcie@0,0 { + reg =3D <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + /* placeholder */ + }; + }; + + gic: interrupt-controller@12400000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x12400000 0 0x20000>, + <0x0 0x12440000 0 0x80000>; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi b/arch/arm64/boo= t/dts/renesas/r9a08g046l48.dtsi new file mode 100644 index 000000000000..f6f673abc01b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E R9A08G046L48 SoC specific parts + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a08g046.dtsi" + +/ { + compatible =3D "renesas,r9a08g046l48", "renesas,r9a08g046"; +}; --=20 2.43.0