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Wed, 18 Mar 2026 01:41:58 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Biju Das , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v5 4/9] clk: renesas: rzg2l-cpg: Re-enable critical module clocks during resume Date: Wed, 18 Mar 2026 08:41:39 +0000 Message-ID: <20260318084151.122674-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260318084151.122674-1-biju.das.jz@bp.renesas.com> References: <20260318084151.122674-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das After a suspend/resume cycle, critical module clocks may be left disabled as the hardware state is not automatically restored. Unlike regular clocks which are re-enabled by their respective drivers, critical clocks (CLK_IS_CRITICAL) have no owning driver to restore them, so the CPG driver must take responsibility for re-enabling them on resume. Introduce struct rzg2l_crit_clk_hw to track critical module clock hardware entries in a singly-linked list anchored at crit_clk_hw_head in rzg2l_cpg_priv. Populate the list during module clock registration by checking for the CLK_IS_CRITICAL flag after clk_hw_register() succeeds. On resume, walk the list and re-enable any critical module clock that is found to be disabled, before deasserting critical resets, ensuring the correct clock-before-reset restore ordering. Signed-off-by: Biju Das --- v4->v5: * No change v4: * Moved this patch from [1] as it is boot-dependent [1] https://lore.kernel.org/all/20260306134228.871815-1-biju.das.jz@bp.ren= esas.com/ --- drivers/clk/renesas/rzg2l-cpg.c | 41 +++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 8165c163143a..c2d31b93f62b 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -130,6 +130,12 @@ struct div_hw_data { u32 width; }; =20 +/* Critical clk list */ +struct rzg2l_crit_clk_hw { + struct clk_hw *hw; + struct rzg2l_crit_clk_hw *next; +}; + #define to_div_hw_data(_hw) container_of(_hw, struct div_hw_data, hw_data) =20 struct rzg2l_pll5_param { @@ -168,6 +174,7 @@ struct rzg2l_pll5_mux_dsi_div_param { * @info: Pointer to platform data * @genpd: PM domain * @mux_dsi_div_params: pll5 mux and dsi div parameters + * @crit_clk_hw_head: Head of the linked list critical clk entries */ struct rzg2l_cpg_priv { struct reset_controller_dev rcdev; @@ -186,8 +193,26 @@ struct rzg2l_cpg_priv { struct generic_pm_domain genpd; =20 struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; + + struct rzg2l_crit_clk_hw *crit_clk_hw_head; }; =20 +static int rzg2l_cpg_add_crit_clk_hw_entry(struct rzg2l_cpg_priv *priv, + struct clk_hw *hw) +{ + struct rzg2l_crit_clk_hw *node; + + node =3D devm_kzalloc(priv->dev, sizeof(*node), GFP_KERNEL); + if (!node) + return -ENOMEM; + + node->hw =3D hw; + node->next =3D priv->crit_clk_hw_head; + priv->crit_clk_hw_head =3D node; + + return 0; +} + static inline u8 rzg2l_cpg_div_ab(u8 a, u8 b) { return (b + 1) << a; @@ -1737,6 +1762,13 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_cl= k *mod, goto fail; } =20 + if (init.flags & CLK_IS_CRITICAL) { + if (rzg2l_cpg_add_crit_clk_hw_entry(priv, &clock->hw)) { + clk =3D ERR_PTR(-ENOMEM); + goto fail; + } + } + clk =3D clock->hw.clk; dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); priv->clks[id] =3D clk; @@ -2086,8 +2118,17 @@ static int __init rzg2l_cpg_probe(struct platform_de= vice *pdev) static int rzg2l_cpg_resume(struct device *dev) { struct rzg2l_cpg_priv *priv =3D dev_get_drvdata(dev); + struct rzg2l_crit_clk_hw *node; int ret; =20 + for (node =3D priv->crit_clk_hw_head; node; node =3D node->next) { + if (!rzg2l_mod_clock_is_enabled(node->hw)) { + ret =3D rzg2l_mod_clock_endisable(node->hw, true); + if (ret) + return ret; + } + } + ret =3D rzg2l_cpg_deassert_crit_resets(&priv->rcdev, priv->info); if (ret) return ret; --=20 2.43.0