From nobody Mon Apr 6 20:29:58 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55CF438BF6C for ; Wed, 18 Mar 2026 08:42:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773823325; cv=none; b=tZod3eU9ObgkIsPp6Wsfy/6D0Ecgydu1Eo8LQFIKndMn+j5E3/hWeTX1I0DSJoQMOGY0sEoXxWKbGB0LeZGssNNvAWVwFuipeFtcRzwfoS88b/eb/36VyOs/IyRs4bRn6XkSaqkvK4jBTIbJFCZ5AhrsIfxHc9W7DyUXGD/7wPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773823325; c=relaxed/simple; bh=pV1aqnTgRdbkKR3+cxXrxVzX6kD09lif4yanDAiAM3Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cdRMI9a01+sGvAk03dq7kncJzXu/a1T1Bg4mzjx0Al1U9f+mfLnYojdJyZYwoNcwlqiw3ED0EyrCF9lcbwHc0Glke1BAubudeBNX7UZLZ8cYT6i8gQJJl5U7Tz2Jyt0ppDZo0Hj5wHM1/Jm5++qeIrjTJ8FXsYx/0/dPN1LlKrM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=AGDNOVRo; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AGDNOVRo" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-439b611274bso4073363f8f.3 for ; Wed, 18 Mar 2026 01:42:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773823318; x=1774428118; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pDGj1POSySNjxI79/aFiLpzdpr0qxiPd0OJ5v0IIHTc=; b=AGDNOVRo8So0iTkhw/YxSuqpbyVd7dd/RnJIH8hXqCmWXneIVqnK9pUCz1MZrUfRSE aSSpwPR9a0Wzv3zMxiBkKdGEn0rOPNDkaOvnJTSA0DPRr6kUyEvrGWiMl8ex7Xt545cF OBS1S8adToIwcpF1e+YTGOveLkhVY9xCVmA2e2VlCaVsPClJ0mzhSiGWM2s6bWQHmym3 9JWq7ApxxN5XhveIYxpWyMYLkJStCvINEN5yi5zkcrLPDOFFHpO9IO8HLplyiTbfQfEr YNAGN695FcFzNAiTZ8mExKYGXtG+tb+8CLWqaHDk99wk7y6vXDkNQOWnGPotHaref5Iu Aheg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773823318; x=1774428118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=pDGj1POSySNjxI79/aFiLpzdpr0qxiPd0OJ5v0IIHTc=; b=EX4crdqkNjl56toMmk4QRilq9/9ljrenpH7K6JGG66v96Po0y/r3qh6OFM0rllvckY MWs+TLHKT/Pvtb8VxmYSfNVskMYqFpaN8SOS0Y7utjsybKv3E5Q3zheHa//zWDgOqd8E ybi+V1S+6CUb9J2nHHt+nl+9Gcsw+RxD6H/sSPbzMQ0Qjg95klY4/sniBh6bIICsTfut 8Gkob+C5AG/OB1GNC1RqbPlJHHZ5ocZgy5xhINiQwS8jJi/a45yK7nQgXLLZ5SUDPhU/ nb7Cpc2sNilBiYr13rn4N57W3+HaQ/WvgQfTY2bZ7+nbW94x8w6mDODmwGlEAuFxCKAm hXtg== X-Forwarded-Encrypted: i=1; AJvYcCXFhXXpsnQXjkNUw0IiOtWXzHFS+zhCRif/L5r9AugeTitDL1D0/ZeStUYmICMprDYSAc7R3tAcKygiomc=@vger.kernel.org X-Gm-Message-State: AOJu0YyRq2d0j8M7+gkvT3bV1EwhnwZuhVfdnvHCWVe3/RP3mjUn1meB /iFRU5OuFaU3KedQ+uxRgbkm+ItpBorizZAGd1wtt9mxB9IRTxQt7pnA X-Gm-Gg: ATEYQzwyDnIpMd5dHMiAcrSUIUyrIcWLjTyc6Raf85gz0fDRKo+mGs2c0nRR8Os9PVW aphgl5gf0dbrIu3i+OxOAk3F6DsJbvtjDmnMo5w9jcL1m77HuDuGR3mnGQHzJ4v9EqUo1rC6MwS DJ/b7SPlOvlQYSCSEjN7PWlxhdtu15flLtuAObDx+gPbJpnNCyk8/ALiUER0Tj0BQRNpPOcI80S FbMY9ZyegX5nzGlhvhmEOE97buKoMS3Mv379aTtO/HE0hVbiBqMvab3a0in21DgAmnq4hMDtEAX Saa31KnQJDxzlUDJvD3ZPo/+glRVE88WQE+2ADfF2JB8Fgus9CCPkDAYNcMXTJuakyo7A32fqn3 BOfqcbv3e6gWfQfI9Difg0rn4mH1CUOFt4GsIkUzZs4j0U32ZGIJoDmuhWq2duMybNu3uhiQ3cB iOzCmF++amSJr0+B4XJg4xBYTUJxmZ2mWE9fDZ1/w24tu9CNHT X-Received: by 2002:a05:6000:184f:b0:439:b636:1fa4 with SMTP id ffacd0b85a97d-43b527c9ea5mr3822720f8f.48.1773823317930; Wed, 18 Mar 2026 01:41:57 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:d643:4385:f93a:2085]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b5184961csm6389350f8f.6.2026.03.18.01.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 01:41:57 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v5 3/9] clk: renesas: r9a07g04{3,4}/r9a08g045-cpg: Add critical reset entries Date: Wed, 18 Mar 2026 08:41:38 +0000 Message-ID: <20260318084151.122674-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260318084151.122674-1-biju.das.jz@bp.renesas.com> References: <20260318084151.122674-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G2L SoC family requires DMA resets to be deasserted for routing some peripheral interrupts to the CPU. Asserting these resets after boot would silently break interrupt delivery with no driver to restore them. Mark the DMA resets as critical by adding them to the crit_resets table in the SoC-specific rzg2l_cpg_info for r9a07g043, r9a07g044, and r9a08g045, preventing __rzg2l_cpg_assert() from asserting them and ensuring they are deasserted during probe and resume. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v4->v5: * No change v4: * Moved this patch from [1] as it is boot-dependent [1] https://lore.kernel.org/all/20260306134228.871815-1-biju.das.jz@bp.ren= esas.com/ --- drivers/clk/renesas/r9a07g043-cpg.c | 8 ++++++++ drivers/clk/renesas/r9a07g044-cpg.c | 13 +++++++++++++ drivers/clk/renesas/r9a08g045-cpg.c | 9 +++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a0= 7g043-cpg.c index 33e9a1223c72..01d741ed8dc5 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -379,6 +379,11 @@ static const unsigned int r9a07g043_crit_mod_clks[] __= initconst =3D { MOD_CLK_BASE + R9A07G043_DMAC_ACLK, }; =20 +static const unsigned int r9a07g043_critical_resets[] =3D { + R9A07G043_DMAC_ARESETN, + R9A07G043_DMAC_RST_ASYNC, +}; + #ifdef CONFIG_ARM64 static const unsigned int r9a07g043_no_pm_mod_clks[] =3D { MOD_CLK_BASE + R9A07G043_CRU_SYSCLK, @@ -420,5 +425,8 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info =3D { .num_resets =3D R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ #endif =20 + /* Critical Resets */ + .crit_resets =3D r9a07g043_critical_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a07g043_critical_resets), .has_clk_mon_regs =3D true, }; diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a0= 7g044-cpg.c index 0dd264877b9a..7f1405cab9c3 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -489,6 +489,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __= initconst =3D { MOD_CLK_BASE + R9A07G044_DMAC_ACLK, }; =20 +static const unsigned int r9a07g044_critical_resets[] =3D { + R9A07G044_DMAC_ARESETN, + R9A07G044_DMAC_RST_ASYNC, +}; + static const unsigned int r9a07g044_no_pm_mod_clks[] =3D { MOD_CLK_BASE + R9A07G044_CRU_SYSCLK, MOD_CLK_BASE + R9A07G044_CRU_VCLK, @@ -519,6 +524,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info =3D { .resets =3D r9a07g044_resets, .num_resets =3D R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ =20 + /* Critical Resets */ + .crit_resets =3D r9a07g044_critical_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a07g044_critical_resets), + .has_clk_mon_regs =3D true, }; #endif @@ -548,6 +557,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info =3D { .resets =3D r9a07g044_resets, .num_resets =3D R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ =20 + /* Critical Resets */ + .crit_resets =3D r9a07g044_critical_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a07g044_critical_resets), + .has_clk_mon_regs =3D true, }; #endif diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 79e7b19c7882..87ee43f9fe18 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -361,6 +361,11 @@ static const unsigned int r9a08g045_crit_mod_clks[] __= initconst =3D { MOD_CLK_BASE + R9A08G045_VBAT_BCLK, }; =20 +static const unsigned int r9a08g045_critical_resets[] =3D { + R9A08G045_DMAC_ARESETN, + R9A08G045_DMAC_RST_ASYNC, +}; + static const unsigned int r9a08g045_no_pm_mod_clks[] =3D { MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM, }; @@ -389,5 +394,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info =3D { .resets =3D r9a08g045_resets, .num_resets =3D R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ =20 + /* Critical Resets */ + .crit_resets =3D r9a08g045_critical_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a08g045_critical_resets), + .has_clk_mon_regs =3D true, }; --=20 2.43.0