From nobody Thu Apr 2 01:08:41 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE80E36167C; Wed, 18 Mar 2026 05:53:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773813210; cv=none; b=HAnURuQo84WREYaaGGQuK9OLckkHVZIGwKjCAvN4ps+j7B45PB4BOofro6AlgLy5NznClE7XjV/cER5lsDe+Xa3TY3ayusmDYbRjtpN8IRZYJk2MALDQ3r2jl75OLtnubsKoxny178NPc6a/jZ2RDJBmaUf3B9Jmtf+GpGhuUzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773813210; c=relaxed/simple; bh=e6j7L6dyXdnkxCZknQIxwO1McnHAqOqVEuo1K+uWbBA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NKyBzuvpxG0PKb+kUwmDS94ObT+lga7+QhdV6mszw4rx7ChV4YpoMwpQpy+dFEMhSxOWMkBqk60WVM4T+rlaQ8zEZv6aCps15MELK0p+JjRAxUm441CJAMMm1//hMq7AneQsyo+ZH4m7DCFtlTOcYI3idn7FmrEg4zUE1rLr3PE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=QgM8tIBH; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="QgM8tIBH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1773813210; x=1805349210; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e6j7L6dyXdnkxCZknQIxwO1McnHAqOqVEuo1K+uWbBA=; b=QgM8tIBHkv6AQ9s6QGQAfWoPV2MjlIJtSK0Ups3Fk9bh8VvfrvRnb7UL YCwhrLOMFnN7yYhtiNJ8+guzylNyKjQjKXhQhe6dAXMRp/ymXQH4qelmI 76Ay+3y05WH7gOoCMSFfgc8jfSxPBfbFDvrN/L9nOtk1w3YAPB2/Tz3r0 KRxnijqn0Tu4zTcAT7zg7aVtt9+6vPBrvrNhAZUQRSvenLNNaahip3MuO qlUVBEBf9RLVtKPx/SH8IeivBrYH0cL6ojkkE/4CN7rTmMxR6AzgqS+uq 51IdujC9bxFp91PDQ6xCYVupzbK5seEMKBo2liQMK/42+4jew1kpreEZX Q==; X-CSE-ConnectionGUID: TZ/u7H+YTQiHBRAlQQhOfg== X-CSE-MsgGUID: O+iu4QjKQkOYHT2aTCWNYg== X-Ironport-Invalid-End-Of-Message: True X-IronPort-AV: E=Sophos;i="6.23,126,1770620400"; d="scan'208";a="286208453" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2026 22:53:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Tue, 17 Mar 2026 22:52:59 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 17 Mar 2026 22:52:49 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v4 1/5] dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible Date: Wed, 18 Mar 2026 11:22:26 +0530 Message-ID: <20260318055230.307030-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260318055230.307030-1-manikandan.m@microchip.com> References: <20260318055230.307030-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the microchip,sama7d65-i3c-hci compatible string to the MIPI I3C HCI binding. The Microchip SAMA7D65 I3C controller is based on the MIPI HCI specification but requires two clocks, so add a conditional constraint when this compatible is present. Signed-off-by: Manikandan Muralidharan --- Changes in v4: - Define and describe the clock in the top-level properties --- .../devicetree/bindings/i3c/mipi-i3c-hci.yaml | 26 ++++++++++++++++--- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml b/Docu= mentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml index 39bb1a1784c9..a946a8920046 100644 --- a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml +++ b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml @@ -9,9 +9,6 @@ title: MIPI I3C HCI maintainers: - Nicolas Pitre =20 -allOf: - - $ref: /schemas/i3c/i3c.yaml# - description: | MIPI I3C Host Controller Interface =20 @@ -28,7 +25,13 @@ description: | =20 properties: compatible: - const: mipi-i3c-hci + enum: + - mipi-i3c-hci + - microchip,sama7d65-i3c-hci + clocks: + items: + - description: Peripheral bus clock + - description: System Generic clock reg: maxItems: 1 interrupts: @@ -39,6 +42,21 @@ required: - reg - interrupts =20 +allOf: + - $ref: /schemas/i3c/i3c.yaml# + - if: + properties: + compatible: + contains: + const: microchip,sama7d65-i3c-hci + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + required: + - clocks + unevaluatedProperties: false =20 examples: --=20 2.25.1