From nobody Wed Apr 1 23:53:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE80E36167C; Wed, 18 Mar 2026 05:53:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773813210; cv=none; b=HAnURuQo84WREYaaGGQuK9OLckkHVZIGwKjCAvN4ps+j7B45PB4BOofro6AlgLy5NznClE7XjV/cER5lsDe+Xa3TY3ayusmDYbRjtpN8IRZYJk2MALDQ3r2jl75OLtnubsKoxny178NPc6a/jZ2RDJBmaUf3B9Jmtf+GpGhuUzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773813210; c=relaxed/simple; bh=e6j7L6dyXdnkxCZknQIxwO1McnHAqOqVEuo1K+uWbBA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NKyBzuvpxG0PKb+kUwmDS94ObT+lga7+QhdV6mszw4rx7ChV4YpoMwpQpy+dFEMhSxOWMkBqk60WVM4T+rlaQ8zEZv6aCps15MELK0p+JjRAxUm441CJAMMm1//hMq7AneQsyo+ZH4m7DCFtlTOcYI3idn7FmrEg4zUE1rLr3PE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=QgM8tIBH; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="QgM8tIBH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1773813210; x=1805349210; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e6j7L6dyXdnkxCZknQIxwO1McnHAqOqVEuo1K+uWbBA=; b=QgM8tIBHkv6AQ9s6QGQAfWoPV2MjlIJtSK0Ups3Fk9bh8VvfrvRnb7UL YCwhrLOMFnN7yYhtiNJ8+guzylNyKjQjKXhQhe6dAXMRp/ymXQH4qelmI 76Ay+3y05WH7gOoCMSFfgc8jfSxPBfbFDvrN/L9nOtk1w3YAPB2/Tz3r0 KRxnijqn0Tu4zTcAT7zg7aVtt9+6vPBrvrNhAZUQRSvenLNNaahip3MuO qlUVBEBf9RLVtKPx/SH8IeivBrYH0cL6ojkkE/4CN7rTmMxR6AzgqS+uq 51IdujC9bxFp91PDQ6xCYVupzbK5seEMKBo2liQMK/42+4jew1kpreEZX Q==; X-CSE-ConnectionGUID: TZ/u7H+YTQiHBRAlQQhOfg== X-CSE-MsgGUID: O+iu4QjKQkOYHT2aTCWNYg== X-Ironport-Invalid-End-Of-Message: True X-IronPort-AV: E=Sophos;i="6.23,126,1770620400"; d="scan'208";a="286208453" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2026 22:53:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Tue, 17 Mar 2026 22:52:59 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 17 Mar 2026 22:52:49 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v4 1/5] dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible Date: Wed, 18 Mar 2026 11:22:26 +0530 Message-ID: <20260318055230.307030-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260318055230.307030-1-manikandan.m@microchip.com> References: <20260318055230.307030-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the microchip,sama7d65-i3c-hci compatible string to the MIPI I3C HCI binding. The Microchip SAMA7D65 I3C controller is based on the MIPI HCI specification but requires two clocks, so add a conditional constraint when this compatible is present. Signed-off-by: Manikandan Muralidharan --- Changes in v4: - Define and describe the clock in the top-level properties --- .../devicetree/bindings/i3c/mipi-i3c-hci.yaml | 26 ++++++++++++++++--- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml b/Docu= mentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml index 39bb1a1784c9..a946a8920046 100644 --- a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml +++ b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml @@ -9,9 +9,6 @@ title: MIPI I3C HCI maintainers: - Nicolas Pitre =20 -allOf: - - $ref: /schemas/i3c/i3c.yaml# - description: | MIPI I3C Host Controller Interface =20 @@ -28,7 +25,13 @@ description: | =20 properties: compatible: - const: mipi-i3c-hci + enum: + - mipi-i3c-hci + - microchip,sama7d65-i3c-hci + clocks: + items: + - description: Peripheral bus clock + - description: System Generic clock reg: maxItems: 1 interrupts: @@ -39,6 +42,21 @@ required: - reg - interrupts =20 +allOf: + - $ref: /schemas/i3c/i3c.yaml# + - if: + properties: + compatible: + contains: + const: microchip,sama7d65-i3c-hci + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + required: + - clocks + unevaluatedProperties: false =20 examples: --=20 2.25.1 From nobody Wed Apr 1 23:53:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24BC8361DD2; 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charset="utf-8" From: Durai Manickam KR Add peripheral clock description for I3C. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- changes in v3: - Fixed indentation issues --- drivers/clk/at91/sama7d65.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 7dee2b160ffb..ba8ff413fa2c 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -677,6 +677,7 @@ static struct { { .n =3D "uhphs_clk", .p =3D PCK_PARENT_HW_MCK5, .id =3D 101, }, { .n =3D "dsi_clk", .p =3D PCK_PARENT_HW_MCK3, .id =3D 103, }, { .n =3D "lvdsc_clk", .p =3D PCK_PARENT_HW_MCK3, .id =3D 104, }, + { .n =3D "i3cc_clk", .p =3D PCK_PARENT_HW_MCK8, .id =3D 105, }, }; =20 /* --=20 2.25.1 From nobody Wed Apr 1 23:53:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 426C636213B; Wed, 18 Mar 2026 05:53:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773813211; cv=none; b=aTt9RZ2dOwvKzMQDWyAs5lrYFYEn80+zqcI4QClX609zJr3uPQum/c5+taiMqMcA+5CJGEeS1M01CB3fIuV+E9YU95IHLIv21Zz8g38DaqVMLZl+l0NNk9DeYNHu9oNCtDQf7yl4rJLFlt/ElE50XS5rJossDs8RsuIhJNbhwA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773813211; c=relaxed/simple; bh=RPOloYqq9rrZ7VgT1x2nQRqLYrx+qWYnpICldMjEYvw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=q6DuhYsF7GUq/QWRfiY0wbZrNv9nInRZvrwP0sIIlstpECXuwecrbj6sEWSO9Ewqy5tmdlBvRLq5A3ZnN2nFH83go+HdJHWmRUMcTsZwbXNTe9GIIUkmGKH0GGWIatvH11BpuDzpnzouwmg0M1bXSFNt7MyKxMslaX8XcSzpHJ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=KHQyqqjN; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="KHQyqqjN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1773813211; x=1805349211; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RPOloYqq9rrZ7VgT1x2nQRqLYrx+qWYnpICldMjEYvw=; b=KHQyqqjNzqv5aXsby75rcKrJllEToZFYi6+QxSk2KhbozfD1kCYBnKux mFVRjiiWrLk+8fGrWJqi/8mLimkBs6C5x1cEGh0L6TfA1F+jTXQCWXlkU PEoOtVtabsSqoiiGWX2F4xANkoP1fBgo6h2fFREGi0E0hOBwKfVMQhUec 45ohpxCljpa3bLVFC1ufsJEPFGzazY9GgZVvEunCQZfquCWfzxN+8DQum ddVFlPdJ9AsVV56C7meMrRqCfPOEiNo/dRPSLKhI8w+wU9AzhxmHn7ECQ PbHgVEj+gJQnJemdQFz8Wip2pcS7OeJDc9m5+KBMFqTvIpbWQb3N5f5Ln A==; X-CSE-ConnectionGUID: TZ/u7H+YTQiHBRAlQQhOfg== X-CSE-MsgGUID: Ul09IGzTTum2bn8E84dyIQ== X-IronPort-AV: E=Sophos;i="6.23,126,1770620400"; d="scan'208";a="286208455" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2026 22:53:23 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Tue, 17 Mar 2026 22:53:18 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 17 Mar 2026 22:53:09 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v4 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the appropriate quirk Date: Wed, 18 Mar 2026 11:22:28 +0530 Message-ID: <20260318055230.307030-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260318055230.307030-1-manikandan.m@microchip.com> References: <20260318055230.307030-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for microchip sama7d65 SoC I3C HCI master only IP with additional clock support to enable bulk clock acquisition for Microchip platforms using HCI_QUIRK_CLK_SUPPORT quirk. Signed-off-by: Manikandan Muralidharan --- Changes in v4: - Remove the clock index variable MCHP_I3C_CLK_IDX Changes in v3: - Make use of existing HCI_QUIRK_* code base - Introduce HCI_QUIRK_CLK_SUPPORT to handle/enable the required Peripheral and system generic clk in bulk Changes in v2: - Platform specific changes are integrated in the existing mipi-i3c-hci driver by introducing separate MCHP_HCI_QUIRK_* quirks and vendor specific quirk files --- drivers/i3c/master/mipi-i3c-hci/core.c | 12 ++++++++++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 284f3ed7af8c..41b7737d22ac 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -950,6 +951,7 @@ static int i3c_hci_probe(struct platform_device *pdev) { const struct mipi_i3c_hci_platform_data *pdata =3D pdev->dev.platform_dat= a; struct i3c_hci *hci; + struct clk_bulk_data *clks; int irq, ret; =20 hci =3D devm_kzalloc(&pdev->dev, sizeof(*hci), GFP_KERNEL); @@ -981,6 +983,13 @@ static int i3c_hci_probe(struct platform_device *pdev) if (!hci->quirks && platform_get_device_id(pdev)) hci->quirks =3D platform_get_device_id(pdev)->driver_data; =20 + if (hci->quirks & HCI_QUIRK_CLK_SUPPORT) { + ret =3D devm_clk_bulk_get_all_enabled(&pdev->dev, &clks); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to get clocks\n"); + } + ret =3D i3c_hci_init(hci); if (ret) return ret; @@ -1008,6 +1017,9 @@ static void i3c_hci_remove(struct platform_device *pd= ev) =20 static const __maybe_unused struct of_device_id i3c_hci_of_match[] =3D { { .compatible =3D "mipi-i3c-hci", }, + { .compatible =3D "microchip,sama7d65-i3c-hci", + .data =3D (void *)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | + HCI_QUIRK_RESP_BUF_THLD | HCI_QUIRK_CLK_SUPPORT) }, {}, }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 9ac9d0e342f4..f01b959a28d9 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -150,6 +150,7 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD p= latforms */ #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD= platforms */ #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ +#define HCI_QUIRK_CLK_SUPPORT BIT(6) /* Enable Clocks for Microchip plat= forms*/ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); 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charset="utf-8" From: Durai Manickam KR Add I3C controller for sama7d65 SoC. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- Changes in v3: - Remove clock-names property as driver enables the clk in bulk --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index e21556f46384..f358aae3ec59 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -1015,5 +1015,13 @@ gic: interrupt-controller@e8c11000 { #address-cells =3D <0>; interrupt-controller; }; + + i3c: i3c@e9000000 { + compatible =3D "microchip,sama7d65-i3c-hci"; + reg =3D <0xe9000000 0x300>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 105>, <&pmc PMC_TYPE_GCK 105>; + status =3D "disabled"; + }; }; }; --=20 2.25.1 From nobody Wed Apr 1 23:53:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C819921578D; Wed, 18 Mar 2026 05:54:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773813244; cv=none; b=jgUiUSFgM6P13H2cNLhtA9VbFZbHXGOCyIkmzm9+EATjxsH+akTGl5if5cwmd/eoYQQGtLRjB+E3uM175Qv+eqfYbz6Lvbd68qYW6VX7oFhsmjgkiFXqJCSyePvoe314nUxn+8B85lTKpMS74bKs67Z0Gdo5QTmJU18KjHAqJdI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773813244; c=relaxed/simple; bh=KhmIAgIkXR/FVGhINWVvBX+bl1GcxmHxs9BhpZObeTQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tEm4G1+9+cJdnI4MED3bDCh+Zrq5Q/k4zIMgTmfSE2ldjmDZJ5wFJdy0F7vU4gAyvdwqNFMzdp6vHggN1M0xeXiuUMkpcH/OvB99IM1lK9EnSDNesjDIGTvWPmJKzFqIlJA/m7dMeTaI9PpeeHopjy6Rt0JlwVnJqQVoEWGS3cQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=hvc0WUVy; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hvc0WUVy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1773813245; x=1805349245; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KhmIAgIkXR/FVGhINWVvBX+bl1GcxmHxs9BhpZObeTQ=; b=hvc0WUVy9SSDkVvGcZKoCo+LSNV2+edHbtk3NXl1i9HoEiY0jqQUqfBt nsRfyQgTWo5c4kjgG0M0/s7ZHDA4pvwuI+4zHoArXsFgAoeeDlbBiefBL QngRWxohKfUsG99GW3ygKPz/gPpJ8+pTrFzFcsnpPuIrKqKU5FhJvle9t c5FyLcev0rhsf+az7/AzFzzCmnDIisW22tyrHgzo0RO1yRHTIJI0YAZ+d Rh7MztmYyy/rZDpQcUXCUOAYZmRjAkkxcX6HLCcH8Y36tn5gZXN94k3ve AuZf3ZZaBTp+Bln4a4q9Ku5sK+JJxmrQN+RlZrYlZwhBCXPcEC6O94lb4 w==; X-CSE-ConnectionGUID: 7RnLfcZ3QASwdVwtDRViwQ== X-CSE-MsgGUID: u6QQk4KrTAW3xOJGhrPHnw== X-IronPort-AV: E=Sophos;i="6.23,126,1770620400"; d="scan'208";a="286208477" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 17 Mar 2026 22:54:04 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 17 Mar 2026 22:53:37 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 17 Mar 2026 22:53:28 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: , Durai Manickam KR Subject: [PATCH v4 5/5] ARM: configs: at91: sama7: add sama7d65 i3c-hci Date: Wed, 18 Mar 2026 11:22:30 +0530 Message-ID: <20260318055230.307030-6-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260318055230.307030-1-manikandan.m@microchip.com> References: <20260318055230.307030-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Durai Manickam KR Enable the configs needed for I3C framework and microchip sama7d65 i3c-hci driver. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- arch/arm/configs/sama7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defc= onfig index e2ad9a05566f..a59b262e48e1 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -115,6 +115,8 @@ CONFIG_HW_RANDOM=3Dy CONFIG_I2C=3Dy CONFIG_I2C_CHARDEV=3Dy CONFIG_I2C_AT91=3Dy +CONFIG_I3C=3Dy +CONFIG_MIPI_I3C_HCI=3Dy CONFIG_SPI=3Dy CONFIG_SPI_ATMEL=3Dy CONFIG_SPI_ATMEL_QUADSPI=3Dy --=20 2.25.1