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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82a6bbe801csm1575768b3a.46.2026.03.18.00.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 00:14:44 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 18 Mar 2026 12:44:31 +0530 Subject: [PATCH v2 2/2] pinctrl: qcom: Introduce IPQ5210 TLMM driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-ipq5210_tlmm-v2-2-182d47b3d540@oss.qualcomm.com> References: <20260318-ipq5210_tlmm-v2-0-182d47b3d540@oss.qualcomm.com> In-Reply-To: <20260318-ipq5210_tlmm-v2-0-182d47b3d540@oss.qualcomm.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773818072; l=31425; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=hgyiYXfUv862Qk2EDqnvtZrros0U9RQCyxLc18WI4S8=; b=FmyTrnB5PsQlqux846mteGvsKbv/Eyt2WKTeCu22xIpOHbr2EhKQ5uJWAsasvwFMq7rTxXwAz EZmuNfolhDVBVIFheNJ/mluHuRcYEUETApUVqk5pkdR5KcHJ5N2kpdV X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-ORIG-GUID: 73se_qCvEHWuUwkmEGqgJ5RipueDsQ9E X-Proofpoint-GUID: 73se_qCvEHWuUwkmEGqgJ5RipueDsQ9E X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDA1OSBTYWx0ZWRfX1MpClWcsRYze Tvuh0Vng4qTlswV+SfPg2S780epmy80LHc4o4yfIrgxQZlXHpNtNU4pxyyMUKs9lHuj+Ebqy64f FuzgfooZ/ZRcCcaJB5+YqCacRRYSI96JWMW8CQzwNmTbuy0/6bQ68zjawU2TWjmfGga9B1PsOi5 J7rQNzp84iC8n0wzA7tBg2eghUWtslxDj1cQRaj60nj5w8xAMTs97pOXa2Nw+3CsDpmkLE68GT3 GkmZveuklAlgLogez2NLv29fDohZXSkBty2MA6zGmI5QnMuTokm4siRKE4s6gj+VbzDg/9nJCgL PZjOiMR+uBZjt/xBllEpo8SQjlXFQsKUSnWzxyusNlcRigaN4/Mls5gdawN3mD5fYllc6iVUHqZ fsKZcVBxjBchBw1pRFKIi1/RKoqUHeg3UwZmTrxXJgwUasnbKV9+L6nZpUyGrFmOSpMyWfJYZ+p AxLQdfscmhbVVPIMwhg== X-Authority-Analysis: v=2.4 cv=Y8n1cxeN c=1 sm=1 tr=0 ts=69ba50e6 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=QZrvAM102NmyLNH2iRIA:9 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_05,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180059 Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms, so add a driver for it. Reviewed-by: Dmitry Baryshkov Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio --- drivers/pinctrl/qcom/Kconfig.msm | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5210.c | 1049 ++++++++++++++++++++++++++++= ++++ 3 files changed, 1058 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfi= g.msm index 6df6159fa5f89f9f0470e700b4698dc8849ed515..17416dce8e70cce022c6ffdc2d3= ac8adf7aae1ff 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -58,6 +58,14 @@ config PINCTRL_IPQ8064 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. =20 +config PINCTRL_IPQ5210 + tristate "Qualcomm Technologies Inc IPQ5210 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc IPQ5210 platform. + config PINCTRL_IPQ5332 tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index a8fd12f90d6e6f8e139097cc0a81d6f178f09000..84ff95ff246a4073508d60e92a0= 9f82f989bb50f 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_GLYMUR) +=3D pinctrl-glymur.o obj-$(CONFIG_PINCTRL_IPQ4019) +=3D pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) +=3D pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) +=3D pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_IPQ5210) +=3D pinctrl-ipq5210.o obj-$(CONFIG_PINCTRL_IPQ5332) +=3D pinctrl-ipq5332.o obj-$(CONFIG_PINCTRL_IPQ5424) +=3D pinctrl-ipq5424.o obj-$(CONFIG_PINCTRL_IPQ8074) +=3D pinctrl-ipq8074.o diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5210.c b/drivers/pinctrl/qcom/= pinctrl-ipq5210.c new file mode 100644 index 0000000000000000000000000000000000000000..b0288e6d5c5889a089c5d3eacb8= 38562be2fe243 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq5210.c @@ -0,0 +1,1049 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp =3D PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg =3D REG_SIZE * id, \ + .io_reg =3D 0x4 + REG_SIZE * id, \ + .intr_cfg_reg =3D 0x8 + REG_SIZE * id, \ + .intr_status_reg =3D 0xc + REG_SIZE * id, \ + .intr_target_reg =3D 0x8 + REG_SIZE * id, \ + .mux_bit =3D 2, \ + .pull_bit =3D 0, \ + .drv_bit =3D 6, \ + .oe_bit =3D 9, \ + .in_bit =3D 0, \ + .out_bit =3D 1, \ + .intr_enable_bit =3D 0, \ + .intr_status_bit =3D 0, \ + .intr_target_bit =3D 5, \ + .intr_target_kpss_val =3D 3, \ + .intr_raw_status_bit =3D 4, \ + .intr_polarity_bit =3D 1, \ + .intr_detection_bit =3D 2, \ + .intr_detection_width =3D 2, \ + .funcs =3D (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + }, \ + .nfuncs =3D 10, \ + } + +static const struct pinctrl_pin_desc ipq5210_pins[] =3D { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] =3D { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); + +enum ipq5210_functions { + msm_mux_atest_char_start, + msm_mux_atest_char_status0, + msm_mux_atest_char_status1, + msm_mux_atest_char_status2, + msm_mux_atest_char_status3, + msm_mux_atest_tic_en, + msm_mux_audio_pri0, + msm_mux_audio_pri1, + msm_mux_audio_pri2, + msm_mux_audio_pri3, + msm_mux_audio_pri_d0, + msm_mux_audio_pri_d1, + msm_mux_audio_pri_fsync, + msm_mux_audio_pri_pclk, + msm_mux_audio_sec0, + msm_mux_audio_sec1, + msm_mux_audio_sec2, + msm_mux_audio_sec3, + msm_mux_audio_sec_d0, + msm_mux_audio_sec_d1, + msm_mux_audio_sec_fsync, + msm_mux_audio_sec_pclk, + msm_mux_core_voltage_0, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cri_trng2, + msm_mux_cri_trng3, + msm_mux_dbg_out_clk, + msm_mux_dg_out, + msm_mux_gcc_plltest_bypassnl, + msm_mux_gcc_plltest_resetn, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_led0, + msm_mux_led1, + msm_mux_led2, + msm_mux_mdc_mst, + msm_mux_mdc_slv0, + msm_mux_mdc_slv1, + msm_mux_mdc_slv2, + msm_mux_mdio_mst, + msm_mux_mdio_slv0, + msm_mux_mdio_slv1, + msm_mux_mdio_slv2, + msm_mux_mux_tod_out, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie1_wake, + msm_mux_pll_test, + msm_mux_pon_active_led, + msm_mux_pon_mux_sel, + msm_mux_pon_rx, + msm_mux_pon_rx_los, + msm_mux_pon_tx, + msm_mux_pon_tx_burst, + msm_mux_pon_tx_dis, + msm_mux_pon_tx_fault, + msm_mux_pon_tx_sd, + msm_mux_gpn_rx_los, + msm_mux_gpn_tx_burst, + msm_mux_gpn_tx_dis, + msm_mux_gpn_tx_fault, + msm_mux_gpn_tx_sd, + msm_mux_pps, + msm_mux_pwm, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_qrng_rosc0, + msm_mux_qrng_rosc1, + msm_mux_qrng_rosc2, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs_n, + msm_mux_qup_se0_l0, + msm_mux_qup_se0_l1, + msm_mux_qup_se0_l2, + msm_mux_qup_se0_l3, + msm_mux_qup_se0_l4, + msm_mux_qup_se0_l5, + msm_mux_qup_se1_l0, + msm_mux_qup_se1_l1, + msm_mux_qup_se1_l2, + msm_mux_qup_se1_l3, + msm_mux_qup_se2_l00, + msm_mux_qup_se2_l01, + msm_mux_qup_se2_l10, + msm_mux_qup_se2_l11, + msm_mux_qup_se2_l2, + msm_mux_qup_se2_l3, + msm_mux_qup_se3_l0, + msm_mux_qup_se3_l1, + msm_mux_qup_se3_l2, + msm_mux_qup_se3_l3, + msm_mux_qup_se4_l0, + msm_mux_qup_se4_l1, + msm_mux_qup_se4_l2, + msm_mux_qup_se4_l3, + msm_mux_qup_se4_l4, + msm_mux_qup_se4_l5, + msm_mux_qup_se5_l00, + msm_mux_qup_se5_l01, + msm_mux_qup_se5_l10, + msm_mux_qup_se5_l11, + msm_mux_qup_se5_l2, + msm_mux_qup_se5_l3, + msm_mux_qup_se5_l4, + msm_mux_qup_se5_l5, + msm_mux_resout, + msm_mux_rx_los00, + msm_mux_rx_los01, + msm_mux_rx_los10, + msm_mux_rx_los11, + msm_mux_rx_los20, + msm_mux_rx_los21, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_sdc_data, + msm_mux_tsens_max, + msm_mux__, +}; + +static const char *const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char *const atest_char_start_groups[] =3D { + "gpio46", +}; + +static const char *const atest_char_status0_groups[] =3D { + "gpio34", +}; + +static const char *const atest_char_status1_groups[] =3D { + "gpio35", +}; + +static const char *const atest_char_status2_groups[] =3D { + "gpio36", +}; + +static const char *const atest_char_status3_groups[] =3D { + "gpio37", +}; + +static const char *const atest_tic_en_groups[] =3D { + "gpio42", +}; + +static const char *const audio_pri0_groups[] =3D { + "gpio12", +}; + +static const char *const audio_pri1_groups[] =3D { + "gpio19", +}; + +static const char *const audio_pri2_groups[] =3D { + "gpio8", +}; + +static const char *const audio_pri3_groups[] =3D { + "gpio13", +}; + +static const char *const audio_pri_d0_groups[] =3D { + "gpio34", +}; + +static const char *const audio_pri_d1_groups[] =3D { + "gpio35", +}; + +static const char *const audio_pri_fsync_groups[] =3D { + "gpio36", +}; + +static const char *const audio_pri_pclk_groups[] =3D { + "gpio37", +}; + +static const char *const audio_sec0_groups[] =3D { + "gpio17", +}; + +static const char *const audio_sec1_groups[] =3D { + "gpio16", +}; + +static const char *const audio_sec2_groups[] =3D { + "gpio49", +}; + +static const char *const audio_sec3_groups[] =3D { + "gpio50", +}; + +static const char *const audio_sec_d0_groups[] =3D { + "gpio43", +}; + +static const char *const audio_sec_d1_groups[] =3D { + "gpio42", +}; + +static const char *const audio_sec_fsync_groups[] =3D { + "gpio40", +}; + +static const char *const audio_sec_pclk_groups[] =3D { + "gpio41", +}; + +static const char *const core_voltage_0_groups[] =3D { + "gpio22", +}; + +static const char *const cri_trng0_groups[] =3D { + "gpio6", +}; + +static const char *const cri_trng1_groups[] =3D { + "gpio7", +}; + +static const char *const cri_trng2_groups[] =3D { + "gpio8", +}; + +static const char *const cri_trng3_groups[] =3D { + "gpio9", +}; + +static const char *const dbg_out_clk_groups[] =3D { + "gpio23", +}; + +static const char *const dg_out_groups[] =3D { + "gpio46", +}; + +static const char *const gcc_plltest_bypassnl_groups[] =3D { + "gpio38", +}; + +static const char *const gcc_plltest_resetn_groups[] =3D { + "gpio40", +}; + +static const char *const gcc_tlmm_groups[] =3D { + "gpio39", +}; + +static const char *const led0_groups[] =3D { + "gpio6", "gpio23", "gpio39", +}; + +static const char *const led1_groups[] =3D { + "gpio7", "gpio27", "gpio39", +}; + +static const char *const led2_groups[] =3D { + "gpio9", "gpio26", "gpio38", +}; + +static const char *const mdc_mst_groups[] =3D { + "gpio26", +}; + +static const char *const mdc_slv0_groups[] =3D { + "gpio31", +}; + +static const char *const mdc_slv1_groups[] =3D { + "gpio20", +}; + +static const char *const mdc_slv2_groups[] =3D { + "gpio47", +}; + +static const char *const mdio_mst_groups[] =3D { + "gpio27", +}; + +static const char *const mdio_slv0_groups[] =3D { + "gpio33", +}; + +static const char *const mdio_slv1_groups[] =3D { + "gpio21", +}; + +static const char *const mdio_slv2_groups[] =3D { + "gpio49", +}; + +static const char *const mux_tod_out_groups[] =3D { + "gpio19", +}; + +static const char *const pcie0_clk_req_n_groups[] =3D { + "gpio31", +}; + +static const char *const pcie0_wake_groups[] =3D { + "gpio33", +}; + +static const char *const pcie1_clk_req_n_groups[] =3D { + "gpio28", +}; + +static const char *const pcie1_wake_groups[] =3D { + "gpio30", +}; + +static const char *const pll_test_groups[] =3D { + "gpio18", +}; + +static const char *const pon_active_led_groups[] =3D { + "gpio11", +}; + +static const char *const pon_mux_sel_groups[] =3D { + "gpio45", +}; + +static const char *const pon_rx_groups[] =3D { + "gpio48", +}; + +static const char *const pon_rx_los_groups[] =3D { + "gpio10", +}; + +static const char *const pon_tx_groups[] =3D { + "gpio15", +}; + +static const char *const pon_tx_burst_groups[] =3D { + "gpio14", +}; + +static const char *const pon_tx_dis_groups[] =3D { + "gpio12", +}; + +static const char *const pon_tx_fault_groups[] =3D { + "gpio17", +}; + +static const char *const pon_tx_sd_groups[] =3D { + "gpio16", +}; + +static const char *const gpn_rx_los_groups[] =3D { + "gpio47", +}; + +static const char *const gpn_tx_burst_groups[] =3D { + "gpio51", +}; + +static const char *const gpn_tx_dis_groups[] =3D { + "gpio13", +}; + +static const char *const gpn_tx_fault_groups[] =3D { + "gpio49", +}; + +static const char *const gpn_tx_sd_groups[] =3D { + "gpio50", +}; + +static const char *const pps_groups[] =3D { + "gpio18", +}; + +static const char *const pwm_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio6", "gpio7", "gpio8", "gpio9", + "gpio10", "gpio11", "gpio12", "gpio22", "gpio13", +}; + +static const char *const qdss_cti_trig_in_a0_groups[] =3D { + "gpio30", +}; + +static const char *const qdss_cti_trig_in_a1_groups[] =3D { + "gpio33", +}; + +static const char *const qdss_cti_trig_in_b0_groups[] =3D { + "gpio34", +}; + +static const char *const qdss_cti_trig_in_b1_groups[] =3D { + "gpio37", +}; + +static const char *const qdss_cti_trig_out_a0_groups[] =3D { + "gpio28", +}; + +static const char *const qdss_cti_trig_out_a1_groups[] =3D { + "gpio31", +}; + +static const char *const qdss_cti_trig_out_b0_groups[] =3D { + "gpio16", +}; + +static const char *const qdss_cti_trig_out_b1_groups[] =3D { + "gpio35", +}; + +static const char *const qdss_traceclk_a_groups[] =3D { + "gpio23", +}; + +static const char *const qdss_tracectl_a_groups[] =3D { + "gpio26", +}; + +static const char *const qdss_tracedata_a_groups[] =3D { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21", + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char *const qrng_rosc0_groups[] =3D { + "gpio12", +}; + +static const char *const qrng_rosc1_groups[] =3D { + "gpio13", +}; + +static const char *const qrng_rosc2_groups[] =3D { + "gpio14", +}; + +static const char *const qspi_data_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qspi_clk_groups[] =3D { + "gpio5", +}; + +static const char *const qspi_cs_n_groups[] =3D { + "gpio4", +}; + +static const char *const qup_se0_l0_groups[] =3D { + "gpio8", +}; + +static const char *const qup_se0_l1_groups[] =3D { + "gpio9", +}; + +static const char *const qup_se0_l2_groups[] =3D { + "gpio6", +}; + +static const char *const qup_se0_l3_groups[] =3D { + "gpio7", +}; + +static const char *const qup_se0_l4_groups[] =3D { + "gpio14", +}; + +static const char *const qup_se0_l5_groups[] =3D { + "gpio15", +}; + +static const char *const qup_se1_l0_groups[] =3D { + "gpio30", +}; + +static const char *const qup_se1_l1_groups[] =3D { + "gpio28", +}; + +static const char *const qup_se1_l2_groups[] =3D { + "gpio39", +}; + +static const char *const qup_se1_l3_groups[] =3D { + "gpio38", +}; + +static const char *const qup_se2_l00_groups[] =3D { + "gpio21", +}; + +static const char *const qup_se2_l01_groups[] =3D { + "gpio53", +}; + +static const char *const qup_se2_l10_groups[] =3D { + "gpio20", +}; + +static const char *const qup_se2_l11_groups[] =3D { + "gpio52", +}; + +static const char *const qup_se2_l2_groups[] =3D { + "gpio13", +}; + +static const char *const qup_se2_l3_groups[] =3D { + "gpio12", +}; + +static const char *const qup_se3_l0_groups[] =3D { + "gpio23", +}; + +static const char *const qup_se3_l1_groups[] =3D { + "gpio22", +}; + +static const char *const qup_se3_l2_groups[] =3D { + "gpio11", +}; + +static const char *const qup_se3_l3_groups[] =3D { + "gpio10", +}; + +static const char *const qup_se4_l0_groups[] =3D { + "gpio42", +}; + +static const char *const qup_se4_l1_groups[] =3D { + "gpio43", +}; + +static const char *const qup_se4_l2_groups[] =3D { + "gpio40", +}; + +static const char *const qup_se4_l3_groups[] =3D { + "gpio41", +}; + +static const char *const qup_se4_l4_groups[] =3D { + "gpio52", +}; + +static const char *const qup_se4_l5_groups[] =3D { + "gpio53", +}; + +static const char *const qup_se5_l00_groups[] =3D { + "gpio49", +}; + +static const char *const qup_se5_l01_groups[] =3D { + "gpio52", +}; + +static const char *const qup_se5_l10_groups[] =3D { + "gpio50", +}; + +static const char *const qup_se5_l11_groups[] =3D { + "gpio53", +}; + +static const char *const qup_se5_l2_groups[] =3D { + "gpio47", +}; + +static const char *const qup_se5_l3_groups[] =3D { + "gpio48", +}; + +static const char *const qup_se5_l4_groups[] =3D { + "gpio51", +}; + +static const char *const qup_se5_l5_groups[] =3D { + "gpio52", +}; + +static const char *const resout_groups[] =3D { + "gpio44", +}; + +static const char *const rx_los00_groups[] =3D { + "gpio42", +}; + +static const char *const rx_los01_groups[] =3D { + "gpio37", +}; + +static const char *const rx_los10_groups[] =3D { + "gpio41", +}; + +static const char *const rx_los11_groups[] =3D { + "gpio36", +}; + +static const char *const rx_los20_groups[] =3D { + "gpio40", +}; + +static const char *const rx_los21_groups[] =3D { + "gpio35", +}; + +static const char *const sdc_clk_groups[] =3D { + "gpio5", +}; + +static const char *const sdc_cmd_groups[] =3D { + "gpio4", +}; + +static const char *const sdc_data_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const tsens_max_groups[] =3D { + "gpio20", +}; + +static const struct pinfunction ipq5210_functions[] =3D { + MSM_PIN_FUNCTION(atest_char_start), + MSM_PIN_FUNCTION(atest_char_status0), + MSM_PIN_FUNCTION(atest_char_status1), + MSM_PIN_FUNCTION(atest_char_status2), + MSM_PIN_FUNCTION(atest_char_status3), + MSM_PIN_FUNCTION(atest_tic_en), + MSM_PIN_FUNCTION(audio_pri0), + MSM_PIN_FUNCTION(audio_pri1), + MSM_PIN_FUNCTION(audio_pri2), + MSM_PIN_FUNCTION(audio_pri3), + MSM_PIN_FUNCTION(audio_pri_d0), + MSM_PIN_FUNCTION(audio_pri_d1), + MSM_PIN_FUNCTION(audio_pri_fsync), + MSM_PIN_FUNCTION(audio_pri_pclk), + MSM_PIN_FUNCTION(audio_sec0), + MSM_PIN_FUNCTION(audio_sec1), + MSM_PIN_FUNCTION(audio_sec2), + MSM_PIN_FUNCTION(audio_sec3), + MSM_PIN_FUNCTION(audio_sec_d0), + MSM_PIN_FUNCTION(audio_sec_d1), + MSM_PIN_FUNCTION(audio_sec_fsync), + MSM_PIN_FUNCTION(audio_sec_pclk), + MSM_PIN_FUNCTION(core_voltage_0), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(cri_trng2), + MSM_PIN_FUNCTION(cri_trng3), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(dg_out), + MSM_PIN_FUNCTION(gcc_plltest_bypassnl), + MSM_PIN_FUNCTION(gcc_plltest_resetn), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(led0), + MSM_PIN_FUNCTION(led1), + MSM_PIN_FUNCTION(led2), + MSM_PIN_FUNCTION(mdc_mst), + MSM_PIN_FUNCTION(mdc_slv0), + MSM_PIN_FUNCTION(mdc_slv1), + MSM_PIN_FUNCTION(mdc_slv2), + MSM_PIN_FUNCTION(mdio_mst), + MSM_PIN_FUNCTION(mdio_slv0), + MSM_PIN_FUNCTION(mdio_slv1), + MSM_PIN_FUNCTION(mdio_slv2), + MSM_PIN_FUNCTION(mux_tod_out), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(pon_active_led), + MSM_PIN_FUNCTION(pon_mux_sel), + MSM_PIN_FUNCTION(pon_rx), + MSM_PIN_FUNCTION(pon_rx_los), + MSM_PIN_FUNCTION(pon_tx), + MSM_PIN_FUNCTION(pon_tx_burst), + MSM_PIN_FUNCTION(pon_tx_dis), + MSM_PIN_FUNCTION(pon_tx_fault), + MSM_PIN_FUNCTION(pon_tx_sd), + MSM_PIN_FUNCTION(gpn_rx_los), + MSM_PIN_FUNCTION(gpn_tx_burst), + MSM_PIN_FUNCTION(gpn_tx_dis), + MSM_PIN_FUNCTION(gpn_tx_fault), + MSM_PIN_FUNCTION(gpn_tx_sd), + MSM_PIN_FUNCTION(pps), + MSM_PIN_FUNCTION(pwm), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qrng_rosc0), + MSM_PIN_FUNCTION(qrng_rosc1), + MSM_PIN_FUNCTION(qrng_rosc2), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs_n), + MSM_PIN_FUNCTION(qup_se0_l0), + MSM_PIN_FUNCTION(qup_se0_l1), + MSM_PIN_FUNCTION(qup_se0_l2), + MSM_PIN_FUNCTION(qup_se0_l3), + MSM_PIN_FUNCTION(qup_se0_l4), + MSM_PIN_FUNCTION(qup_se0_l5), + MSM_PIN_FUNCTION(qup_se1_l0), + MSM_PIN_FUNCTION(qup_se1_l1), + MSM_PIN_FUNCTION(qup_se1_l2), + MSM_PIN_FUNCTION(qup_se1_l3), + MSM_PIN_FUNCTION(qup_se2_l00), + MSM_PIN_FUNCTION(qup_se2_l01), + MSM_PIN_FUNCTION(qup_se2_l10), + MSM_PIN_FUNCTION(qup_se2_l11), + MSM_PIN_FUNCTION(qup_se2_l2), + MSM_PIN_FUNCTION(qup_se2_l3), + MSM_PIN_FUNCTION(qup_se3_l0), + MSM_PIN_FUNCTION(qup_se3_l1), + MSM_PIN_FUNCTION(qup_se3_l2), + MSM_PIN_FUNCTION(qup_se3_l3), + MSM_PIN_FUNCTION(qup_se4_l0), + MSM_PIN_FUNCTION(qup_se4_l1), + MSM_PIN_FUNCTION(qup_se4_l2), + MSM_PIN_FUNCTION(qup_se4_l3), + MSM_PIN_FUNCTION(qup_se4_l4), + MSM_PIN_FUNCTION(qup_se4_l5), + MSM_PIN_FUNCTION(qup_se5_l00), + MSM_PIN_FUNCTION(qup_se5_l01), + MSM_PIN_FUNCTION(qup_se5_l10), + MSM_PIN_FUNCTION(qup_se5_l11), + MSM_PIN_FUNCTION(qup_se5_l2), + MSM_PIN_FUNCTION(qup_se5_l3), + MSM_PIN_FUNCTION(qup_se5_l4), + MSM_PIN_FUNCTION(qup_se5_l5), + MSM_PIN_FUNCTION(resout), + MSM_PIN_FUNCTION(rx_los00), + MSM_PIN_FUNCTION(rx_los01), + MSM_PIN_FUNCTION(rx_los10), + MSM_PIN_FUNCTION(rx_los11), + MSM_PIN_FUNCTION(rx_los20), + MSM_PIN_FUNCTION(rx_los21), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(tsens_max), +}; + +static const struct msm_pingroup ipq5210_groups[] =3D { + [0] =3D PINGROUP(0, sdc_data, qspi_data, pwm, _, _, _, _, _, _), + [1] =3D PINGROUP(1, sdc_data, qspi_data, pwm, _, _, _, _, _, _), + [2] =3D PINGROUP(2, sdc_data, qspi_data, pwm, _, _, _, _, _, _), + [3] =3D PINGROUP(3, sdc_data, qspi_data, pwm, _, _, _, _, _, _), + [4] =3D PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _), + [5] =3D PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _), + [6] =3D PINGROUP(6, qup_se0_l2, led0, pwm, _, cri_trng0, qdss_tracedata_a= , _, _, _), + [7] =3D PINGROUP(7, qup_se0_l3, led1, pwm, _, cri_trng1, qdss_tracedata_a= , _, _, _), + [8] =3D PINGROUP(8, qup_se0_l0, pwm, audio_pri2, audio_pri2, _, cri_trng2= , qdss_tracedata_a, _, _), + [9] =3D PINGROUP(9, qup_se0_l1, led2, pwm, _, cri_trng3, qdss_tracedata_a= , _, _, _), + [10] =3D PINGROUP(10, pon_rx_los, qup_se3_l3, pwm, _, _, qdss_tracedata_a= , _, _, _), + [11] =3D PINGROUP(11, pon_active_led, qup_se3_l2, pwm, _, _, qdss_traceda= ta_a, _, _, _), + [12] =3D PINGROUP(12, pon_tx_dis, qup_se2_l3, pwm, audio_pri0, audio_pri0= , _, qrng_rosc0, qdss_tracedata_a, _), + [13] =3D PINGROUP(13, gpn_tx_dis, qup_se2_l2, pwm, audio_pri3, audio_pri3= , _, qrng_rosc1, qdss_tracedata_a, _), + [14] =3D PINGROUP(14, pon_tx_burst, qup_se0_l4, _, qrng_rosc2, qdss_trace= data_a, _, _, _, _), + [15] =3D PINGROUP(15, pon_tx, qup_se0_l5, _, qdss_tracedata_a, _, _, _, _= , _), + [16] =3D PINGROUP(16, pon_tx_sd, audio_sec1, audio_sec1, qdss_cti_trig_ou= t_b0, _, _, _, _, _), + [17] =3D PINGROUP(17, pon_tx_fault, audio_sec0, audio_sec0, _, _, _, _, _= , _), + [18] =3D PINGROUP(18, pps, pll_test, _, _, _, _, _, _, _), + [19] =3D PINGROUP(19, mux_tod_out, audio_pri1, audio_pri1, _, _, _, _, _,= _), + [20] =3D PINGROUP(20, qup_se2_l10, mdc_slv1, tsens_max, qdss_tracedata_a,= _, _, _, _, _), + [21] =3D PINGROUP(21, qup_se2_l00, mdio_slv1, qdss_tracedata_a, _, _, _, = _, _, _), + [22] =3D PINGROUP(22, core_voltage_0, qup_se3_l1, pwm, _, _, _, _, _, _), + [23] =3D PINGROUP(23, led0, qup_se3_l0, dbg_out_clk, qdss_traceclk_a, _, = _, _, _, _), + [24] =3D PINGROUP(24, _, _, _, _, _, _, _, _, _), + [25] =3D PINGROUP(25, _, _, _, _, _, _, _, _, _), + [26] =3D PINGROUP(26, mdc_mst, led2, _, qdss_tracectl_a, _, _, _, _, _), + [27] =3D PINGROUP(27, mdio_mst, led1, _, _, _, _, _, _, _), + [28] =3D PINGROUP(28, pcie1_clk_req_n, qup_se1_l1, _, _, qdss_cti_trig_ou= t_a0, _, _, _, _), + [29] =3D PINGROUP(29, _, _, _, _, _, _, _, _, _), + [30] =3D PINGROUP(30, pcie1_wake, qup_se1_l0, _, _, qdss_cti_trig_in_a0, = _, _, _, _), + [31] =3D PINGROUP(31, pcie0_clk_req_n, mdc_slv0, _, qdss_cti_trig_out_a1,= _, _, _, _, _), + [32] =3D PINGROUP(32, _, _, _, _, _, _, _, _, _), + [33] =3D PINGROUP(33, pcie0_wake, mdio_slv0, qdss_cti_trig_in_a1, _, _, _= , _, _, _), + [34] =3D PINGROUP(34, audio_pri_d0, atest_char_status0, qdss_cti_trig_in_= b0, _, _, _, _, _, _), + [35] =3D PINGROUP(35, audio_pri_d1, rx_los21, atest_char_status1, qdss_ct= i_trig_out_b1, _, _, _, _, _), + [36] =3D PINGROUP(36, audio_pri_fsync, _, rx_los11, atest_char_status2, _= , _, _, _, _), + [37] =3D PINGROUP(37, audio_pri_pclk, rx_los01, atest_char_status3, _, qd= ss_cti_trig_in_b1, _, _, _, _), + [38] =3D PINGROUP(38, qup_se1_l3, led2, gcc_plltest_bypassnl, qdss_traced= ata_a, _, _, _, _, _), + [39] =3D PINGROUP(39, qup_se1_l2, led1, led0, gcc_tlmm, qdss_tracedata_a,= _, _, _, _), + [40] =3D PINGROUP(40, qup_se4_l2, rx_los20, audio_sec_fsync, gcc_plltest_= resetn, qdss_tracedata_a, _, _, _, _), + [41] =3D PINGROUP(41, qup_se4_l3, rx_los10, audio_sec_pclk, qdss_tracedat= a_a, _, _, _, _, _), + [42] =3D PINGROUP(42, qup_se4_l0, rx_los00, audio_sec_d1, atest_tic_en, _= , _, _, _, _), + [43] =3D PINGROUP(43, qup_se4_l1, audio_sec_d0, _, _, _, _, _, _, _), + [44] =3D PINGROUP(44, resout, _, _, _, _, _, _, _, _), + [45] =3D PINGROUP(45, pon_mux_sel, _, _, _, _, _, _, _, _), + [46] =3D PINGROUP(46, dg_out, atest_char_start, _, _, _, _, _, _, _), + [47] =3D PINGROUP(47, gpn_rx_los, mdc_slv2, qup_se5_l2, _, _, _, _, _, _), + [48] =3D PINGROUP(48, pon_rx, qup_se5_l3, _, _, _, _, _, _, _), + [49] =3D PINGROUP(49, gpn_tx_fault, mdio_slv2, qup_se5_l00, audio_sec2, a= udio_sec2, _, _, _, _), + [50] =3D PINGROUP(50, gpn_tx_sd, qup_se5_l10, audio_sec3, audio_sec3, _, = _, _, _, _), + [51] =3D PINGROUP(51, gpn_tx_burst, qup_se5_l4, _, _, _, _, _, _, _), + [52] =3D PINGROUP(52, qup_se2_l11, qup_se5_l5, qup_se4_l4, qup_se5_l01, _= , _, _, _, _), + [53] =3D PINGROUP(53, qup_se2_l01, qup_se4_l5, qup_se5_l11, _, _, _, _, _= , _), +}; + +static const struct msm_pinctrl_soc_data ipq5210_tlmm =3D { + .pins =3D ipq5210_pins, + .npins =3D ARRAY_SIZE(ipq5210_pins), + .functions =3D ipq5210_functions, + .nfunctions =3D ARRAY_SIZE(ipq5210_functions), + .groups =3D ipq5210_groups, + .ngroups =3D ARRAY_SIZE(ipq5210_groups), + .ngpios =3D 54, +}; + +static const struct of_device_id ipq5210_tlmm_of_match[] =3D { + { .compatible =3D "qcom,ipq5210-tlmm", }, + { }, +}; + +static int ipq5210_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq5210_tlmm); +} + +static struct platform_driver ipq5210_tlmm_driver =3D { + .driver =3D { + .name =3D "ipq5210-tlmm", + .of_match_table =3D ipq5210_tlmm_of_match, + }, + .probe =3D ipq5210_tlmm_probe, +}; + +static int __init ipq5210_tlmm_init(void) +{ + return platform_driver_register(&ipq5210_tlmm_driver); +} +arch_initcall(ipq5210_tlmm_init); + +static void __exit ipq5210_tlmm_exit(void) +{ + platform_driver_unregister(&ipq5210_tlmm_driver); +} +module_exit(ipq5210_tlmm_exit); + +MODULE_DESCRIPTION("QTI IPQ5210 TLMM driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1