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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- .../bindings/clock/qcom,ipq5210-gcc.yaml | 62 ++++++++++ include/dt-bindings/clock/qcom,ipq5210-gcc.h | 126 +++++++++++++++++= +++ include/dt-bindings/reset/qcom,ipq5210-gcc.h | 127 +++++++++++++++++= ++++ 3 files changed, 315 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..f1cc3fc190855708c28868224a8= ac4a1454a7831 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5210 + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: | + Qualcomm global clock control module provides the clocks, resets and pow= er + domains on IPQ5210 + + See also: + include/dt-bindings/clock/qcom,ipq5210-gcc.h + include/dt-bindings/reset/qcom,ipq5210-gcc.h + +properties: + compatible: + const: qcom,ipq5210-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: USB3 PHY pipe clock source + - description: NSS common clock source + + '#power-domain-cells': false + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible =3D "qcom,ipq5210-gcc"; + reg =3D <0x01800000 0x40000>; + clocks =3D <&xo_board_clk>, + <&sleep_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>, + <&nss_cmn_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq5210-gcc.h b/include/dt-bind= ings/clock/qcom,ipq5210-gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..84116f34ee4d0433a092987e8d1= 89c2aa95da204 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5210-gcc.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H + +#define GCC_ADSS_PWM_CLK 0 +#define GCC_ADSS_PWM_CLK_SRC 1 +#define GCC_CMN_12GPLL_AHB_CLK 2 +#define GCC_CMN_12GPLL_SYS_CLK 3 +#define GCC_CNOC_LPASS_CFG_CLK 4 +#define GCC_CNOC_PCIE0_1LANE_S_CLK 5 +#define GCC_CNOC_PCIE1_2LANE_S_CLK 6 +#define GCC_CNOC_USB_CLK 7 +#define GCC_GEPHY_SYS_CLK 8 +#define GCC_LPASS_AXIM_CLK_SRC 9 +#define GCC_LPASS_CORE_AXIM_CLK 10 +#define GCC_LPASS_SWAY_CLK 11 +#define GCC_LPASS_SWAY_CLK_SRC 12 +#define GCC_MDIO_AHB_CLK 13 +#define GCC_MDIO_GEPHY_AHB_CLK 14 +#define GCC_NSS_TS_CLK 15 +#define GCC_NSS_TS_CLK_SRC 16 +#define GCC_NSSCC_CLK 17 +#define GCC_NSSCFG_CLK 18 +#define GCC_NSSNOC_ATB_CLK 19 +#define GCC_NSSNOC_MEMNOC_1_CLK 20 +#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 +#define GCC_NSSNOC_MEMNOC_CLK 22 +#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 +#define GCC_NSSNOC_NSSCC_CLK 24 +#define GCC_NSSNOC_PCNOC_1_CLK 25 +#define GCC_NSSNOC_QOSGEN_REF_CLK 26 +#define GCC_NSSNOC_SNOC_1_CLK 27 +#define GCC_NSSNOC_SNOC_CLK 28 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 29 +#define GCC_NSSNOC_XO_DCD_CLK 30 +#define GCC_PCIE0_AHB_CLK 31 +#define GCC_PCIE0_AUX_CLK 32 +#define GCC_PCIE0_AXI_M_CLK 33 +#define GCC_PCIE0_AXI_M_CLK_SRC 34 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 35 +#define GCC_PCIE0_AXI_S_CLK 36 +#define GCC_PCIE0_AXI_S_CLK_SRC 37 +#define GCC_PCIE0_PIPE_CLK 38 +#define GCC_PCIE0_PIPE_CLK_SRC 39 +#define GCC_PCIE0_RCHNG_CLK 40 +#define GCC_PCIE0_RCHNG_CLK_SRC 41 +#define GCC_PCIE1_AHB_CLK 42 +#define GCC_PCIE1_AUX_CLK 43 +#define GCC_PCIE1_AXI_M_CLK 44 +#define GCC_PCIE1_AXI_M_CLK_SRC 45 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 46 +#define GCC_PCIE1_AXI_S_CLK 47 +#define GCC_PCIE1_AXI_S_CLK_SRC 48 +#define GCC_PCIE1_PIPE_CLK 49 +#define GCC_PCIE1_PIPE_CLK_SRC 50 +#define GCC_PCIE1_RCHNG_CLK 51 +#define GCC_PCIE1_RCHNG_CLK_SRC 52 +#define GCC_PCIE_AUX_CLK_SRC 53 +#define GCC_PCNOC_BFDCD_CLK_SRC 54 +#define GCC_PON_APB_CLK 55 +#define GCC_PON_TM_CLK 56 +#define GCC_PON_TM2X_CLK 57 +#define GCC_PON_TM2X_CLK_SRC 58 +#define GCC_QDSS_AT_CLK 59 +#define GCC_QDSS_AT_CLK_SRC 60 +#define GCC_QDSS_DAP_CLK 61 +#define GCC_QDSS_TSCTR_CLK_SRC 62 +#define GCC_QPIC_AHB_CLK 63 +#define GCC_QPIC_CLK 64 +#define GCC_QPIC_CLK_SRC 65 +#define GCC_QPIC_IO_MACRO_CLK 66 +#define GCC_QPIC_IO_MACRO_CLK_SRC 67 +#define GCC_QRNG_AHB_CLK 68 +#define GCC_QUPV3_AHB_MST_CLK 69 +#define GCC_QUPV3_AHB_SLV_CLK 70 +#define GCC_QUPV3_WRAP_SE0_CLK 71 +#define GCC_QUPV3_WRAP_SE0_CLK_SRC 72 +#define GCC_QUPV3_WRAP_SE1_CLK 73 +#define GCC_QUPV3_WRAP_SE1_CLK_SRC 74 +#define GCC_QUPV3_WRAP_SE2_CLK 75 +#define GCC_QUPV3_WRAP_SE2_CLK_SRC 76 +#define GCC_QUPV3_WRAP_SE3_CLK 77 +#define GCC_QUPV3_WRAP_SE3_CLK_SRC 78 +#define GCC_QUPV3_WRAP_SE4_CLK 79 +#define GCC_QUPV3_WRAP_SE4_CLK_SRC 80 +#define GCC_QUPV3_WRAP_SE5_CLK 81 +#define GCC_QUPV3_WRAP_SE5_CLK_SRC 82 +#define GCC_SDCC1_AHB_CLK 83 +#define GCC_SDCC1_APPS_CLK 84 +#define GCC_SDCC1_APPS_CLK_SRC 85 +#define GCC_SDCC1_ICE_CORE_CLK 86 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 87 +#define GCC_SLEEP_CLK_SRC 88 +#define GCC_SNOC_LPASS_CLK 89 +#define GCC_SNOC_PCIE0_AXI_M_CLK 90 +#define GCC_SNOC_PCIE1_AXI_M_CLK 91 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 92 +#define GCC_UNIPHY0_AHB_CLK 93 +#define GCC_UNIPHY0_SYS_CLK 94 +#define GCC_UNIPHY1_AHB_CLK 95 +#define GCC_UNIPHY1_SYS_CLK 96 +#define GCC_UNIPHY2_AHB_CLK 97 +#define GCC_UNIPHY2_SYS_CLK 98 +#define GCC_UNIPHY_SYS_CLK_SRC 99 +#define GCC_USB0_AUX_CLK 100 +#define GCC_USB0_AUX_CLK_SRC 101 +#define GCC_USB0_MASTER_CLK 102 +#define GCC_USB0_MASTER_CLK_SRC 103 +#define GCC_USB0_MOCK_UTMI_CLK 104 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 105 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 106 +#define GCC_USB0_PHY_CFG_AHB_CLK 107 +#define GCC_USB0_PIPE_CLK 108 +#define GCC_USB0_PIPE_CLK_SRC 109 +#define GCC_USB0_SLEEP_CLK 110 +#define GCC_XO_CLK_SRC 111 +#define GPLL0_MAIN 112 +#define GPLL0 113 +#define GPLL2_MAIN 114 +#define GPLL2 115 +#define GPLL4_MAIN 116 +#endif diff --git a/include/dt-bindings/reset/qcom,ipq5210-gcc.h b/include/dt-bind= ings/reset/qcom,ipq5210-gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..09890a09087c39288683d105437= fc68f3d68be4c --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq5210-gcc.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H +#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_ARES 1 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES 3 +#define GCC_APSS_AHB_ARES 4 +#define GCC_APSS_ATB_ARES 5 +#define GCC_APSS_AXI_ARES 6 +#define GCC_APSS_TS_ARES 7 +#define GCC_BOOT_ROM_AHB_ARES 8 +#define GCC_BOOT_ROM_BCR 9 +#define GCC_GEPHY_BCR 10 +#define GCC_GEPHY_SYS_ARES 11 +#define GCC_GP1_ARES 12 +#define GCC_GP2_ARES 13 +#define GCC_GP3_ARES 14 +#define GCC_MDIO_AHB_ARES 15 +#define GCC_MDIO_BCR 16 +#define GCC_MDIO_GEPHY_AHB_ARES 17 +#define GCC_NSS_BCR 18 +#define GCC_NSS_TS_ARES 19 +#define GCC_NSSCC_ARES 20 +#define GCC_NSSCFG_ARES 21 +#define GCC_NSSNOC_ATB_ARES 22 +#define GCC_NSSNOC_MEMNOC_1_ARES 23 +#define GCC_NSSNOC_MEMNOC_ARES 24 +#define GCC_NSSNOC_NSSCC_ARES 25 +#define GCC_NSSNOC_PCNOC_1_ARES 26 +#define GCC_NSSNOC_QOSGEN_REF_ARES 27 +#define GCC_NSSNOC_SNOC_1_ARES 28 +#define GCC_NSSNOC_SNOC_ARES 29 +#define GCC_NSSNOC_TIMEOUT_REF_ARES 30 +#define GCC_NSSNOC_XO_DCD_ARES 31 +#define GCC_PCIE0_AHB_ARES 32 +#define GCC_PCIE0_AUX_ARES 33 +#define GCC_PCIE0_AXI_M_ARES 34 +#define GCC_PCIE0_AXI_S_BRIDGE_ARES 35 +#define GCC_PCIE0_AXI_S_ARES 36 +#define GCC_PCIE0_BCR 37 +#define GCC_PCIE0_LINK_DOWN_BCR 38 +#define GCC_PCIE0_PHY_BCR 39 +#define GCC_PCIE0_PIPE_ARES 40 +#define GCC_PCIE0PHY_PHY_BCR 41 +#define GCC_PCIE1_AHB_ARES 42 +#define GCC_PCIE1_AUX_ARES 43 +#define GCC_PCIE1_AXI_M_ARES 44 +#define GCC_PCIE1_AXI_S_BRIDGE_ARES 45 +#define GCC_PCIE1_AXI_S_ARES 46 +#define GCC_PCIE1_BCR 47 +#define GCC_PCIE1_LINK_DOWN_BCR 48 +#define GCC_PCIE1_PHY_BCR 49 +#define GCC_PCIE1_PIPE_ARES 50 +#define GCC_PCIE1PHY_PHY_BCR 51 +#define GCC_QRNG_AHB_ARES 52 +#define GCC_QRNG_BCR 53 +#define GCC_QUPV3_2X_CORE_ARES 54 +#define GCC_QUPV3_AHB_MST_ARES 55 +#define GCC_QUPV3_AHB_SLV_ARES 56 +#define GCC_QUPV3_BCR 57 +#define GCC_QUPV3_CORE_ARES 58 +#define GCC_QUPV3_WRAP_SE0_ARES 59 +#define GCC_QUPV3_WRAP_SE0_BCR 60 +#define GCC_QUPV3_WRAP_SE1_ARES 61 +#define GCC_QUPV3_WRAP_SE1_BCR 62 +#define GCC_QUPV3_WRAP_SE2_ARES 63 +#define GCC_QUPV3_WRAP_SE2_BCR 64 +#define GCC_QUPV3_WRAP_SE3_ARES 65 +#define GCC_QUPV3_WRAP_SE3_BCR 66 +#define GCC_QUPV3_WRAP_SE4_ARES 67 +#define GCC_QUPV3_WRAP_SE4_BCR 68 +#define GCC_QUPV3_WRAP_SE5_ARES 69 +#define GCC_QUPV3_WRAP_SE5_BCR 70 +#define GCC_QUSB2_0_PHY_BCR 71 +#define GCC_SDCC1_AHB_ARES 72 +#define GCC_SDCC1_APPS_ARES 73 +#define GCC_SDCC1_ICE_CORE_ARES 74 +#define GCC_SDCC_BCR 75 +#define GCC_TLMM_AHB_ARES 76 +#define GCC_TLMM_ARES 77 +#define GCC_TLMM_BCR 78 +#define GCC_UNIPHY0_AHB_ARES 79 +#define GCC_UNIPHY0_BCR 80 +#define GCC_UNIPHY0_SYS_ARES 81 +#define GCC_UNIPHY1_AHB_ARES 82 +#define GCC_UNIPHY1_BCR 83 +#define GCC_UNIPHY1_SYS_ARES 84 +#define GCC_UNIPHY2_AHB_ARES 85 +#define GCC_UNIPHY2_BCR 86 +#define GCC_UNIPHY2_SYS_ARES 87 +#define GCC_USB0_AUX_ARES 88 +#define GCC_USB0_MASTER_ARES 89 +#define GCC_USB0_MOCK_UTMI_ARES 90 +#define GCC_USB0_PHY_BCR 91 +#define GCC_USB0_PHY_CFG_AHB_ARES 92 +#define GCC_USB0_PIPE_ARES 93 +#define GCC_USB0_SLEEP_ARES 94 +#define GCC_USB3PHY_0_PHY_BCR 95 +#define GCC_USB_BCR 96 +#define GCC_PCIE0_PIPE_RESET 97 +#define GCC_PCIE0_CORE_STICKY_RESET 98 +#define GCC_PCIE0_AXI_S_STICKY_RESET 99 +#define GCC_PCIE0_AXI_S_RESET 100 +#define GCC_PCIE0_AXI_M_STICKY_RESET 101 +#define GCC_PCIE0_AXI_M_RESET 102 +#define GCC_PCIE0_AUX_RESET 103 +#define GCC_PCIE0_AHB_RESET 104 +#define GCC_PCIE1_PIPE_RESET 105 +#define GCC_PCIE1_CORE_STICKY_RESET 106 +#define GCC_PCIE1_AXI_S_STICKY_RESET 107 +#define GCC_PCIE1_AXI_S_RESET 108 +#define GCC_PCIE1_AXI_M_STICKY_RESET 109 +#define GCC_PCIE1_AXI_M_RESET 110 +#define GCC_PCIE1_AUX_RESET 111 +#define GCC_PCIE1_AHB_RESET 112 +#define GCC_UNIPHY0_XPCS_ARES 113 +#define GCC_UNIPHY1_XPCS_ARES 114 +#define GCC_UNIPHY2_XPCS_ARES 115 +#define GCC_QDSS_BCR 116 + +#endif --=20 2.34.1 From nobody Mon Apr 6 18:56:45 2026 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Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq5210.c | 2661 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 2670 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 87728f13f948a68307163c48a7327ae0c84d82d0..df38fc3f29a146b3a80e3ae4994= 86a92e60cbe96 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -349,6 +349,14 @@ config IPQ_GCC_5018 Say Y if you want to use peripheral devices such as UART, SPI, i2c, USB, SD/eMMC, etc. =20 +config IPQ_GCC_5210 + tristate "IPQ5210 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + help + Support for the global clock controller on ipq5210 devices. + Say Y if you want to use peripheral devices such as UART, SPI, + i2c, USB, SD/eMMC, etc. + config IPQ_GCC_5332 tristate "IPQ5332 Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 82c5c2ec968ed0dfe5d1cc7ef5f17c67162186ea..807a7c9071a7d5e611aeba334b2= 71be9a8216c6c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_IPQ_APSS_6018) +=3D apss-ipq6018.o obj-$(CONFIG_IPQ_CMN_PLL) +=3D ipq-cmn-pll.o obj-$(CONFIG_IPQ_GCC_4019) +=3D gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_5018) +=3D gcc-ipq5018.o +obj-$(CONFIG_IPQ_GCC_5210) +=3D gcc-ipq5210.o obj-$(CONFIG_IPQ_GCC_5332) +=3D gcc-ipq5332.o obj-$(CONFIG_IPQ_GCC_5424) +=3D gcc-ipq5424.o obj-$(CONFIG_IPQ_GCC_6018) +=3D gcc-ipq6018.o diff --git a/drivers/clk/qcom/gcc-ipq5210.c b/drivers/clk/qcom/gcc-ipq5210.c new file mode 100644 index 0000000000000000000000000000000000000000..3a786a21bdff56d90595ff03095= edbab8c39369f --- /dev/null +++ b/drivers/clk/qcom/gcc-ipq5210.c @@ -0,0 +1,2661 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "reset.h" + +enum { + DT_XO, + DT_SLEEP_CLK, + DT_PCIE30_PHY0_PIPE_CLK, + DT_PCIE30_PHY1_PIPE_CLK, + DT_USB3_PHY0_CC_PIPE_CLK, + DT_NSS_CMN_CLK, +}; + +enum { + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, + P_GPLL0_OUT_AUX, + P_GPLL0_OUT_MAIN, + P_GPLL2_OUT_AUX, + P_GPLL2_OUT_MAIN, + P_GPLL4_OUT_AUX, + P_GPLL4_OUT_MAIN, + P_NSS_CMN_CLK, + P_SLEEP_CLK, + P_USB3PHY_0_PIPE, + P_XO, +}; + +static const struct clk_parent_data gcc_parent_data_xo =3D { .index =3D DT= _XO }; + +static struct clk_alpha_pll gpll0_main =3D { + .offset =3D 0x20000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_main", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll0_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_div2", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_main.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll_postdiv gpll0 =3D { + .offset =3D 0x20000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_main.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static struct clk_alpha_pll gpll2_main =3D { + .offset =3D 0x21000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll2_main", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll2[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll2 =3D { + .offset =3D 0x21000, + .post_div_table =3D post_div_table_gpll2, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll2), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll2", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll2_main.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static struct clk_alpha_pll gpll4_main =3D { + .offset =3D 0x22000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll4_main", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + /* + * There are no consumers for this GPLL in kernel yet, + * (will be added soon), so the clock framework + * disables this source. But some of the clocks + * initialized by boot loaders uses this source. So we + * need to keep this clock ON. Add the + * CLK_IGNORE_UNUSED flag so the clock will not be + * disabled. Once the consumer in kernel is added, we + * can get rid of this flag. + */ + .flags =3D CLK_IS_CRITICAL, + }, + }, +}; +static const struct parent_map gcc_parent_map_xo[] =3D { + { P_XO, 0 }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_XO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_XO }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_XO, 0 }, + { P_NSS_CMN_CLK, 1 }, + { P_GPLL0_OUT_AUX, 2 }, + { P_GPLL2_OUT_AUX, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_NSS_CMN_CLK }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_AUX, 2 }, + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL2_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_7[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4_main.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_8[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_AUX, 2 }, + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_9[] =3D { + { P_XO, 0 }, + { P_GPLL4_OUT_AUX, 1 }, + { P_GPLL0_OUT_MAIN, 3 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll4_main.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_10[] =3D { + { P_XO, 0 }, + { P_GPLL4_OUT_MAIN, 1 }, + { P_GPLL0_OUT_AUX, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll4_main.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_11[] =3D { + { P_XO, 0 }, + { P_GPLL4_OUT_MAIN, 1 }, + { P_GPLL0_OUT_AUX, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll4_main.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_12[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL2_OUT_AUX, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_13[] =3D { + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_13[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_adss_pwm_clk_src =3D { + .cmd_rcgr =3D 0x1c004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_adss_pwm_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_nss_ts_clk_src =3D { + .cmd_rcgr =3D 0x17088, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nss_ts_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x2e004, + .freq_tbl =3D ftbl_gcc_system_noc_bfdcd_clk_src, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_7, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_system_noc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src[] =3D { + F(429000000, P_NSS_CMN_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_nssnoc_memnoc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x17004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] =3D { + F(200000000, P_GPLL4_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie0_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x28018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_m_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie0_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x28020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie0_rchng_clk_src =3D { + .cmd_rcgr =3D 0x28028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_rchng_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie1_axi_m_clk_src[] =3D { + F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie1_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x29018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie1_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_m_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie1_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x29020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie1_rchng_clk_src =3D { + .cmd_rcgr =3D 0x29028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_rchng_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] =3D { + F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4), + { } +}; + +static struct clk_rcg2 gcc_pcie_aux_clk_src =3D { + .cmd_rcgr =3D 0x28004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_pcie_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap_se0_clk_src[] =3D { + F(960000, P_XO, 10, 2, 5), + F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217), + F(4800000, P_XO, 5, 0, 0), + F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217), + F(9600000, P_XO, 2.5, 0, 0), + F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217), + F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), + F(24000000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), + F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250), + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), + F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217), + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), + F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se0_clk_src =3D { + .cmd_rcgr =3D 0x4004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se1_clk_src =3D { + .cmd_rcgr =3D 0x5004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se2_clk_src =3D { + .cmd_rcgr =3D 0x2018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se3_clk_src =3D { + .cmd_rcgr =3D 0x2034, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se4_clk_src =3D { + .cmd_rcgr =3D 0x3018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se5_clk_src =3D { + .cmd_rcgr =3D 0x3034, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] =3D { + F(144000, P_XO, 16, 12, 125), + F(400000, P_XO, 12, 1, 5), + F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2), + F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0), + F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0), + F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x33004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] =3D { + F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x33018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_7, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ice_core_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static struct clk_rcg2 gcc_uniphy_sys_clk_src =3D { + .cmd_rcgr =3D 0x17090, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy_sys_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb0_aux_clk_src =3D { + .cmd_rcgr =3D 0x2c018, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_8, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_aux_clk_src", + .parent_data =3D gcc_parent_data_8, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb0_master_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb0_master_clk_src =3D { + .cmd_rcgr =3D 0x2c004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb0_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] =3D { + F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2), + { } +}; + +static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x2c02c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_9, + .freq_tbl =3D ftbl_gcc_usb0_mock_utmi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_9, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_9), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] =3D { + F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qdss_at_clk_src =3D { + .cmd_rcgr =3D 0x2d004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_10, + .freq_tbl =3D ftbl_gcc_qdss_at_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_at_clk_src", + .parent_data =3D gcc_parent_data_10, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] =3D { + F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qdss_tsctr_clk_src =3D { + .cmd_rcgr =3D 0x2d01c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_10, + .freq_tbl =3D ftbl_gcc_qdss_tsctr_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_tsctr_clk_src", + .parent_data =3D gcc_parent_data_10, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x31004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcnoc_bfdcd_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcnoc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + /* + * There are no consumers for this source in kernel yet, + * (will be added soon), so the clock framework + * disables this source. But some of the clocks + * initialized by boot loaders uses this source. So we + * need to keep this clock ON. Add the + * CLK_IGNORE_UNUSED flag so the clock will not be + * disabled. Once the consumer in kernel is added, we + * can get rid of this flag. + */ + .flags =3D CLK_IS_CRITICAL, + }, +}; + +static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qpic_io_macro_clk_src =3D { + .cmd_rcgr =3D 0x32004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_12, + .freq_tbl =3D ftbl_gcc_qpic_io_macro_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_io_macro_clk_src", + .parent_data =3D gcc_parent_data_12, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_12), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qpic_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qpic_clk_src =3D { + .cmd_rcgr =3D 0x32020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_12, + .freq_tbl =3D ftbl_gcc_qpic_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_clk_src", + .parent_data =3D gcc_parent_data_12, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_12), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pon_tm2x_clk_src[] =3D { + F(342860000, P_GPLL4_OUT_MAIN, 3.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pon_tm2x_clk_src =3D { + .cmd_rcgr =3D 0x3c004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_11, + .freq_tbl =3D ftbl_gcc_pon_tm2x_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pon_tm2x_clk_src", + .parent_data =3D gcc_parent_data_11, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_11), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x3400c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_13, + .freq_tbl =3D ftbl_gcc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sleep_clk_src", + .parent_data =3D gcc_parent_data_13, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_13), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] =3D { + F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_lpass_sway_clk_src =3D { + .cmd_rcgr =3D 0x27004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_lpass_sway_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_lpass_sway_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_lpass_axim_clk_src =3D { + .cmd_rcgr =3D 0x2700c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_lpass_sway_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_lpass_axim_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gcc_nssnoc_memnoc_div_clk_src =3D { + .reg =3D 0x1700c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src =3D { + .reg =3D 0x2c040, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_fixed_factor gcc_pon_tm_div_clk_src =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pon_tm_div_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pon_tm2x_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_branch gcc_adss_pwm_clk =3D { + .halt_reg =3D 0x1c00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1c00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_adss_pwm_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_adss_pwm_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_pcie0_1lane_s_clk =3D { + .halt_reg =3D 0x31088, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x31088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_pcie0_1lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_pcie1_2lane_s_clk =3D { + .halt_reg =3D 0x3108c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3108c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_pcie1_2lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_usb_clk =3D { + .halt_reg =3D 0x310a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x310a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_usb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdio_ahb_clk =3D { + .halt_reg =3D 0x17040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_mdio_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdio_gephy_ahb_clk =3D { + .halt_reg =3D 0x17098, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17098, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_mdio_gephy_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_ts_clk =3D { + .halt_reg =3D 0x17018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nss_ts_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nss_ts_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nsscc_clk =3D { + .halt_reg =3D 0x17034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nsscc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nsscfg_clk =3D { + .halt_reg =3D 0x1702c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1702c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nsscfg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_atb_clk =3D { + .halt_reg =3D 0x17014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_atb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_at_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_memnoc_1_clk =3D { + .halt_reg =3D 0x17084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_memnoc_clk =3D { + .halt_reg =3D 0x17024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_nsscc_clk =3D { + .halt_reg =3D 0x17030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_nsscc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_rcg2 gcc_xo_clk_src =3D { + .cmd_rcgr =3D 0x34004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_xo, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_xo_clk_src", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor gcc_xo_div4_clk_src =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_xo_div4_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_xo_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_branch gcc_gephy_sys_clk =3D { + .halt_reg =3D 0x2a004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gephy_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_pcnoc_1_clk =3D { + .halt_reg =3D 0x17080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_pcnoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_qosgen_ref_clk =3D { + .halt_reg =3D 0x1701c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1701c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_qosgen_ref_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &gcc_xo_div4_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_snoc_1_clk =3D { + .halt_reg =3D 0x1707c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1707c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_snoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_system_noc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_snoc_clk =3D { + .halt_reg =3D 0x17028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_snoc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_system_noc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_timeout_ref_clk =3D { + .halt_reg =3D 0x17020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_timeout_ref_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_xo_div4_clk_src.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_xo_dcd_clk =3D { + .halt_reg =3D 0x17074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_xo_dcd_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_ahb_clk =3D { + .halt_reg =3D 0x28030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_aux_clk =3D { + .halt_reg =3D 0x28070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_m_clk =3D { + .halt_reg =3D 0x28038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_bridge_clk =3D { + .halt_reg =3D 0x28048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_clk =3D { + .halt_reg =3D 0x28040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src =3D { + .reg =3D 0x28064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie0_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY0_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_pipe_clk =3D { + .halt_reg =3D 0x28068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x28068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie0_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_ahb_clk =3D { + .halt_reg =3D 0x29030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_aux_clk =3D { + .halt_reg =3D 0x29074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_m_clk =3D { + .halt_reg =3D 0x29038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_s_bridge_clk =3D { + .halt_reg =3D 0x29048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_s_clk =3D { + .halt_reg =3D 0x29040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src =3D { + .reg =3D 0x29064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie1_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY1_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_pipe_clk =3D { + .halt_reg =3D 0x29068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x29068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie1_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qrng_ahb_clk =3D { + .halt_reg =3D 0x13024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qrng_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_ahb_mst_clk =3D { + .halt_reg =3D 0x1014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_ahb_mst_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_ahb_slv_clk =3D { + .halt_reg =3D 0x102c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_ahb_slv_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se0_clk =3D { + .halt_reg =3D 0x4020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se1_clk =3D { + .halt_reg =3D 0x5020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se2_clk =3D { + .halt_reg =3D 0x202c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x202c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se3_clk =3D { + .halt_reg =3D 0x2048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se4_clk =3D { + .halt_reg =3D 0x302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se5_clk =3D { + .halt_reg =3D 0x3048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x3303c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3303c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x3302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0x33034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x33034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_pcie0_axi_m_clk =3D { + .halt_reg =3D 0x2e04c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e04c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_pcie0_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_pcie1_axi_m_clk =3D { + .halt_reg =3D 0x2e050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_pcie1_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_ahb_clk =3D { + .halt_reg =3D 0x1704c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1704c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_sys_clk =3D { + .halt_reg =3D 0x17048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy0_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_ahb_clk =3D { + .halt_reg =3D 0x1705c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1705c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_sys_clk =3D { + .halt_reg =3D 0x17058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy1_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy2_ahb_clk =3D { + .halt_reg =3D 0x1706c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1706c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy2_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy2_sys_clk =3D { + .halt_reg =3D 0x17068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy2_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_aux_clk =3D { + .halt_reg =3D 0x2c04c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c04c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_master_clk =3D { + .halt_reg =3D 0x2c044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_mock_utmi_clk =3D { + .halt_reg =3D 0x2c050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_mock_utmi_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_phy_cfg_ahb_clk =3D { + .halt_reg =3D 0x2c05c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c05c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_phy_cfg_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src =3D { + .reg =3D 0x2c074, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_USB3_PHY0_CC_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_pipe_clk =3D { + .halt_reg =3D 0x2c054, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2c054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_usb0_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_sleep_clk =3D { + .halt_reg =3D 0x2c058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_rchng_clk =3D { + .halt_reg =3D 0x28028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie0_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_rchng_clk =3D { + .halt_reg =3D 0x29028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie1_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_ahb_clk =3D { + .halt_reg =3D 0x32010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_clk =3D { + .halt_reg =3D 0x32028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qpic_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_io_macro_clk =3D { + .halt_reg =3D 0x3200c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3200c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_io_macro_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qpic_io_macro_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_12gpll_ahb_clk =3D { + .halt_reg =3D 0x3a004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cmn_12gpll_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_12gpll_sys_clk =3D { + .halt_reg =3D 0x3a008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3a008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cmn_12gpll_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_at_clk =3D { + .halt_reg =3D 0x2d034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2d034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_at_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_at_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_dap_clk =3D { + .halt_reg =3D 0x2d058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_dap_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_tsctr_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pon_apb_clk =3D { + .halt_reg =3D 0x3c01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pon_apb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pon_tm_clk =3D { + .halt_reg =3D 0x3c014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pon_tm_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pon_tm_div_clk_src.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pon_tm2x_clk =3D { + .halt_reg =3D 0x3c00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pon_tm2x_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pon_tm2x_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_lpass_clk =3D { + .halt_reg =3D 0x2e028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_lpass_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_lpass_axim_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_sway_clk =3D { + .halt_reg =3D 0x27014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x27014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_lpass_sway_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_lpass_sway_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_lpass_cfg_clk =3D { + .halt_reg =3D 0x31020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x31020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_lpass_cfg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_lpass_sway_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_core_axim_clk =3D { + .halt_reg =3D 0x27018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x27018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_lpass_core_axim_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_lpass_axim_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static __maybe_unused struct clk_regmap *gcc_ipq5210_clocks[] =3D { + [GCC_ADSS_PWM_CLK] =3D &gcc_adss_pwm_clk.clkr, + [GCC_ADSS_PWM_CLK_SRC] =3D &gcc_adss_pwm_clk_src.clkr, + [GCC_CMN_12GPLL_AHB_CLK] =3D &gcc_cmn_12gpll_ahb_clk.clkr, + [GCC_CMN_12GPLL_SYS_CLK] =3D &gcc_cmn_12gpll_sys_clk.clkr, + [GCC_CNOC_LPASS_CFG_CLK] =3D &gcc_cnoc_lpass_cfg_clk.clkr, + [GCC_CNOC_PCIE0_1LANE_S_CLK] =3D &gcc_cnoc_pcie0_1lane_s_clk.clkr, + [GCC_CNOC_PCIE1_2LANE_S_CLK] =3D &gcc_cnoc_pcie1_2lane_s_clk.clkr, + [GCC_CNOC_USB_CLK] =3D &gcc_cnoc_usb_clk.clkr, + [GCC_GEPHY_SYS_CLK] =3D &gcc_gephy_sys_clk.clkr, + [GCC_LPASS_AXIM_CLK_SRC] =3D &gcc_lpass_axim_clk_src.clkr, + [GCC_LPASS_CORE_AXIM_CLK] =3D &gcc_lpass_core_axim_clk.clkr, + [GCC_LPASS_SWAY_CLK] =3D &gcc_lpass_sway_clk.clkr, + [GCC_LPASS_SWAY_CLK_SRC] =3D &gcc_lpass_sway_clk_src.clkr, + [GCC_MDIO_AHB_CLK] =3D &gcc_mdio_ahb_clk.clkr, + [GCC_MDIO_GEPHY_AHB_CLK] =3D &gcc_mdio_gephy_ahb_clk.clkr, + [GCC_NSS_TS_CLK] =3D &gcc_nss_ts_clk.clkr, + [GCC_NSS_TS_CLK_SRC] =3D &gcc_nss_ts_clk_src.clkr, + [GCC_NSSCC_CLK] =3D &gcc_nsscc_clk.clkr, + [GCC_NSSCFG_CLK] =3D &gcc_nsscfg_clk.clkr, + [GCC_NSSNOC_ATB_CLK] =3D &gcc_nssnoc_atb_clk.clkr, + [GCC_NSSNOC_MEMNOC_1_CLK] =3D &gcc_nssnoc_memnoc_1_clk.clkr, + [GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC] =3D &gcc_nssnoc_memnoc_bfdcd_clk_src.cl= kr, + [GCC_NSSNOC_MEMNOC_CLK] =3D &gcc_nssnoc_memnoc_clk.clkr, + [GCC_NSSNOC_MEMNOC_DIV_CLK_SRC] =3D &gcc_nssnoc_memnoc_div_clk_src.clkr, + [GCC_NSSNOC_NSSCC_CLK] =3D &gcc_nssnoc_nsscc_clk.clkr, + [GCC_NSSNOC_PCNOC_1_CLK] =3D &gcc_nssnoc_pcnoc_1_clk.clkr, + [GCC_NSSNOC_QOSGEN_REF_CLK] =3D &gcc_nssnoc_qosgen_ref_clk.clkr, + [GCC_NSSNOC_SNOC_1_CLK] =3D &gcc_nssnoc_snoc_1_clk.clkr, + [GCC_NSSNOC_SNOC_CLK] =3D &gcc_nssnoc_snoc_clk.clkr, + [GCC_NSSNOC_TIMEOUT_REF_CLK] =3D &gcc_nssnoc_timeout_ref_clk.clkr, + [GCC_NSSNOC_XO_DCD_CLK] =3D &gcc_nssnoc_xo_dcd_clk.clkr, + [GCC_PCIE0_AHB_CLK] =3D &gcc_pcie0_ahb_clk.clkr, + [GCC_PCIE0_AUX_CLK] =3D &gcc_pcie0_aux_clk.clkr, + [GCC_PCIE0_AXI_M_CLK] =3D &gcc_pcie0_axi_m_clk.clkr, + [GCC_PCIE0_AXI_M_CLK_SRC] =3D &gcc_pcie0_axi_m_clk_src.clkr, + [GCC_PCIE0_AXI_S_BRIDGE_CLK] =3D &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_PCIE0_AXI_S_CLK] =3D &gcc_pcie0_axi_s_clk.clkr, + [GCC_PCIE0_AXI_S_CLK_SRC] =3D &gcc_pcie0_axi_s_clk_src.clkr, + [GCC_PCIE0_PIPE_CLK] =3D &gcc_pcie0_pipe_clk.clkr, + [GCC_PCIE0_PIPE_CLK_SRC] =3D &gcc_pcie0_pipe_clk_src.clkr, + [GCC_PCIE0_RCHNG_CLK] =3D &gcc_pcie0_rchng_clk.clkr, + [GCC_PCIE0_RCHNG_CLK_SRC] =3D &gcc_pcie0_rchng_clk_src.clkr, + [GCC_PCIE1_AHB_CLK] =3D &gcc_pcie1_ahb_clk.clkr, + [GCC_PCIE1_AUX_CLK] =3D &gcc_pcie1_aux_clk.clkr, + [GCC_PCIE1_AXI_M_CLK] =3D &gcc_pcie1_axi_m_clk.clkr, + [GCC_PCIE1_AXI_M_CLK_SRC] =3D &gcc_pcie1_axi_m_clk_src.clkr, + [GCC_PCIE1_AXI_S_BRIDGE_CLK] =3D &gcc_pcie1_axi_s_bridge_clk.clkr, + [GCC_PCIE1_AXI_S_CLK] =3D &gcc_pcie1_axi_s_clk.clkr, + [GCC_PCIE1_AXI_S_CLK_SRC] =3D &gcc_pcie1_axi_s_clk_src.clkr, + [GCC_PCIE1_PIPE_CLK] =3D &gcc_pcie1_pipe_clk.clkr, + [GCC_PCIE1_PIPE_CLK_SRC] =3D &gcc_pcie1_pipe_clk_src.clkr, + [GCC_PCIE1_RCHNG_CLK] =3D &gcc_pcie1_rchng_clk.clkr, + [GCC_PCIE1_RCHNG_CLK_SRC] =3D &gcc_pcie1_rchng_clk_src.clkr, + [GCC_PCIE_AUX_CLK_SRC] =3D &gcc_pcie_aux_clk_src.clkr, + [GCC_PCNOC_BFDCD_CLK_SRC] =3D &gcc_pcnoc_bfdcd_clk_src.clkr, + [GCC_PON_APB_CLK] =3D &gcc_pon_apb_clk.clkr, + [GCC_PON_TM_CLK] =3D &gcc_pon_tm_clk.clkr, + [GCC_PON_TM2X_CLK] =3D &gcc_pon_tm2x_clk.clkr, + [GCC_PON_TM2X_CLK_SRC] =3D &gcc_pon_tm2x_clk_src.clkr, + [GCC_QDSS_AT_CLK] =3D &gcc_qdss_at_clk.clkr, + [GCC_QDSS_AT_CLK_SRC] =3D &gcc_qdss_at_clk_src.clkr, + [GCC_QDSS_DAP_CLK] =3D &gcc_qdss_dap_clk.clkr, + [GCC_QDSS_TSCTR_CLK_SRC] =3D &gcc_qdss_tsctr_clk_src.clkr, + [GCC_QPIC_AHB_CLK] =3D &gcc_qpic_ahb_clk.clkr, + [GCC_QPIC_CLK] =3D &gcc_qpic_clk.clkr, + [GCC_QPIC_CLK_SRC] =3D &gcc_qpic_clk_src.clkr, + [GCC_QPIC_IO_MACRO_CLK] =3D &gcc_qpic_io_macro_clk.clkr, + [GCC_QPIC_IO_MACRO_CLK_SRC] =3D &gcc_qpic_io_macro_clk_src.clkr, + [GCC_QRNG_AHB_CLK] =3D &gcc_qrng_ahb_clk.clkr, + [GCC_QUPV3_AHB_MST_CLK] =3D &gcc_qupv3_ahb_mst_clk.clkr, + [GCC_QUPV3_AHB_SLV_CLK] =3D &gcc_qupv3_ahb_slv_clk.clkr, + [GCC_QUPV3_WRAP_SE0_CLK] =3D &gcc_qupv3_wrap_se0_clk.clkr, + [GCC_QUPV3_WRAP_SE0_CLK_SRC] =3D &gcc_qupv3_wrap_se0_clk_src.clkr, + [GCC_QUPV3_WRAP_SE1_CLK] =3D &gcc_qupv3_wrap_se1_clk.clkr, + [GCC_QUPV3_WRAP_SE1_CLK_SRC] =3D &gcc_qupv3_wrap_se1_clk_src.clkr, + [GCC_QUPV3_WRAP_SE2_CLK] =3D &gcc_qupv3_wrap_se2_clk.clkr, + [GCC_QUPV3_WRAP_SE2_CLK_SRC] =3D &gcc_qupv3_wrap_se2_clk_src.clkr, + [GCC_QUPV3_WRAP_SE3_CLK] =3D &gcc_qupv3_wrap_se3_clk.clkr, + [GCC_QUPV3_WRAP_SE3_CLK_SRC] =3D &gcc_qupv3_wrap_se3_clk_src.clkr, + [GCC_QUPV3_WRAP_SE4_CLK] =3D &gcc_qupv3_wrap_se4_clk.clkr, + [GCC_QUPV3_WRAP_SE4_CLK_SRC] =3D &gcc_qupv3_wrap_se4_clk_src.clkr, + [GCC_QUPV3_WRAP_SE5_CLK] =3D &gcc_qupv3_wrap_se5_clk.clkr, + [GCC_QUPV3_WRAP_SE5_CLK_SRC] =3D &gcc_qupv3_wrap_se5_clk_src.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] =3D &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] =3D &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SLEEP_CLK_SRC] =3D &gcc_sleep_clk_src.clkr, + [GCC_SNOC_LPASS_CLK] =3D &gcc_snoc_lpass_clk.clkr, + [GCC_SNOC_PCIE0_AXI_M_CLK] =3D &gcc_snoc_pcie0_axi_m_clk.clkr, + [GCC_SNOC_PCIE1_AXI_M_CLK] =3D &gcc_snoc_pcie1_axi_m_clk.clkr, + [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] =3D &gcc_system_noc_bfdcd_clk_src.clkr, + [GCC_UNIPHY0_AHB_CLK] =3D &gcc_uniphy0_ahb_clk.clkr, + [GCC_UNIPHY0_SYS_CLK] =3D &gcc_uniphy0_sys_clk.clkr, + [GCC_UNIPHY1_AHB_CLK] =3D &gcc_uniphy1_ahb_clk.clkr, + [GCC_UNIPHY1_SYS_CLK] =3D &gcc_uniphy1_sys_clk.clkr, + [GCC_UNIPHY2_AHB_CLK] =3D &gcc_uniphy2_ahb_clk.clkr, + [GCC_UNIPHY2_SYS_CLK] =3D &gcc_uniphy2_sys_clk.clkr, + [GCC_UNIPHY_SYS_CLK_SRC] =3D &gcc_uniphy_sys_clk_src.clkr, + [GCC_USB0_AUX_CLK] =3D &gcc_usb0_aux_clk.clkr, + [GCC_USB0_AUX_CLK_SRC] =3D &gcc_usb0_aux_clk_src.clkr, + [GCC_USB0_MASTER_CLK] =3D &gcc_usb0_master_clk.clkr, + [GCC_USB0_MASTER_CLK_SRC] =3D &gcc_usb0_master_clk_src.clkr, + [GCC_USB0_MOCK_UTMI_CLK] =3D &gcc_usb0_mock_utmi_clk.clkr, + [GCC_USB0_MOCK_UTMI_CLK_SRC] =3D &gcc_usb0_mock_utmi_clk_src.clkr, + [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] =3D &gcc_usb0_mock_utmi_div_clk_src.clkr, + [GCC_USB0_PHY_CFG_AHB_CLK] =3D &gcc_usb0_phy_cfg_ahb_clk.clkr, + [GCC_USB0_PIPE_CLK] =3D &gcc_usb0_pipe_clk.clkr, + [GCC_USB0_PIPE_CLK_SRC] =3D &gcc_usb0_pipe_clk_src.clkr, + [GCC_USB0_SLEEP_CLK] =3D &gcc_usb0_sleep_clk.clkr, + [GCC_XO_CLK_SRC] =3D &gcc_xo_clk_src.clkr, + [GPLL0_MAIN] =3D &gpll0_main.clkr, + [GPLL0] =3D &gpll0.clkr, + [GPLL2_MAIN] =3D &gpll2_main.clkr, + [GPLL2] =3D &gpll2.clkr, + [GPLL4_MAIN] =3D &gpll4_main.clkr, +}; + +static const struct qcom_reset_map gcc_ipq5210_resets[] =3D { + [GCC_ADSS_BCR] =3D { 0x1c000 }, + [GCC_ADSS_PWM_ARES] =3D { 0x1c00c, 2 }, + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] =3D { 0x38000 }, + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES] =3D { 0x3800c, 2 }, + [GCC_APSS_AHB_ARES] =3D { 0x24014, 2 }, + [GCC_APSS_ATB_ARES] =3D { 0x24034, 2 }, + [GCC_APSS_AXI_ARES] =3D { 0x24018, 2 }, + [GCC_APSS_TS_ARES] =3D { 0x24030, 2 }, + [GCC_BOOT_ROM_AHB_ARES] =3D { 0x1302c, 2 }, + [GCC_BOOT_ROM_BCR] =3D { 0x13028 }, + [GCC_GEPHY_BCR] =3D { 0x2a000 }, + [GCC_GEPHY_SYS_ARES] =3D { 0x2a004, 2 }, + [GCC_GP1_ARES] =3D { 0x8018, 2 }, + [GCC_GP2_ARES] =3D { 0x9018, 2 }, + [GCC_GP3_ARES] =3D { 0xa018, 2 }, + [GCC_MDIO_AHB_ARES] =3D { 0x17040, 2 }, + [GCC_MDIO_BCR] =3D { 0x1703c }, + [GCC_MDIO_GEPHY_AHB_ARES] =3D { 0x17098, 2 }, + [GCC_NSS_BCR] =3D { 0x17000 }, + [GCC_NSS_TS_ARES] =3D { 0x17018, 2 }, + [GCC_NSSCC_ARES] =3D { 0x17034, 2 }, + [GCC_NSSCFG_ARES] =3D { 0x1702c, 2 }, + [GCC_NSSNOC_ATB_ARES] =3D { 0x17014, 2 }, + [GCC_NSSNOC_MEMNOC_1_ARES] =3D { 0x17084, 2 }, + [GCC_NSSNOC_MEMNOC_ARES] =3D { 0x17024, 2 }, + [GCC_NSSNOC_NSSCC_ARES] =3D { 0x17030, 2 }, + [GCC_NSSNOC_PCNOC_1_ARES] =3D { 0x17080, 2 }, + [GCC_NSSNOC_QOSGEN_REF_ARES] =3D { 0x1701c, 2 }, + [GCC_NSSNOC_SNOC_1_ARES] =3D { 0x1707c, 2 }, + [GCC_NSSNOC_SNOC_ARES] =3D { 0x17028, 2 }, + [GCC_NSSNOC_TIMEOUT_REF_ARES] =3D { 0x17020, 2 }, + [GCC_NSSNOC_XO_DCD_ARES] =3D { 0x17074, 2 }, + [GCC_PCIE0_AHB_ARES] =3D { 0x28030, 2 }, + [GCC_PCIE0_AUX_ARES] =3D { 0x28070, 2 }, + [GCC_PCIE0_AXI_M_ARES] =3D { 0x28038, 2 }, + [GCC_PCIE0_AXI_S_BRIDGE_ARES] =3D { 0x28048, 2 }, + [GCC_PCIE0_AXI_S_ARES] =3D { 0x28040, 2 }, + [GCC_PCIE0_BCR] =3D { 0x28000 }, + [GCC_PCIE0_LINK_DOWN_BCR] =3D { 0x28054 }, + [GCC_PCIE0_PIPE_RESET] =3D { 0x28058, 0 }, + [GCC_PCIE0_CORE_STICKY_RESET] =3D { 0x28058, 1 }, + [GCC_PCIE0_AXI_S_STICKY_RESET] =3D { 0x28058, 2 }, + [GCC_PCIE0_AXI_S_RESET] =3D { 0x28058, 3 }, + [GCC_PCIE0_AXI_M_STICKY_RESET] =3D { 0x28058, 4 }, + [GCC_PCIE0_AXI_M_RESET] =3D { 0x28058, 5 }, + [GCC_PCIE0_AUX_RESET] =3D { 0x28058, 6 }, + [GCC_PCIE0_AHB_RESET] =3D { 0x28058, 7 }, + [GCC_PCIE0_PHY_BCR] =3D { 0x28060 }, + [GCC_PCIE0_PIPE_ARES] =3D { 0x28068, 2 }, + [GCC_PCIE0PHY_PHY_BCR] =3D { 0x2805c }, + [GCC_PCIE1_AHB_ARES] =3D { 0x29030, 2 }, + [GCC_PCIE1_AUX_ARES] =3D { 0x29074, 2 }, + [GCC_PCIE1_AXI_M_ARES] =3D { 0x29038, 2 }, + [GCC_PCIE1_AXI_S_BRIDGE_ARES] =3D { 0x29048, 2 }, + [GCC_PCIE1_AXI_S_ARES] =3D { 0x29040, 2 }, + [GCC_PCIE1_BCR] =3D { 0x29000 }, + [GCC_PCIE1_LINK_DOWN_BCR] =3D { 0x29054 }, + [GCC_PCIE1_PIPE_RESET] =3D { 0x29058, 0 }, + [GCC_PCIE1_CORE_STICKY_RESET] =3D { 0x29058, 1 }, + [GCC_PCIE1_AXI_S_STICKY_RESET] =3D { 0x29058, 2 }, + [GCC_PCIE1_AXI_S_RESET] =3D { 0x29058, 3 }, + [GCC_PCIE1_AXI_M_STICKY_RESET] =3D { 0x29058, 4 }, + [GCC_PCIE1_AXI_M_RESET] =3D { 0x29058, 5 }, + [GCC_PCIE1_AUX_RESET] =3D { 0x29058, 6 }, + [GCC_PCIE1_AHB_RESET] =3D { 0x29058, 7 }, + [GCC_PCIE1_PHY_BCR] =3D { 0x29060 }, + [GCC_PCIE1_PIPE_ARES] =3D { 0x29068, 2 }, + [GCC_PCIE1PHY_PHY_BCR] =3D { 0x2905c }, + [GCC_QRNG_AHB_ARES] =3D { 0x13024, 2 }, + [GCC_QRNG_BCR] =3D { 0x13020 }, + [GCC_QUPV3_2X_CORE_ARES] =3D { 0x1020, 2 }, + [GCC_QUPV3_AHB_MST_ARES] =3D { 0x1014, 2 }, + [GCC_QUPV3_AHB_SLV_ARES] =3D { 0x102c, 2 }, + [GCC_QUPV3_BCR] =3D { 0x1000 }, + [GCC_QUPV3_CORE_ARES] =3D { 0x1018, 2 }, + [GCC_QUPV3_WRAP_SE0_ARES] =3D { 0x4020, 2 }, + [GCC_QUPV3_WRAP_SE0_BCR] =3D { 0x4000 }, + [GCC_QUPV3_WRAP_SE1_ARES] =3D { 0x5020, 2 }, + [GCC_QUPV3_WRAP_SE1_BCR] =3D { 0x5000 }, + [GCC_QUPV3_WRAP_SE2_ARES] =3D { 0x202c, 2 }, + [GCC_QUPV3_WRAP_SE2_BCR] =3D { 0x2000 }, + [GCC_QUPV3_WRAP_SE3_ARES] =3D { 0x2048, 2 }, + [GCC_QUPV3_WRAP_SE3_BCR] =3D { 0x2030 }, + [GCC_QUPV3_WRAP_SE4_ARES] =3D { 0x302c, 2 }, + [GCC_QUPV3_WRAP_SE4_BCR] =3D { 0x3000 }, + [GCC_QUPV3_WRAP_SE5_ARES] =3D { 0x3048, 2 }, + [GCC_QUPV3_WRAP_SE5_BCR] =3D { 0x3030 }, + [GCC_QUSB2_0_PHY_BCR] =3D { 0x2c068 }, + [GCC_SDCC1_AHB_ARES] =3D { 0x3303c, 2 }, + [GCC_SDCC1_APPS_ARES] =3D { 0x3302c, 2 }, + [GCC_SDCC1_ICE_CORE_ARES] =3D { 0x33034, 2 }, + [GCC_SDCC_BCR] =3D { 0x33000 }, + [GCC_TLMM_AHB_ARES] =3D { 0x3e004, 2 }, + [GCC_TLMM_ARES] =3D { 0x3e008, 2 }, + [GCC_TLMM_BCR] =3D { 0x3e000 }, + [GCC_UNIPHY0_AHB_ARES] =3D { 0x1704c, 2 }, + [GCC_UNIPHY0_BCR] =3D { 0x17044 }, + [GCC_UNIPHY0_SYS_ARES] =3D { 0x17048, 2 }, + [GCC_UNIPHY1_AHB_ARES] =3D { 0x1705c, 2 }, + [GCC_UNIPHY1_BCR] =3D { 0x17054 }, + [GCC_UNIPHY1_SYS_ARES] =3D { 0x17058, 2 }, + [GCC_UNIPHY2_AHB_ARES] =3D { 0x1706c, 2 }, + [GCC_UNIPHY2_BCR] =3D { 0x17064 }, + [GCC_UNIPHY2_SYS_ARES] =3D { 0x17068, 2 }, + [GCC_USB0_AUX_ARES] =3D { 0x2c04c, 2 }, + [GCC_USB0_MASTER_ARES] =3D { 0x2c044, 2 }, + [GCC_USB0_MOCK_UTMI_ARES] =3D { 0x2c050, 2 }, + [GCC_USB0_PHY_BCR] =3D { 0x2c06c }, + [GCC_USB0_PHY_CFG_AHB_ARES] =3D { 0x2c05c, 2 }, + [GCC_USB0_PIPE_ARES] =3D { 0x2c054, 2 }, + [GCC_USB0_SLEEP_ARES] =3D { 0x2c058, 2 }, + [GCC_USB3PHY_0_PHY_BCR] =3D { 0x2c070 }, + [GCC_USB_BCR] =3D { 0x2c000 }, + [GCC_QDSS_BCR] =3D { 0x2d000 }, +}; + +static const struct of_device_id gcc_ipq5210_match_table[] =3D { + { .compatible =3D "qcom,ipq5210-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_ipq5210_match_table); + +static const struct regmap_config gcc_ipq5210_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3f024, + .fast_io =3D true, +}; + +static struct clk_hw *gcc_ipq5210_hws[] =3D { + &gpll0_div2.hw, + &gcc_xo_div4_clk_src.hw, + &gcc_pon_tm_div_clk_src.hw, +}; + +static const struct qcom_cc_desc gcc_ipq5210_desc =3D { + .config =3D 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Acked-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d054a8f5632d853509b7cd37f07f02473cf6bf71..7a36da412ab82b425479fbf6d81= 293f24e66ea36 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -309,6 +309,11 @@ properties: - tplink,archer-ax55-v1 - const: qcom,ipq5018 =20 + - items: + - enum: + - qcom,ipq5210-rdp504 + - const: qcom,ipq5210 + - items: - enum: - qcom,ipq5332-ap-mi01.2 --=20 2.34.1 From nobody Mon Apr 6 18:56:45 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76886387374 for ; Wed, 18 Mar 2026 08:40:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index d66459f1d84e4d99c7f72415d08bfdaf1d701948..6d9b71a9b9b3fefd1951b963f34= 942243aa48ccb 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -26,6 +26,7 @@ properties: - qcom,scm-glymur - qcom,scm-ipq4019 - qcom,scm-ipq5018 + - qcom,scm-ipq5210 - qcom,scm-ipq5332 - qcom,scm-ipq5424 - qcom,scm-ipq6018 --=20 2.34.1 From nobody Mon Apr 6 18:56:45 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F7A8386573 for ; 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Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 86 ++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 311 ++++++++++++++++++++++++= ++++ 3 files changed, 398 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 02921a495b2cbabcbacc74fbbb99eafe1f6478ac..e7748af640cccffa5c83ec82c37= aa441444c2b13 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -22,6 +22,7 @@ hamoa-iot-evk-el2-dtbs :=3D hamoa-iot-evk.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-tplink-archer-ax55-v1.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5210-rdp504.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts new file mode 100644 index 0000000000000000000000000000000000000000..d4d4ef7948a5a710752da0169ce= 4462592920320 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq5210.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IPQ5210 RDP504"; + compatible =3D "qcom,ipq5210-rdp504", "qcom,ipq5210"; + + aliases { + serial0 =3D &uart1; + }; + + chosen { + stdout-path =3D "serial0"; + }; +}; + +&sdhc { + max-frequency =3D <192000000>; + bus-width =3D <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 =3D <&sdhc_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&tlmm { + qup_uart1_default_state: qup-uart1-default-state { + tx-pins { + pins =3D "gpio39"; + function =3D "qup_se1_l2"; + drive-strength =3D <6>; + bias-pull-down; + }; + + rx-pins { + pins =3D "gpio38"; + function =3D "qup_se1_l3"; + drive-strength =3D <6>; + bias-pull-down; + }; + }; + + sdhc_default_state: sdhc-default-state { + clk-pins { + pins =3D "gpio5"; + function =3D "sdc_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio4"; + function =3D "sdc_cmd"; + drive-strength =3D <8>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "sdc_data"; + drive-strength =3D <8>; + bias-pull-up; + }; + }; +}; + +&uart1 { + pinctrl-0 =3D <&qup_uart1_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&xo_board { + clock-frequency =3D <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..b04bc84ac4521a918f75180d946= 7c8599bdc3d05 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + }; + + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + }; + + cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + }; + + cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + }; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + scm { + compatible =3D "qcom,scm-ipq5210", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + bootloader@87800000 { + reg =3D <0x0 0x87800000 0x0 0x400000>; + no-map; + }; + + smem@87c00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x87c00000 0x0 0x40000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + }; + + tfa@87d00000 { + reg =3D <0x0 0x87d00000 0x0 0x80000>; + no-map; + }; + + optee@87d80000 { + reg =3D <0x0 0x87d80000 0x0 0x280000>; + no-map; + }; + }; + + soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0 0 0 0 0x10 0>; + ranges =3D <0 0 0 0 0x10 0>; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,ipq5210-tlmm"; + reg =3D <0x0 0x01000000 0x0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 54>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,ipq5210-gcc"; + reg =3D <0x0 0x01800000 0x0 0x40000>; + clocks =3D <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01905000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + qupv3: geniqup@1ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x01ac0000 0x0 0x2000>; + clocks =3D <&gcc GCC_QUPV3_AHB_MST_CLK>, + <&gcc GCC_QUPV3_AHB_SLV_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + uart1: serial@1a84000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x01a84000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_SE1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + + status =3D "disabled"; + }; + }; + + sdhc: mmc@7804000 { + compatible =3D "qcom,ipq5210-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>; + reg-names =3D "hc", + "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", + "core", + "xo"; + non-removable; + + status =3D "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0 0xb000000 0x0 0x1000>, /* GICD */ + <0x0 0xb002000 0x0 0x1000>, /* GICC */ + <0x0 0xb001000 0x0 0x1000>, /* GICH */ + <0x0 0xb004000 0x0 0x1000>; /* GICV */ + interrupts =3D ; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0x0b00c000 0 0x3000>; + + v2m0: v2m@0 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x0 0x0 0xffd>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x00001000 0x0 0xffd>; + msi-controller; + }; + + v2m2: v2m@2000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x00002000 0x0 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0xb120000 0x0 0x1000>; + ranges =3D <0 0 0 0x10000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@b121000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x0b123000 0x1000>; + + status =3D "disabled"; + }; + + frame@b124000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x0b124000 0x1000>; + + status =3D "disabled"; + }; + + frame@b125000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x0b125000 0x1000>; + + status =3D "disabled"; + }; + + frame@b126000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x0b126000 0x1000>; + + status =3D "disabled"; + }; + + frame@b127000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x0b127000 0x1000>; + + status =3D "disabled"; + }; + + frame@b128000 { + frame-number =3D <6>; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82a6bbb2802sm1863498b3a.31.2026.03.18.01.40.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 01:40:28 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 18 Mar 2026 14:09:48 +0530 Subject: [PATCH v2 6/6] arm64: defconfig: enable IPQ5210 RDP504 base configs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-ipq5210_boot_to_shell-v2-6-a87e27c37070@oss.qualcomm.com> References: <20260318-ipq5210_boot_to_shell-v2-0-a87e27c37070@oss.qualcomm.com> In-Reply-To: <20260318-ipq5210_boot_to_shell-v2-0-a87e27c37070@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Konrad Dybcio , Robert Marko , Guru Das Srinagesh , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Kathiravan Thirumoorthy , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773823188; l=1056; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=dy2TgZcFr9/VB3bkmaus0Cw/gHd5PPq/I0Ed7LWpshY=; b=6lprkFKodzP4k0sKVzjKf00VbCzbGf50y6WOPChoRVJ34fDSoTqdz3WKbqR382Ul9sxVyiaZR aMiW+5nuamxBRio0eXil4YZ906KsuyUNtmTwVq4BzqYpUJQ93OuLzOW X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDA3MSBTYWx0ZWRfXxguV8lacxAyn 23K+aqOR0N3CAQyHezBkPhDAscWP6BvKtWQtfvHSdDZb3nemECOf0l+f0ZyRuOk6Qu727rJwFaA PwbuLICgs1AGY5UH6mTKVa/yOZ6kzV4EBUmhRkC8wEtiFZjLJM9xJMbJaYq3JTnM4CXBzs4ym+t vEwUYZQIy6UnfqOEBc6WSrmO+y8x2q3qMmiq+4QP9oRP9s6Nqev2oTuIX9Nvax3Vuu525TrQ51Q wEQS7uBaRUSa/mGKWIe5EcR6u5zPy84xaIc4ReXWNO2ZtCbBaeLby4zrVCjXSJDNH96vmzXd2ne NFg76v+3PFjnackDRJqMbG0bYkQWaielOnR1vNcfEOfFUjn+fPVrbTvJOTSpUY4byDlWbAqfkRt lO25swgzAUbXQ30Lx1/5RfWBPle0lktE/TA8nlhm03hbJFrvYvkSTVxetLJJVVaemmR1Y0pHFTR /LrEH2cpdA3KcHSkEBw== X-Authority-Analysis: v=2.4 cv=P8I3RyAu c=1 sm=1 tr=0 ts=69ba64fe cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=Y4Inp1xfyx_JXr0qu3kA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: J80e5tZR_EOCoYXgzAzJNAPXkzFT5PFA X-Proofpoint-GUID: J80e5tZR_EOCoYXgzAzJNAPXkzFT5PFA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_05,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 malwarescore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180071 Enable GCC, Pinctrl for Qualcomm's IPQ5210 SoC which is required to boot ipq5210-rdp504 board to a console shell. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 18881bd239f9c53e74ad5caa492bace394e4fde7..ceec9a109f08f2a2a4f4090e92c= 228279509c3ed 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -649,6 +649,7 @@ CONFIG_PINCTRL_IMX_SCMI=3Dy CONFIG_PINCTRL_MSM=3Dy CONFIG_PINCTRL_GLYMUR=3Dy CONFIG_PINCTRL_IPQ5018=3Dy +CONFIG_PINCTRL_IPQ5210=3Dy CONFIG_PINCTRL_IPQ5332=3Dy CONFIG_PINCTRL_IPQ5424=3Dy CONFIG_PINCTRL_IPQ8074=3Dy @@ -1479,6 +1480,7 @@ CONFIG_IPQ_APSS_6018=3Dy CONFIG_IPQ_APSS_5018=3Dy CONFIG_IPQ_CMN_PLL=3Dm CONFIG_IPQ_GCC_5018=3Dy +CONFIG_IPQ_GCC_5210=3Dy CONFIG_IPQ_GCC_5332=3Dy CONFIG_IPQ_GCC_5424=3Dy CONFIG_IPQ_GCC_6018=3Dy --=20 2.34.1