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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f173a3e3sm226989566b.61.2026.03.18.08.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 08:27:58 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 18 Mar 2026 15:27:46 +0000 Subject: [PATCH v8 01/10] dt-bindings: soc: google: add google,gs101-dtzpc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-gs101-pd-v8-1-241523460b10@linaro.org> References: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> In-Reply-To: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.3 The Exynos Distributed TruztZone Protection Control (D_TZPC) provides an interface to the protection bits that are included in the TrustZone design in a secure system. It configures each area of the memory as secure or non-secure. Reviewed-by: Rob Herring (Arm) Signed-off-by: Andr=C3=A9 Draszik --- .../bindings/soc/google/google,gs101-dtzpc.yaml | 42 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/google/google,gs101-dtzp= c.yaml b/Documentation/devicetree/bindings/soc/google/google,gs101-dtzpc.ya= ml new file mode 100644 index 000000000000..a8c61ce069d6 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/google/google,gs101-dtzpc.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/google/google,gs101-dtzpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Distributed TruztZone Protection Control. + +description: + Distributed TrustZone Protection Control (D_TZPC) provides an interface = to the + protection bits that are included in the TrustZone design in a secure sy= stem. + It configures each area of the memory as secure or non-secure. + +maintainers: + - Andr=C3=A9 Draszik + +properties: + compatible: + const: google,gs101-dtzpc + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - reg + +additionalProperties: false + +examples: + - | + #include + + dtzpc_hsi0: dtzpc@11010000 { + compatible =3D "google,gs101-dtzpc"; + reg =3D <0x11010000 0x10000>; + clocks =3D <&cmu_hsi0 CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 6358dd7f1632..e8376343935f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10905,6 +10905,7 @@ P: Documentation/process/maintainer-soc-clean-dts.r= st C: irc://irc.oftc.net/pixel6-kernel-dev F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml F: Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml +F: Documentation/devicetree/bindings/soc/google/google,gs101-dtzpc.yaml F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.= yaml F: Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml F: arch/arm64/boot/dts/exynos/google/ --=20 2.53.0.851.ga537e3e6e9-goog From nobody Thu Apr 2 00:09:21 2026 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D017D3E121D for ; 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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f173a3e3sm226989566b.61.2026.03.18.08.27.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 08:27:59 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 18 Mar 2026 15:27:47 +0000 Subject: [PATCH v8 02/10] dt-bindings: power: samsung: add google,gs101-pd Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-gs101-pd-v8-2-241523460b10@linaro.org> References: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> In-Reply-To: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.3 Add support for the Google gs101 version of the Exynos power domains. A new compatible is needed because register fields have changed and because power domain operations involve interfacing with the TrustZone protection control on newer Exynos SoCs. Power domains can also have a power supply linked to them, so add optional support for that, too. It is believed that all (existing) platforms could benefit from this, hence it's not being limited to gs101-pd. Reviewed-by: Rob Herring (Arm) Signed-off-by: Andr=C3=A9 Draszik --- v5: - add domain-supply and update commit message v4: - add new vendor property samsung,dtzpc - drop previous tags due to that --- .../devicetree/bindings/power/pd-samsung.yaml | 33 ++++++++++++++++++= ++-- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/power/pd-samsung.yaml b/Docu= mentation/devicetree/bindings/power/pd-samsung.yaml index 9c2c51133457..3f1a2dc17862 100644 --- a/Documentation/devicetree/bindings/power/pd-samsung.yaml +++ b/Documentation/devicetree/bindings/power/pd-samsung.yaml @@ -13,12 +13,10 @@ description: |+ Exynos processors include support for multiple power domains which are u= sed to gate power to one or more peripherals on the processor. =20 -allOf: - - $ref: power-domain.yaml# - properties: compatible: enum: + - google,gs101-pd - samsung,exynos4210-pd - samsung,exynos5433-pd =20 @@ -33,6 +31,9 @@ properties: deprecated: true maxItems: 1 =20 + domain-supply: + description: domain regulator supply. + label: description: Human readable string with domain name. Will be visible in userspace @@ -44,11 +45,28 @@ properties: power-domains: maxItems: 1 =20 + samsung,dtzpc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Distributed TrustZone Protection Control (DTZPC) node. + required: - compatible - "#power-domain-cells" - reg =20 +allOf: + - $ref: power-domain.yaml# + - if: + not: + properties: + compatible: + contains: + const: google,gs101-pd + then: + properties: + samsung,dtzpc: false + unevaluatedProperties: false =20 examples: @@ -66,3 +84,12 @@ examples: #power-domain-cells =3D <0>; label =3D "MFC"; }; + + power-domain@2080 { + compatible =3D "google,gs101-pd"; + reg =3D <0x2080 0x80>; + #power-domain-cells =3D <0>; + label =3D "hsi0"; + domain-supply =3D <&ldo7m>; + samsung,dtzpc =3D <&dtzpc_hsi0>; + }; --=20 2.53.0.851.ga537e3e6e9-goog From nobody Thu Apr 2 00:09:21 2026 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95ABF3E3C50 for ; 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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f173a3e3sm226989566b.61.2026.03.18.08.27.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 08:28:00 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 18 Mar 2026 15:27:48 +0000 Subject: [PATCH v8 03/10] dt-bindings: soc: samsung: exynos-pmu: move gs101-pmu into separate binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-gs101-pd-v8-3-241523460b10@linaro.org> References: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> In-Reply-To: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.3 The gs101-pmu binding is going to acquire various additional (pattern) properties that don't apply to other PMUs supported by this binding. To enable this, move google,gs101-pmu into a separate binding. Reviewed-by: Rob Herring (Arm) Signed-off-by: Andr=C3=A9 Draszik --- v7: - drop invalid tested-by tag (Krzysztof) v4: - update since 'syscon' was removed from gs101-pmu compatibles - update since 'select:' was removed from google,gs101-pmu.yaml v3: - use additionalProperties, not unevaluatedProperties - fix path in $id (Rob) - drop comment around 'select' (Rob) --- .../bindings/soc/google/google,gs101-pmu.yaml | 56 ++++++++++++++++++= ++++ .../bindings/soc/samsung/exynos-pmu.yaml | 20 -------- MAINTAINERS | 1 + 3 files changed, 57 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu.= yaml b/Documentation/devicetree/bindings/soc/google/google,gs101-pmu.yaml new file mode 100644 index 000000000000..a06bd8ec3c20 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/google/google,gs101-pmu.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/google/google,gs101-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 Power Management Unit (PMU) + +maintainers: + - Andr=C3=A9 Draszik + +properties: + compatible: + const: google,gs101-pmu + + reg: + maxItems: 1 + + reboot-mode: + $ref: /schemas/power/reset/syscon-reboot-mode.yaml + type: object + description: + Reboot mode to alter bootloader behavior for the next boot + + syscon-poweroff: + $ref: /schemas/power/reset/syscon-poweroff.yaml# + type: object + description: + Node for power off method + + syscon-reboot: + $ref: /schemas/power/reset/syscon-reboot.yaml# + type: object + description: + Node for reboot method + + google,pmu-intr-gen-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to PMU interrupt generation interface. + +required: + - compatible + - reg + - google,pmu-intr-gen-syscon + +additionalProperties: false + +examples: + - | + system-controller@17460000 { + compatible =3D "google,gs101-pmu"; + reg =3D <0x17460000 0x10000>; + + google,pmu-intr-gen-syscon =3D <&pmu_intr_gen>; + }; diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml = b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 76ce7e98c10f..09368dbb6de6 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -12,8 +12,6 @@ maintainers: properties: compatible: oneOf: - - enum: - - google,gs101-pmu - items: - enum: - samsung,exynos3250-pmu @@ -110,11 +108,6 @@ properties: description: Node for reboot method =20 - google,pmu-intr-gen-syscon: - $ref: /schemas/types.yaml#/definitions/phandle - description: - Phandle to PMU interrupt generation interface. - required: - compatible - reg @@ -176,19 +169,6 @@ allOf: properties: dp-phy: false =20 - - if: - properties: - compatible: - contains: - enum: - - google,gs101-pmu - then: - required: - - google,pmu-intr-gen-syscon - else: - properties: - google,pmu-intr-gen-syscon: false - examples: - | #include diff --git a/MAINTAINERS b/MAINTAINERS index e8376343935f..60da52c420d4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10906,6 +10906,7 @@ C: irc://irc.oftc.net/pixel6-kernel-dev F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml F: Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml F: Documentation/devicetree/bindings/soc/google/google,gs101-dtzpc.yaml +F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu.yaml F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.= yaml F: Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml F: arch/arm64/boot/dts/exynos/google/ --=20 2.53.0.851.ga537e3e6e9-goog From nobody Thu Apr 2 00:09:21 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4162A391831 for ; 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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f173a3e3sm226989566b.61.2026.03.18.08.28.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 08:28:00 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 18 Mar 2026 15:27:49 +0000 Subject: [PATCH v8 04/10] dt-bindings: soc: google: gs101-pmu: allow power domains as children Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-gs101-pd-v8-4-241523460b10@linaro.org> References: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> In-Reply-To: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.3 The power domains are a property of / implemented in the PMU. As such, they should be modelled as child nodes of the PMU. Note: Because the properties added are 'required', this commit breaks DT validation of the existing DT for Pixel 6, but a) that's simply because the DT is incomplete and b) a DT update will be posted once the binding is accepted. It is not possible to write the binding such that it supports old (incomplete) DTs in addition to the full version, but as per above it's not required to keep supporting old DTs. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Rob Herring (Arm) --- v8: - move comment from commit message footer into body (Rob) - fix incorrect use of ranges in example (Rob) v7: - really be consistent with quoting (Krzysztof) - drop invalid tested-by tag (Krzysztof) v4: - consistent quoting using " (Krzysztof) - add samsung,dtzpc to example --- .../bindings/soc/google/google,gs101-pmu.yaml | 41 ++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu.= yaml b/Documentation/devicetree/bindings/soc/google/google,gs101-pmu.yaml index a06bd8ec3c20..52c47252b801 100644 --- a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/google/google,gs101-pmu.yaml @@ -16,6 +16,14 @@ properties: reg: maxItems: 1 =20 + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + reboot-mode: $ref: /schemas/power/reset/syscon-reboot-mode.yaml type: object @@ -39,9 +47,23 @@ properties: description: Phandle to PMU interrupt generation interface. =20 +patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: Child node describing one power domain within the PMU + + additionalProperties: true + + properties: + compatible: + const: google,gs101-pd + required: - compatible - reg + - "#address-cells" + - "#size-cells" + - ranges - google,pmu-intr-gen-syscon =20 additionalProperties: false @@ -51,6 +73,25 @@ examples: system-controller@17460000 { compatible =3D "google,gs101-pmu"; reg =3D <0x17460000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x17460000 0x10000>; =20 google,pmu-intr-gen-syscon =3D <&pmu_intr_gen>; + + pd_g3d: power-domain@1e00 { + compatible =3D "google,gs101-pd"; + reg =3D <0x1e00 0x80>; + #power-domain-cells =3D <0>; + label =3D "g3d"; + samsung,dtzpc =3D <&pd_g3d>; + }; + + power-domain@2000 { + compatible =3D "google,gs101-pd"; + reg =3D <0x2000 0x80>; + #power-domain-cells =3D <0>; + power-domains =3D <&pd_g3d>; + label =3D "embedded_g3d"; + }; }; --=20 2.53.0.851.ga537e3e6e9-goog From nobody Thu Apr 2 00:09:21 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9CEE3E2768 for ; Wed, 18 Mar 2026 15:28:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal: i=1; 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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f173a3e3sm226989566b.61.2026.03.18.08.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 08:28:01 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 18 Mar 2026 15:27:50 +0000 Subject: [PATCH v8 05/10] pmdomain: samsung: convert to using regmap Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-gs101-pd-v8-5-241523460b10@linaro.org> References: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> In-Reply-To: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Marek Szyprowski X-Mailer: b4 0.14.3 On platforms such as Google gs101, direct mmio register access to the PMU registers doesn't necessarily work and access must happen via a regmap created by the PMU driver instead. In preparation for supporting such SoCs convert the existing mmio accesses to using a regmap wrapper. With this change in place, a follow-up patch can update the driver to optionally acquire the PMU-created regmap without having to change the rest of the code. Tested-by: Marek Szyprowski Signed-off-by: Andr=C3=A9 Draszik --- There is one checkpatch warning, relating to the non-const regmap_config. It can not easily be made const at this stage, but a follow-up patch allows us to make it const and the warning will go away anyway. v8: - add missing \n in some of the new log messages v4: - rework the loop in exynos_pd_power() slightly, to not return 0 early to allow more code to be run after pd on/off register write without changing the loop again, required for gs101. - add error message in case first regmap write in exynos_pd_power() fails --- drivers/pmdomain/samsung/exynos-pm-domains.c | 83 +++++++++++++++++++++---= ---- 1 file changed, 62 insertions(+), 21 deletions(-) diff --git a/drivers/pmdomain/samsung/exynos-pm-domains.c b/drivers/pmdomai= n/samsung/exynos-pm-domains.c index 5c3aa8983087..68b1e7ba8729 100644 --- a/drivers/pmdomain/samsung/exynos-pm-domains.c +++ b/drivers/pmdomain/samsung/exynos-pm-domains.c @@ -9,15 +9,14 @@ // conjunction with runtime-pm. Support for both device-tree and non-devic= e-tree // based power domain support is included. =20 -#include #include #include #include #include #include #include -#include #include +#include =20 struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ @@ -28,7 +27,7 @@ struct exynos_pm_domain_config { * Exynos specific wrapper around the generic power domain */ struct exynos_pm_domain { - void __iomem *base; + struct regmap *regmap; struct generic_pm_domain pd; u32 local_pwr_cfg; }; @@ -36,31 +35,42 @@ struct exynos_pm_domain { static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) { struct exynos_pm_domain *pd; - void __iomem *base; u32 timeout, pwr; - char *op; + int err; =20 pd =3D container_of(domain, struct exynos_pm_domain, pd); - base =3D pd->base; =20 pwr =3D power_on ? pd->local_pwr_cfg : 0; - writel_relaxed(pwr, base); + err =3D regmap_write(pd->regmap, 0, pwr); + if (err) { + pr_err("Regmap write for power domain %s %sable failed: %d\n", + domain->name, power_on ? "en" : "dis", err); + return err; + } =20 /* Wait max 1ms */ timeout =3D 10; - - while ((readl_relaxed(base + 0x4) & pd->local_pwr_cfg) !=3D pwr) { - if (!timeout) { - op =3D (power_on) ? "enable" : "disable"; - pr_err("Power domain %s %s failed\n", domain->name, op); - return -ETIMEDOUT; + while (timeout-- > 0) { + unsigned int val; + + err =3D regmap_read(pd->regmap, 0x4, &val); + if (err || ((val & pd->local_pwr_cfg) !=3D pwr)) { + cpu_relax(); + usleep_range(80, 100); + continue; } - timeout--; - cpu_relax(); - usleep_range(80, 100); + + break; } =20 - return 0; + if (!timeout && !err) + /* Only return timeout if no other error also occurred. */ + err =3D -ETIMEDOUT; + if (err) + pr_err("Power domain %s %sable failed: %d\n", domain->name, + power_on ? "en" : "dis", err); + + return err; } =20 static int exynos_pd_power_on(struct generic_pm_domain *domain) @@ -109,8 +119,18 @@ static int exynos_pd_probe(struct platform_device *pde= v) struct device_node *np =3D dev->of_node; struct of_phandle_args child, parent; struct exynos_pm_domain *pd; + struct resource *res; + void __iomem *base; + unsigned int val; int on, ret; =20 + struct regmap_config reg_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .use_relaxed_mmio =3D true, + }; + pm_domain_cfg =3D of_device_get_match_data(dev); pd =3D devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); if (!pd) @@ -120,9 +140,26 @@ static int exynos_pd_probe(struct platform_device *pde= v) if (!pd->pd.name) return -ENOMEM; =20 - pd->base =3D of_iomap(np, 0); - if (!pd->base) - return -ENODEV; + /* + * The resource typically points into the address space of the PMU. + * Therefore, avoid using devm_platform_get_and_ioremap_resource() and + * instead use platform_get_resource() and devm_ioremap() to avoid + * conflicts due to address space overlap. + */ + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return dev_err_probe(dev, -ENXIO, "missing IO resources\n"); + + base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return dev_err_probe(dev, -ENOMEM, + "failed to ioremap PMU regs\n"); + + reg_config.max_register =3D resource_size(res) - reg_config.reg_stride; + pd->regmap =3D devm_regmap_init_mmio(dev, base, ®_config); + if (IS_ERR(pd->regmap)) + return dev_err_probe(dev, PTR_ERR(base), + "failed to init regmap\n"); =20 pd->pd.power_off =3D exynos_pd_power_off; pd->pd.power_on =3D exynos_pd_power_on; @@ -137,7 +174,11 @@ static int exynos_pd_probe(struct platform_device *pde= v) of_device_is_compatible(np, "samsung,exynos4210-pd")) exynos_pd_power_off(&pd->pd); =20 - on =3D readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg; + ret =3D regmap_read(pd->regmap, 0x4, &val); + if (ret) + return dev_err_probe(dev, ret, "failed to read status\n"); + + on =3D val & pd->local_pwr_cfg; =20 pm_genpd_init(&pd->pd, NULL, !on); ret =3D of_genpd_add_provider_simple(np, &pd->pd); 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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f173a3e3sm226989566b.61.2026.03.18.08.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 08:28:01 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 18 Mar 2026 15:27:51 +0000 Subject: [PATCH v8 06/10] pmdomain: samsung: don't hard-code offset for registers to 0 and 4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-gs101-pd-v8-6-241523460b10@linaro.org> References: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> In-Reply-To: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Marek Szyprowski X-Mailer: b4 0.14.3 On platforms such as Google gs101, direct mmio register access to the PMU registers doesn't necessarily work and access must happen via a regmap created by the PMU driver instead. When such a regmap is used it will cover the complete PMU memory region rather than individual power domains. This means the register offsets for the configuration and status registers will have to take the power domain offsets into account, rather than unconditionally hard-coding 0 and 4 respectively. Update the code to allow that. Tested-by: Marek Szyprowski Signed-off-by: Andr=C3=A9 Draszik --- drivers/pmdomain/samsung/exynos-pm-domains.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pmdomain/samsung/exynos-pm-domains.c b/drivers/pmdomai= n/samsung/exynos-pm-domains.c index 68b1e7ba8729..3aba00b9ddef 100644 --- a/drivers/pmdomain/samsung/exynos-pm-domains.c +++ b/drivers/pmdomain/samsung/exynos-pm-domains.c @@ -30,6 +30,8 @@ struct exynos_pm_domain { struct regmap *regmap; struct generic_pm_domain pd; u32 local_pwr_cfg; + u32 configuration_reg; + u32 status_reg; }; =20 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) @@ -41,7 +43,7 @@ static int exynos_pd_power(struct generic_pm_domain *doma= in, bool power_on) pd =3D container_of(domain, struct exynos_pm_domain, pd); =20 pwr =3D power_on ? pd->local_pwr_cfg : 0; - err =3D regmap_write(pd->regmap, 0, pwr); + err =3D regmap_write(pd->regmap, pd->configuration_reg, pwr); if (err) { pr_err("Regmap write for power domain %s %sable failed: %d\n", domain->name, power_on ? "en" : "dis", err); @@ -53,7 +55,7 @@ static int exynos_pd_power(struct generic_pm_domain *doma= in, bool power_on) while (timeout-- > 0) { unsigned int val; =20 - err =3D regmap_read(pd->regmap, 0x4, &val); + err =3D regmap_read(pd->regmap, pd->status_reg, &val); if (err || ((val & pd->local_pwr_cfg) !=3D pwr)) { cpu_relax(); usleep_range(80, 100); @@ -164,6 +166,8 @@ static int exynos_pd_probe(struct platform_device *pdev) pd->pd.power_off =3D exynos_pd_power_off; pd->pd.power_on =3D exynos_pd_power_on; pd->local_pwr_cfg =3D pm_domain_cfg->local_pwr_cfg; + pd->configuration_reg +=3D 0; + pd->status_reg +=3D 4; =20 /* * Some Samsung platforms with bootloaders turning on the splash-screen @@ -174,7 +178,7 @@ static int exynos_pd_probe(struct platform_device *pdev) of_device_is_compatible(np, "samsung,exynos4210-pd")) exynos_pd_power_off(&pd->pd); =20 - ret =3D regmap_read(pd->regmap, 0x4, &val); + ret =3D regmap_read(pd->regmap, pd->status_reg, &val); if (ret) return dev_err_probe(dev, ret, "failed to read status\n"); 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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f173a3e3sm226989566b.61.2026.03.18.08.28.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 08:28:02 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 18 Mar 2026 15:27:52 +0000 Subject: [PATCH v8 07/10] pmdomain: samsung: add support for google,gs101-pd Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-gs101-pd-v8-7-241523460b10@linaro.org> References: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> In-Reply-To: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Marek Szyprowski X-Mailer: b4 0.14.3 On Google gs101, direct mmio register access to the PMU registers doesn't work and access must happen via a regmap created by the PMU driver instead. Add a flag to the device match data to denote this case, and obtain the regmap using the parent node in DT if true, while keeping to use the traditional direct mmio regmap otherwise. Additionally, the status is just one bit on gs101. Tested-by: Marek Szyprowski Signed-off-by: Andr=C3=A9 Draszik --- v8: - Update offset calculation into parent regmap. DT's ranges property now properly denotes PD address space to be an offset into parent node. Change code to account for that and subtract parent start address to get the offset back. v4: - add 'use_parent_regmap' flag instead of going by 'syscon' compatible in parent, as it's not a given that the parent provides a syscon- compatible regmap (it actually doesn't anymore after recent changes on gs101) I've still kept Marek's Tested-by from v3, as legacy Exynos code doesn't change. We need the offset as we use the parent's regmap. --- drivers/pmdomain/samsung/exynos-pm-domains.c | 74 ++++++++++++++++++++----= ---- 1 file changed, 54 insertions(+), 20 deletions(-) diff --git a/drivers/pmdomain/samsung/exynos-pm-domains.c b/drivers/pmdomai= n/samsung/exynos-pm-domains.c index 3aba00b9ddef..f8c0d11e9b33 100644 --- a/drivers/pmdomain/samsung/exynos-pm-domains.c +++ b/drivers/pmdomain/samsung/exynos-pm-domains.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -21,6 +22,7 @@ struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ u32 local_pwr_cfg; + bool use_parent_regmap; }; =20 /* @@ -93,8 +95,16 @@ static const struct exynos_pm_domain_config exynos5433_c= fg =3D { .local_pwr_cfg =3D 0xf, }; =20 +static const struct exynos_pm_domain_config gs101_cfg =3D { + .local_pwr_cfg =3D BIT(0), + .use_parent_regmap =3D true, +}; + static const struct of_device_id exynos_pm_domain_of_match[] =3D { { + .compatible =3D "google,gs101-pd", + .data =3D &gs101_cfg, + }, { .compatible =3D "samsung,exynos4210-pd", .data =3D &exynos4210_cfg, }, { @@ -122,17 +132,9 @@ static int exynos_pd_probe(struct platform_device *pde= v) struct of_phandle_args child, parent; struct exynos_pm_domain *pd; struct resource *res; - void __iomem *base; unsigned int val; int on, ret; =20 - struct regmap_config reg_config =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .use_relaxed_mmio =3D true, - }; - pm_domain_cfg =3D of_device_get_match_data(dev); pd =3D devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); if (!pd) @@ -143,25 +145,57 @@ static int exynos_pd_probe(struct platform_device *pd= ev) return -ENOMEM; =20 /* - * The resource typically points into the address space of the PMU. + * The resource typically points into the address space of the PMU and + * we have to consider two cases: + * 1) some implementations require a custom regmap (from PMU parent) + * 2) this driver might map the same addresses as the PMU driver * Therefore, avoid using devm_platform_get_and_ioremap_resource() and - * instead use platform_get_resource() and devm_ioremap() to avoid + * instead use platform_get_resource() here, and below for case 1) use + * syscon_node_to_regmap() while for case 2) use devm_ioremap() to avoid * conflicts due to address space overlap. */ res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return dev_err_probe(dev, -ENXIO, "missing IO resources\n"); =20 - base =3D devm_ioremap(dev, res->start, resource_size(res)); - if (!base) - return dev_err_probe(dev, -ENOMEM, - "failed to ioremap PMU regs\n"); - - reg_config.max_register =3D resource_size(res) - reg_config.reg_stride; - pd->regmap =3D devm_regmap_init_mmio(dev, base, ®_config); - if (IS_ERR(pd->regmap)) - return dev_err_probe(dev, PTR_ERR(base), - "failed to init regmap\n"); + if (pm_domain_cfg->use_parent_regmap) { + const struct resource *pres; + + pres =3D platform_get_resource(to_platform_device(dev->parent), + IORESOURCE_MEM, 0); + if (!pres) + return dev_err_probe(dev, -ENXIO, + "missing parent IO resources\n"); + + pd->regmap =3D syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(pd->regmap)) + return dev_err_probe(dev, PTR_ERR(pd->regmap), + "failed to acquire PMU regmap\n"); + + pd->configuration_reg =3D res->start - pres->start; + pd->status_reg =3D res->start - pres->start; + } else { + void __iomem *base; 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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f173a3e3sm226989566b.61.2026.03.18.08.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 08:28:03 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 18 Mar 2026 15:27:53 +0000 Subject: [PATCH v8 08/10] pmdomain: samsung: use dev_err() instead of pr_err() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-gs101-pd-v8-8-241523460b10@linaro.org> References: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> In-Reply-To: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Marek Szyprowski , Krzysztof Kozlowski X-Mailer: b4 0.14.3 dev_err() gives us more consistent error messages, which include the device. Switch to using dev_err(). Reviewed-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Signed-off-by: Andr=C3=A9 Draszik --- drivers/pmdomain/samsung/exynos-pm-domains.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pmdomain/samsung/exynos-pm-domains.c b/drivers/pmdomai= n/samsung/exynos-pm-domains.c index f8c0d11e9b33..6b0a0f395509 100644 --- a/drivers/pmdomain/samsung/exynos-pm-domains.c +++ b/drivers/pmdomain/samsung/exynos-pm-domains.c @@ -30,6 +30,7 @@ struct exynos_pm_domain_config { */ struct exynos_pm_domain { struct regmap *regmap; + struct device *dev; struct generic_pm_domain pd; u32 local_pwr_cfg; u32 configuration_reg; @@ -47,8 +48,9 @@ static int exynos_pd_power(struct generic_pm_domain *doma= in, bool power_on) pwr =3D power_on ? pd->local_pwr_cfg : 0; err =3D regmap_write(pd->regmap, pd->configuration_reg, pwr); if (err) { - pr_err("Regmap write for power domain %s %sable failed: %d\n", - domain->name, power_on ? "en" : "dis", err); + dev_err(pd->dev, + "Regmap write for power domain %s %sable failed: %d\n", + domain->name, power_on ? "en" : "dis", err); return err; } =20 @@ -71,8 +73,8 @@ static int exynos_pd_power(struct generic_pm_domain *doma= in, bool power_on) /* Only return timeout if no other error also occurred. */ err =3D -ETIMEDOUT; if (err) - pr_err("Power domain %s %sable failed: %d\n", domain->name, - power_on ? "en" : "dis", err); + dev_err(pd->dev, "Power domain %s %sable failed: %d\n", + domain->name, power_on ? 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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f173a3e3sm226989566b.61.2026.03.18.08.28.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 08:28:04 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 18 Mar 2026 15:27:54 +0000 Subject: [PATCH v8 09/10] pmdomain: samsung: implement SMC to save / restore TZ config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-gs101-pd-v8-9-241523460b10@linaro.org> References: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> In-Reply-To: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.3 Newer Exynos platforms have a Distributed Trust Zone Protection Control (DTZPC) linked to each power domain. It controls the access permissions to various registers from secure and non-secure world. An SMC call is required to instruct the firmware that the power domain is about to be turned off and again once it was turned on. This allows the firmware to save and restore the DTZPC configuration. Without, register access to various registers becomes impossible from Linux (causing SError), as the PoR configuration doesn't allow access. Neither the requirement for the SMC call, nor its arguments appear to be specific to gs101, as at least Exynos E850 also uses the same as can be seen in [1], hence prefix the new macros simply with EXYNOS_. At least on gs101, this SMC call isn't implemented for all power domains (e.g. it's missing for HSI2 (UFS)), therefore we issue a test SMC to store the configuration during probe, and if it fails we mark a domain as always-on to avoid the SErrors and to avoid unnecessarily retrying for each domain on/off. Link: https://lore.kernel.org/all/20230308233822.31180-4-semen.protsenko@li= naro.org/ [1] Signed-off-by: Andr=C3=A9 Draszik --- drivers/pmdomain/samsung/exynos-pm-domains.c | 96 ++++++++++++++++++++++++= ++-- 1 file changed, 90 insertions(+), 6 deletions(-) diff --git a/drivers/pmdomain/samsung/exynos-pm-domains.c b/drivers/pmdomai= n/samsung/exynos-pm-domains.c index 6b0a0f395509..d2e00f8310ce 100644 --- a/drivers/pmdomain/samsung/exynos-pm-domains.c +++ b/drivers/pmdomain/samsung/exynos-pm-domains.c @@ -9,6 +9,7 @@ // conjunction with runtime-pm. Support for both device-tree and non-devic= e-tree // based power domain support is included. =20 +#include #include #include #include @@ -16,12 +17,19 @@ #include #include #include +#include #include #include =20 +#define EXYNOS_SMC_CMD_PREPARE_PD_ONOFF 0x82000410 +#define EXYNOS_GET_IN_PD_DOWN 0 +#define EXYNOS_WAKEUP_PD_DOWN 1 +#define EXYNOS_RUNTIME_PM_TZPC_GROUP 2 + struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ u32 local_pwr_cfg; + u32 smc_offset; bool use_parent_regmap; }; =20 @@ -32,11 +40,28 @@ struct exynos_pm_domain { struct regmap *regmap; struct device *dev; struct generic_pm_domain pd; - u32 local_pwr_cfg; + const struct exynos_pm_domain_config *cfg; u32 configuration_reg; u32 status_reg; + phys_addr_t ac_pa; }; =20 +static int exynos_pd_access_controller_power(struct exynos_pm_domain *pd, + bool power_on) +{ + struct arm_smccc_res res; + + if (!pd->ac_pa || !pd->cfg->smc_offset) + return 0; + + arm_smccc_smc(EXYNOS_SMC_CMD_PREPARE_PD_ONOFF, + power_on ? EXYNOS_WAKEUP_PD_DOWN : EXYNOS_GET_IN_PD_DOWN, + pd->ac_pa + pd->cfg->smc_offset, + EXYNOS_RUNTIME_PM_TZPC_GROUP, 0, 0, 0, 0, &res); + + return res.a0; +} + static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) { struct exynos_pm_domain *pd; @@ -45,7 +70,17 @@ static int exynos_pd_power(struct generic_pm_domain *dom= ain, bool power_on) =20 pd =3D container_of(domain, struct exynos_pm_domain, pd); =20 - pwr =3D power_on ? pd->local_pwr_cfg : 0; + if (!power_on) { + err =3D exynos_pd_access_controller_power(pd, power_on); + if (err) { + dev_err(pd->dev, + "SMC for power domain %s %sable failed: %d\n", + domain->name, power_on ? "en" : "dis", err); + return err; + } + } + + pwr =3D power_on ? pd->cfg->local_pwr_cfg : 0; err =3D regmap_write(pd->regmap, pd->configuration_reg, pwr); if (err) { dev_err(pd->dev, @@ -60,7 +95,7 @@ static int exynos_pd_power(struct generic_pm_domain *doma= in, bool power_on) unsigned int val; =20 err =3D regmap_read(pd->regmap, pd->status_reg, &val); - if (err || ((val & pd->local_pwr_cfg) !=3D pwr)) { + if (err || ((val & pd->cfg->local_pwr_cfg) !=3D pwr)) { cpu_relax(); usleep_range(80, 100); continue; @@ -72,9 +107,21 @@ static int exynos_pd_power(struct generic_pm_domain *do= main, bool power_on) if (!timeout && !err) /* Only return timeout if no other error also occurred. */ err =3D -ETIMEDOUT; - if (err) + if (err) { dev_err(pd->dev, "Power domain %s %sable failed: %d\n", domain->name, power_on ? "en" : "dis", err); + return err; + } + + if (power_on) { + err =3D exynos_pd_access_controller_power(pd, power_on); + if (err) { + dev_err(pd->dev, + "SMC for power domain %s %sable failed: %d\n", + domain->name, power_on ? "en" : "dis", err); + return err; + } + } =20 return err; } @@ -99,6 +146,7 @@ static const struct exynos_pm_domain_config exynos5433_c= fg =3D { =20 static const struct exynos_pm_domain_config gs101_cfg =3D { .local_pwr_cfg =3D BIT(0), + .smc_offset =3D 0x0204, .use_parent_regmap =3D true, }; =20 @@ -126,6 +174,38 @@ static const char *exynos_get_domain_name(struct devic= e *dev, return devm_kstrdup_const(dev, name, GFP_KERNEL); } =20 +static int exynos_pd_get_access_controller(struct exynos_pm_domain *pd) +{ + struct device_node *ac_np; + struct resource ac_res; + int ret; + + ac_np =3D of_parse_phandle(pd->dev->of_node, "samsung,dtzpc", 0); + if (!ac_np) + return 0; + + ret =3D of_address_to_resource(ac_np, 0, &ac_res); + of_node_put(ac_np); + if (ret) + return dev_err_probe(pd->dev, ret, + "failed to get access controller\n"); + + pd->ac_pa =3D ac_res.start; + + /* + * For some domains, TZ save/restore might not be implemented. If that + * is the case, simply mark it as always on, as otherwise a power cycle + * will lead to lost TZ configuration, making it impossible to access + * registers from Linux afterwards. + */ + if (exynos_pd_access_controller_power(pd, false) =3D=3D -ENOENT) { + pd->ac_pa =3D 0; + pd->pd.flags |=3D GENPD_FLAG_ALWAYS_ON; + } + + return 0; +} + static int exynos_pd_probe(struct platform_device *pdev) { const struct exynos_pm_domain_config *pm_domain_cfg; @@ -203,10 +283,14 @@ static int exynos_pd_probe(struct platform_device *pd= ev) =20 pd->pd.power_off =3D exynos_pd_power_off; pd->pd.power_on =3D exynos_pd_power_on; - pd->local_pwr_cfg =3D pm_domain_cfg->local_pwr_cfg; + pd->cfg =3D pm_domain_cfg; pd->configuration_reg +=3D 0; pd->status_reg +=3D 4; =20 + ret =3D exynos_pd_get_access_controller(pd); + if (ret) + return ret; + /* * Some Samsung platforms with bootloaders turning on the splash-screen * and handing it over to the kernel, requires the power-domains to be @@ -220,7 +304,7 @@ static int exynos_pd_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "failed to read status\n"); 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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f173a3e3sm226989566b.61.2026.03.18.08.28.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 08:28:05 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 18 Mar 2026 15:27:55 +0000 Subject: [PATCH v8 10/10] pmdomain: samsung: implement domain-supply regulator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-gs101-pd-v8-10-241523460b10@linaro.org> References: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> In-Reply-To: <20260318-gs101-pd-v8-0-241523460b10@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.3 Some power domains on Exynos are fed by a regulator rail and therefore regulator control needs be implemented for Exynos power domains. On Google gs101, HSI0 (USB) is one example of such a power domain. While at it, add a to_exynos_pd() to avoid direct use of container_of() in various additional places, and update existing code to use it. Signed-off-by: Andr=C3=A9 Draszik --- v8: - add missing \n in some of the new log messages --- drivers/pmdomain/samsung/exynos-pm-domains.c | 53 ++++++++++++++++++++++++= +--- 1 file changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/pmdomain/samsung/exynos-pm-domains.c b/drivers/pmdomai= n/samsung/exynos-pm-domains.c index d2e00f8310ce..3b5e84ca2dec 100644 --- a/drivers/pmdomain/samsung/exynos-pm-domains.c +++ b/drivers/pmdomain/samsung/exynos-pm-domains.c @@ -20,12 +20,15 @@ #include #include #include +#include =20 #define EXYNOS_SMC_CMD_PREPARE_PD_ONOFF 0x82000410 #define EXYNOS_GET_IN_PD_DOWN 0 #define EXYNOS_WAKEUP_PD_DOWN 1 #define EXYNOS_RUNTIME_PM_TZPC_GROUP 2 =20 +#define to_exynos_pd(gpd) container_of_const(gpd, struct exynos_pm_domain,= pd) + struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ u32 local_pwr_cfg; @@ -39,6 +42,7 @@ struct exynos_pm_domain_config { struct exynos_pm_domain { struct regmap *regmap; struct device *dev; + struct regulator *supply; struct generic_pm_domain pd; const struct exynos_pm_domain_config *cfg; u32 configuration_reg; @@ -64,12 +68,10 @@ static int exynos_pd_access_controller_power(struct exy= nos_pm_domain *pd, =20 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) { - struct exynos_pm_domain *pd; + struct exynos_pm_domain *pd =3D to_exynos_pd(domain); u32 timeout, pwr; int err; =20 - pd =3D container_of(domain, struct exynos_pm_domain, pd); - if (!power_on) { err =3D exynos_pd_access_controller_power(pd, power_on); if (err) { @@ -126,14 +128,45 @@ static int exynos_pd_power(struct generic_pm_domain *= domain, bool power_on) return err; } =20 +static int exynos_pd_regulator_enable(struct regulator *supply) +{ + return supply ? regulator_enable(supply) : 0; +} + +static int exynos_pd_regulator_disable(struct regulator *supply) +{ + return supply ? regulator_disable(supply) : 0; +} + static int exynos_pd_power_on(struct generic_pm_domain *domain) { - return exynos_pd_power(domain, true); + struct exynos_pm_domain *pd =3D to_exynos_pd(domain); + int ret; + + ret =3D exynos_pd_regulator_enable(pd->supply); + if (ret) + return ret; + + ret =3D exynos_pd_power(domain, true); + if (ret) + exynos_pd_regulator_disable(pd->supply); + + return ret; } =20 static int exynos_pd_power_off(struct generic_pm_domain *domain) { - return exynos_pd_power(domain, false); + struct exynos_pm_domain *pd =3D to_exynos_pd(domain); + int ret; + + ret =3D exynos_pd_power(domain, false); + if (ret) + return ret; + + /* Ignore regulator errors - the domain was disabled after all. */ + exynos_pd_regulator_disable(pd->supply); + + return 0; } =20 static const struct exynos_pm_domain_config exynos4210_cfg =3D { @@ -291,6 +324,16 @@ static int exynos_pd_probe(struct platform_device *pde= v) if (ret) return ret; =20 + /* get the domain power supply if required */ + pd->supply =3D devm_regulator_get_optional(dev, "domain"); + if (IS_ERR(pd->supply)) { + if (PTR_ERR(pd->supply) !=3D -ENODEV) + return dev_err_probe(dev, PTR_ERR(pd->supply), + "failed to get domain supply\n"); + + pd->supply =3D NULL; + } + /* * Some Samsung platforms with bootloaders turning on the splash-screen * and handing it over to the kernel, requires the power-domains to be --=20 2.53.0.851.ga537e3e6e9-goog