From nobody Mon Apr 6 18:22:59 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22E733C4567; Wed, 18 Mar 2026 11:04:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831888; cv=none; b=l0zHK/PILnKjcz4zpn3f3fAlR1G2bbe3CtAy3a9Lu4CetwzMAo5miUaaO/cpBIR7XB09QMAcrJ9A/cInlumeN+p3L3p4OUp46Gctbk0/xMCWFmtFBvk3QISD1OaZ7eU1oVw2H7DODuWcgRS7tGcXwbOEWzfUs8pdatTlJI2Ixgw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831888; c=relaxed/simple; bh=7rNVad+B7+QaXsOmWf2AwAwbqZ0cbbd/BzWX6Rw2CF0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m+vWJmRJE21b8cjj+vA7l5F/5f2CaESgmYjgcu3EXyAvctaUmoP5nrasnAvAdntdlEL/vtwbIY/konhxKaSEe1PG8+T3NuRbvm/ohO9a5/gBs0BVhimtZ6gBxKnMDIlj+MZIHxHqtWHVkYo4ibEzwxKZlnWJ4J6WtkBrtBU5/co= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Gdd4xjR+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Gdd4xjR+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B5D8FC2BCB2; Wed, 18 Mar 2026 11:04:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773831887; bh=7rNVad+B7+QaXsOmWf2AwAwbqZ0cbbd/BzWX6Rw2CF0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gdd4xjR+aoSrnT2aU4PCaudtHFjxR/RcSD6iG2HqgqmptJBvtIdA42vqcb8Zf5ymv +b+GU0vL5sb+qglnCk+0FGFxZlmXLL76DY0gNf47b8FielnC41/2nahumdQwNbXyIm zXBz08HIQbrZPTPfkwARpAgopIHsIP5DStkS3r+tZAr7hIsnMYjLkXUPWuszKELxFY 37uOTk8mbxB1Iicn61RQ1UMIJ/PPdX43duB71ARmvbvj9IMBo+vnnuzdLZIo6DdwU1 4Tj12EOwvIv+CkDo8QAWsI7SBfHtwJzup/7b5QcSlWlDcIBnaMSSYoAYVbLPt8orM8 x64UgwTvoLvOQ== From: Conor Dooley To: linux-gpio@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Thomas Gleixner , Herve Codina , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v13 1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation Date: Wed, 18 Mar 2026 11:04:32 +0000 Message-ID: <20260318-fondly-tradition-90b8241f0cc8@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260318-gift-nearest-fd3ef3e4819b@spud> References: <20260318-gift-nearest-fd3ef3e4819b@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3190; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=27/jkLY5kQVq9jTRVF6tl1zmApScLGF112Z5WyTB0Qc=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJm72o6s9HuxjM2yme9l5esMlVvTJJ/PMltlw2R67ZVNw sLtZ8tedJSyMIhxMciKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiecaMDP3H4mX4dWriCtXC QoqPyZYt5Lqx0FHIYLnd1G2RfIsSNjAyvJ1QGbRzAd+mrIidVtIlHwMsTP/NFNzM63p/7v/3C/b H8gEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The microchip,mpfs-gpio binding suffered greatly due to being written with a narrow minded view of the controller, and the interrupt bits ended up incorrect. It was mistakenly assumed that the interrupt configuration was set by platform firmware, based on the FPGA configuration, and that the GPIO DT nodes were the only way to really communicate interrupt configuration to software. Instead, the mux should be a device in its own right, and the GPIO controllers should be connected to it, rather than to the PLIC. Now that a binding exists for that mux, try to fix the misconceptions in the GPIO controller binding. Firstly, it's not possible for this controller to have fewer than 14 GPIOs, and thus 14 interrupts also. There are three controllers, with 14, 24 & 32 GPIOs each. The fabric core, CoreGPIO, can of course have a customisable number of GPIOs. The example is wacky too - it follows from the incorrect understanding that the GPIO controllers are connected to the PLIC directly. They are not however, with a mux sitting in between. Update the example to use the mux as a parent, and the interrupt numbers at the mux for GPIO2 as the example - rather than the strange looking, repeated <53>. Signed-off-by: Conor Dooley Acked-by: Rob Herring (Arm) Reviewed-by: Linus Walleij --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 24 ++++++++++++------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yam= l b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml index 184432d24ea18..9b8c58f391f40 100644 --- a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -62,6 +62,11 @@ allOf: contains: const: microchip,mpfs-gpio then: + properties: + ngpios: + enum: [14, 24, 32] + interrupts: + minItems: 14 required: - interrupts - "#interrupt-cells" @@ -82,18 +87,19 @@ examples: compatible =3D "microchip,mpfs-gpio"; reg =3D <0x20122000 0x1000>; clocks =3D <&clkcfg 25>; - interrupt-parent =3D <&plic>; + interrupt-parent =3D <&irqmux>; gpio-controller; #gpio-cells =3D <2>; + ngpios =3D <32>; interrupt-controller; #interrupt-cells =3D <1>; - interrupts =3D <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; + interrupts =3D <64>, <65>, <66>, <67>, + <68>, <69>, <70>, <71>, + <72>, <73>, <74>, <75>, + <76>, <77>, <78>, <79>, + <80>, <81>, <82>, <83>, + <84>, <85>, <86>, <87>, + <88>, <89>, <90>, <91>, + <92>, <93>, <94>, <95>; }; ... --=20 2.51.0 From nobody Mon Apr 6 18:22:59 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBC6936BCE7; Wed, 18 Mar 2026 11:04:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773831892; cv=none; b=jzFjjQBvrGtY3VUP30cJiEaHCv7fSgS5gdTr6Qg/2kd2ePFXKCCW2Z2njW1XNvu68H65DBo3/SwbS5BQbHZeV8POWTbZodYxXPTRC1bvCU/lS68S00yRyoAJPkCFfjhEB5Azdpuz6dXeOIlLhDmeuoERPvf3U+ldKetsTsQCihw= ARC-Message-Signature: i=1; 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b=qQKnFWuh9UnmhLyeTrExtfzSyxRSpHsXJ19zfTRSdwpbs1ONFoYYw0/+0wTe0L3Mu 8uAkikK8y689EEg/Bn1eurLNbomn2hI/YL9b/Oghj4+0lkT9shyqH6EFeLAJmzKPZE n2+xgOIPy8mjaBPFWv2d2YJctmWmR4ajYEn/PnXALLTBWsnuMkIDUeNOF2ycKHKdPk 96v6xT4oTVnqCUSV2P6YHklnhTn3Nu9wa6TPXo+Ann1oJaHy11pwDR75go0VIowEAl U0KUAhm0egBxSy6+2+k2DkJE+oytE7dtg3FuvBCA/JbAQth0LXWMQTD53psTroz3lQ gGVrSHIlaCU0Q== From: Conor Dooley To: linux-gpio@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Thomas Gleixner , Herve Codina , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v13 2/5] gpio: mpfs: Add interrupt support Date: Wed, 18 Mar 2026 11:04:33 +0000 Message-ID: <20260318-siamese-twirl-ba045ad446f9@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260318-gift-nearest-fd3ef3e4819b@spud> References: <20260318-gift-nearest-fd3ef3e4819b@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6415; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=qZAxon0cLWKPAGU5V9eYU2gifbxZBOUs+2bM9g63Uso=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJm72o6E/KhMu9YioWc2b9KflzLCESWuby9rJ209nrX46 6o1Pz91d5SyMIhxMciKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiWqKMDK8O3t9h/aOgu0JZ LUlfPO5TSO+LwwGmuVYhhwotpjQudmL47xL3x8+9T7LA/si7b3zx0TLRL778vrR5RdulH3388mU unAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add support for interrupts to the PolarFire SoC GPIO driver. Each GPIO has an independent interrupt that is wired to an interrupt mux that sits between the controllers and the PLIC. The SoC has more GPIO lines than connections from the mux to the PLIC, so some GPIOs must share PLIC interrupts. The configuration is not static and is set at runtime, conventionally by the platform's firmware. CoreGPIO, the version intended for use in the FPGA fabric has two interrupt output ports, one is IO_NUM bits wide, as is used in the hardened cores, and the other is a single bit with all lines ORed together. Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Conor Dooley --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-mpfs.c | 122 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 120 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b45fb799e36c1..1d1239323f615 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -572,6 +572,7 @@ config GPIO_PL061 config GPIO_POLARFIRE_SOC bool "Microchip FPGA GPIO support" select REGMAP_MMIO + select GPIOLIB_IRQCHIP help Say yes here to support the GPIO controllers on Microchip FPGAs. =20 diff --git a/drivers/gpio/gpio-mpfs.c b/drivers/gpio/gpio-mpfs.c index 9468795b96348..1a4cf213c723c 100644 --- a/drivers/gpio/gpio-mpfs.c +++ b/drivers/gpio/gpio-mpfs.c @@ -9,8 +9,9 @@ #include #include #include -#include +#include #include +#include #include #include #include @@ -18,7 +19,7 @@ =20 #define MPFS_GPIO_CTRL(i) (0x4 * (i)) #define MPFS_MAX_NUM_GPIO 32 -#define MPFS_GPIO_EN_INT 3 +#define MPFS_GPIO_EN_INT BIT(3) #define MPFS_GPIO_EN_OUT_BUF BIT(2) #define MPFS_GPIO_EN_IN BIT(1) #define MPFS_GPIO_EN_OUT BIT(0) @@ -52,6 +53,7 @@ static const struct regmap_config mpfs_gpio_regmap_config= =3D { .reg_bits =3D 32, .reg_stride =3D 4, .val_bits =3D 32, + .use_raw_spinlock =3D true, }; =20 static int mpfs_gpio_direction_input(struct gpio_chip *gc, unsigned int gp= io_index) @@ -114,13 +116,98 @@ static int mpfs_gpio_set(struct gpio_chip *gc, unsign= ed int gpio_index, int valu return ret; } =20 +static int mpfs_gpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(data); + struct mpfs_gpio_chip *mpfs_gpio =3D gpiochip_get_data(gc); + int gpio_index =3D irqd_to_hwirq(data) % 32; + u32 interrupt_type; + + switch (type) { + case IRQ_TYPE_EDGE_BOTH: + interrupt_type =3D MPFS_GPIO_TYPE_INT_EDGE_BOTH; + break; + case IRQ_TYPE_EDGE_FALLING: + interrupt_type =3D MPFS_GPIO_TYPE_INT_EDGE_NEG; + break; + case IRQ_TYPE_EDGE_RISING: + interrupt_type =3D MPFS_GPIO_TYPE_INT_EDGE_POS; + break; + case IRQ_TYPE_LEVEL_HIGH: + interrupt_type =3D MPFS_GPIO_TYPE_INT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + interrupt_type =3D MPFS_GPIO_TYPE_INT_LEVEL_LOW; + break; + } + + regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), + MPFS_GPIO_TYPE_INT_MASK, interrupt_type); + + return 0; +} + +static void mpfs_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(data); + struct mpfs_gpio_chip *mpfs_gpio =3D gpiochip_get_data(gc); + int gpio_index =3D irqd_to_hwirq(data) % 32; + + gpiochip_enable_irq(gc, gpio_index); + mpfs_gpio_direction_input(gc, gpio_index); + regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), + MPFS_GPIO_EN_INT, MPFS_GPIO_EN_INT); +} + +static void mpfs_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(data); + struct mpfs_gpio_chip *mpfs_gpio =3D gpiochip_get_data(gc); + int gpio_index =3D irqd_to_hwirq(data) % 32; + + regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), + MPFS_GPIO_EN_INT, 0); + gpiochip_disable_irq(gc, gpio_index); +} + +static const struct irq_chip mpfs_gpio_irqchip =3D { + .name =3D "MPFS GPIO", + .irq_set_type =3D mpfs_gpio_irq_set_type, + .irq_mask =3D mpfs_gpio_irq_mask, + .irq_unmask =3D mpfs_gpio_irq_unmask, + .flags =3D IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static void mpfs_gpio_irq_handler(struct irq_desc *desc) +{ + struct irq_chip *irqchip =3D irq_desc_get_chip(desc); + struct mpfs_gpio_chip *mpfs_gpio =3D irq_desc_get_handler_data(desc); + unsigned long status; + u32 val; + int i; + + chained_irq_enter(irqchip, desc); + + regmap_read(mpfs_gpio->regs, MPFS_IRQ_REG, &val); + status =3D val; + for_each_set_bit(i, &status, MPFS_MAX_NUM_GPIO) { + regmap_write(mpfs_gpio->regs, MPFS_IRQ_REG, BIT(i)); + generic_handle_domain_irq(mpfs_gpio->gc.irq.domain, i); + } + + chained_irq_exit(irqchip, desc); +} + static int mpfs_gpio_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->of_node; struct mpfs_gpio_chip *mpfs_gpio; + struct gpio_irq_chip *girq; struct clk *clk; void __iomem *base; - int ngpios; + int ngpios, nirqs, ret; =20 mpfs_gpio =3D devm_kzalloc(dev, sizeof(*mpfs_gpio), GFP_KERNEL); if (!mpfs_gpio) @@ -157,6 +244,35 @@ static int mpfs_gpio_probe(struct platform_device *pde= v) mpfs_gpio->gc.parent =3D dev; mpfs_gpio->gc.owner =3D THIS_MODULE; =20 + nirqs =3D of_irq_count(node); + if (nirqs > MPFS_MAX_NUM_GPIO) + return -ENXIO; + + if (nirqs) { + girq =3D &mpfs_gpio->gc.irq; + + gpio_irq_chip_set_chip(girq, &mpfs_gpio_irqchip); + + girq->num_parents =3D nirqs; + girq->parents =3D devm_kcalloc(&pdev->dev, girq->num_parents, + sizeof(*girq->parents), GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + + for (int i =3D 0; i < nirqs; i++) { + ret =3D platform_get_irq(pdev, i); + if (ret < 0) + return ret; + + girq->parents[i] =3D ret; + girq->parent_handler_data =3D mpfs_gpio; + girq->parent_handler =3D mpfs_gpio_irq_handler; + } + + girq->handler =3D handle_level_irq; + girq->default_type =3D IRQ_TYPE_NONE; + } + return devm_gpiochip_add_data(dev, &mpfs_gpio->gc, mpfs_gpio); } =20 --=20 2.51.0 From nobody Mon Apr 6 18:22:59 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 327543BA25E; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AE6CGxWA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE94EC2BCB2; Wed, 18 Mar 2026 11:04:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773831895; bh=ibJRUfU6Xesj/AT2j6L/6W1DSm2j7eke+aFZWYsow44=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AE6CGxWAqqRddKzIADfVMNULZCMiiBRbWbH1TRAB72+eDae3Tjshb5lF84r1ve3L8 Rceh/CLEvfe+LcHy37DpwZPIMGx0aCtEdhzjC3KO2vU7N7iWvHotD7YCheDfzB6vNY jnoqQS6uwC8tQMoZa5YIwbT//JM1/DUP22W/Fi1mBRu9xjSL+CICLDzmcFkaaGsKNH PsYeDvSAIwBzZpOI3KfKJhPX10nwEUYxe6N6wcXKdM8DjU9gYy32J1RVwEygB9VTXm BswueGYxP6vDfyZqJ2tL6eU8/rQHseKTgw8KJ3Ve+HakH6AkSC1+7ccfjUeZFtrW1Y JWLtHlLIPjmTg== From: Conor Dooley To: linux-gpio@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Thomas Gleixner , Herve Codina , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v13 3/5] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux Date: Wed, 18 Mar 2026 11:04:34 +0000 Message-ID: <20260318-whisking-steadily-91b2497f6fb9@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260318-gift-nearest-fd3ef3e4819b@spud> References: <20260318-gift-nearest-fd3ef3e4819b@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5607; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=wBo9yWbFkmoIJWrjOw6aKTDA8JEfCYkbuuKymCWysYg=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJm72o7Ynngv2unhERCW4Dexxzm+Odnv6PujL0Ic+wrTl oQaJWl3lLIwiHExyIopsiTe7muRWv/HZYdzz1uYOaxMIEMYuDgFYCIbIxn+5wYWsZ7yntpjVOd1 f7Nv7Qqz+CNLEo6+Td914Z2Tl5jiPoY/nFs/pRvNPHZBbd6KebsOZC5sy3rcet5ywp9A6YALM8u EmAE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On PolarFire SoC there are more GPIO interrupts than there are interrupt lines available on the PLIC, and a runtime configurable mux is used to decide which interrupts are assigned direct connections to the PLIC & which are relegated to sharing a line. Reviewed-by: Herve Codina Signed-off-by: Conor Dooley Reviewed-by: Linus Walleij Reviewed-by: Rob Herring (Arm) --- .../soc/microchip/microchip,mpfs-irqmux.yaml | 103 ++++++++++++++++++ .../microchip,mpfs-mss-top-sysreg.yaml | 4 + 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-irqmux.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -irqmux.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mp= fs-irqmux.yaml new file mode 100644 index 0000000000000..51164772724f5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux= .yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-irqmux.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Polarfire SoC GPIO Interrupt Mux + +maintainers: + - Conor Dooley + +description: | + There are 3 GPIO controllers on this SoC, of which: + - GPIO controller 0 has 14 GPIOs + - GPIO controller 1 has 24 GPIOs + - GPIO controller 2 has 32 GPIOs + + All GPIOs are capable of generating interrupts, for a total of 70. + There are only 41 IRQs available however, so a configurable mux is used = to + ensure all GPIOs can be used for interrupt generation. + 38 of the 41 interrupts are in what the documentation calls "direct mode= ", + as they provide an exclusive connection from a GPIO to the PLIC. + Lines 18 to 23 on GPIO controller 1 are always in "direct mode". + The 3 remaining interrupts are used to mux the interrupts which do not h= ave + a exclusive connection, one for each GPIO controller. + +properties: + compatible: + const: microchip,mpfs-irqmux + + reg: + maxItems: 1 + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0x7f + + interrupt-map: + description: | + Specifies the mapping from GPIO interrupt lines to plic interrupts. + + The child interrupt number set in arrays items is computed using the + following formula: + gpio_bank * 32 + gpio_number + with: + - gpio_bank: The GPIO bank number + - 0 for GPIO0, + - 1 for GPIO1, + - 2 for GPIO2 + - gpio_number: Number of the gpio in the bank (0..31) + maxItems: 70 + +required: + - compatible + - reg + - "#address-cells" + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: false + +examples: + - | + interrupt-controller@54 { + compatible =3D "microchip,mpfs-irqmux"; + reg =3D <0x54 0x4>; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x7f>; + interrupt-map =3D <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; + }; diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml index 44e4a50c31554..276d48ba15f01 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -38,6 +38,10 @@ properties: of PolarFire clock/reset IDs. const: 1 =20 + interrupt-controller@54: + type: object + $ref: /schemas/soc/microchip/microchip,mpfs-irqmux.yaml + pinctrl@200: type: object $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml --=20 2.51.0 From nobody Mon Apr 6 18:22:59 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EECE3A873A; Wed, 18 Mar 2026 11:04:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 18 Mar 2026 11:04:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773831898; bh=QkhsuHxeBIhHrtgQizPa1cqFV48lv4Y3L5S4Fc3AdQ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pzthHmHjANpdtvpDH6RziZNfyMSEEYRgE6PLVZWEpmNtaawu7rXebG5y2GeoEAZgB NNw7Ult6VXrmISVqKFXuxPKF+EB1rUMa+wBFke7fo3tu9cVSo6Ko4wtcXWkcSCkhs4 UjfGJUfAPbbXPi6YRnbc33deAFV/G3CwNISFs0UFi8l9KbxX4ubfJmAyvbiccWr2W9 TCi3AYmNDb/TCx0OWHEiwfu4DdFh4WQaFd7tkj5877cTK81QVwhuTbb7LQY4X9weZq F8kiSTjPDL44sDn/RgNBV1pAfD8SIM5J+8iQfmmh9hmKAzdZajLWttRWWO0C/MFF6z YlhfdkB8SiRcw== From: Conor Dooley To: linux-gpio@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Thomas Gleixner , Herve Codina , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v13 4/5] soc: microchip: add mpfs gpio interrupt mux driver Date: Wed, 18 Mar 2026 11:04:35 +0000 Message-ID: <20260318-capsize-agreed-d11a67fdfad2@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260318-gift-nearest-fd3ef3e4819b@spud> References: <20260318-gift-nearest-fd3ef3e4819b@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8942; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=0VdL10AsIya/09nL9LUhGVZIsekmdPpe92n4y+qOvNc=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJm72o4+e6+nc2dCc1XyQYWrHhusKyc8mnC3TrPFxWHKz CRJl4fyHaUsDGJcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjIql8M/5SUcxqygn6+1/N7 s+XcxAW7jp9yV77jZmRvH2sUX+L334vhn8G88qcbrL9ZvMjIYX0y48+BylO3Xge1N8kpfl5be6s wjR0A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On PolarFire SoC there are more GPIO interrupts than there are interrupt lines available on the PLIC, and a runtime configurable mux is used to decide which interrupts are assigned direct connections to the PLIC & which are relegated to sharing a line. Add a driver so that Linux can set the mux based on the interrupt mapping in the devicetree. Reviewed-by: Herve Codina Reviewed-by: Linus Walleij Reviewed-by: Bartosz Golaszewski Signed-off-by: Conor Dooley --- MAINTAINERS | 2 +- drivers/soc/microchip/Kconfig | 11 ++ drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs-irqmux.c | 181 ++++++++++++++++++++++++++++ 4 files changed, 194 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/microchip/mpfs-irqmux.c diff --git a/MAINTAINERS b/MAINTAINERS index 55af015174a54..723c58756a5c1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22734,7 +22734,7 @@ F: Documentation/devicetree/bindings/pinctrl/microc= hip,mpfs-pinctrl-mssio.yaml F: Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpi= o2.yaml F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml F: Documentation/devicetree/bindings/riscv/microchip.yaml -F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-cont= roller.yaml +F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs*.yaml F: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml F: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml F: arch/riscv/boot/dts/microchip/ diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig index bcf5546025610..af7946741bce4 100644 --- a/drivers/soc/microchip/Kconfig +++ b/drivers/soc/microchip/Kconfig @@ -1,3 +1,14 @@ +config POLARFIRE_SOC_IRQ_MUX + bool "Microchip PolarFire SoC's GPIO IRQ Mux" + depends on ARCH_MICROCHIP + select REGMAP + select REGMAP_MMIO + default y + help + Support for the interrupt mux on Polarfire SoC. It sits between + the GPIO controllers and the PLIC, as only 41 interrupts are shared + between 3 GPIO controllers with a total of 70 interrupts. + config POLARFIRE_SOC_SYS_CTRL tristate "Microchip PolarFire SoC (MPFS) system controller support" depends on POLARFIRE_SOC_MAILBOX diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile index 1a3a1594b089b..55775db45ee76 100644 --- a/drivers/soc/microchip/Makefile +++ b/drivers/soc/microchip/Makefile @@ -1,2 +1,3 @@ +obj-$(CONFIG_POLARFIRE_SOC_IRQ_MUX) +=3D mpfs-irqmux.o obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) +=3D mpfs-sys-controller.o obj-$(CONFIG_POLARFIRE_SOC_SYSCONS) +=3D mpfs-control-scb.o mpfs-mss-top-s= ysreg.o diff --git a/drivers/soc/microchip/mpfs-irqmux.c b/drivers/soc/microchip/mp= fs-irqmux.c new file mode 100644 index 0000000000000..ae15e913e7802 --- /dev/null +++ b/drivers/soc/microchip/mpfs-irqmux.c @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Largely copied from rzn1_irqmux.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MPFS_IRQMUX_CR 0x54 +#define MPFS_IRQMUX_NUM_CHILDREN 96 +#define MPFS_IRQMUX_NUM_DIRECT 38 +#define MPFS_IRQMUX_DIRECT_START 13 +#define MPFS_IRQMUX_DIRECT_END 50 +#define MPFS_IRQMUX_NONDIRECT_END 53 + +static int mpfs_irqmux_is_direct_mode(struct device *dev, + const struct of_phandle_args *parent_args) +{ + if (parent_args->args_count !=3D 1) { + dev_err(dev, "Invalid interrupt-map item\n"); + return -EINVAL; + } + + if (parent_args->args[0] < MPFS_IRQMUX_DIRECT_START || + parent_args->args[0] > MPFS_IRQMUX_NONDIRECT_END) { + dev_err(dev, "Invalid interrupt %u\n", parent_args->args[0]); + return -EINVAL; + } + + if (parent_args->args[0] > MPFS_IRQMUX_DIRECT_END) + return 0; + + return 1; +} + +static int mpfs_irqmux_probe(struct platform_device *pdev) +{ + DECLARE_BITMAP(child_done, MPFS_IRQMUX_NUM_CHILDREN) =3D {}; + DECLARE_BITMAP(parent_done, MPFS_IRQMUX_NUM_DIRECT) =3D {}; + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct of_imap_parser imap_parser; + struct of_imap_item imap_item; + struct regmap *regmap; + int ret, direct_mode, line, controller, gpio, parent_line; + u32 tmp, val =3D 0, old; + + regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Failed to find syscon regmap= \n"); + + /* We support only #interrupt-cells =3D <1> and #address-cells =3D <0> */ + ret =3D of_property_read_u32(np, "#interrupt-cells", &tmp); + if (ret) + return ret; + if (tmp !=3D 1) + return -EINVAL; + + ret =3D of_property_read_u32(np, "#address-cells", &tmp); + if (ret) + return ret; + if (tmp !=3D 0) + return -EINVAL; + + ret =3D of_imap_parser_init(&imap_parser, np, &imap_item); + if (ret) + return ret; + + for_each_of_imap_item(&imap_parser, &imap_item) { + + direct_mode =3D mpfs_irqmux_is_direct_mode(dev, &imap_item.parent_args); + if (direct_mode < 0) { + of_node_put(imap_item.parent_args.np); + return direct_mode; + } + + line =3D imap_item.child_imap[0]; + gpio =3D line % 32; + controller =3D line / 32; + + if (controller > 2) { + of_node_put(imap_item.parent_args.np); + dev_err(dev, "child interrupt number too large: %d\n", line); + return -EINVAL; + } + + if (test_and_set_bit(line, child_done)) { + of_node_put(imap_item.parent_args.np); + dev_err(dev, "mux child line %d already defined in interrupt-map\n", + line); + return -EINVAL; + } + + parent_line =3D imap_item.parent_args.args[0] - MPFS_IRQMUX_DIRECT_START; + if (direct_mode && test_and_set_bit(parent_line, parent_done)) { + of_node_put(imap_item.parent_args.np); + dev_err(dev, "mux parent line %d already defined in interrupt-map\n", + line); + return -EINVAL; + } + + /* + * There are 41 interrupts assigned to GPIOs, of which 38 are "direct". = Since the + * mux has 32 bits only, 6 of these exclusive/"direct" interrupts remain= . These + * are used by GPIO controller 1's lines 18 to 23. Nothing needs to be d= one + * for these interrupts. + */ + if (controller =3D=3D 1 && gpio >=3D 18) + continue; + + /* + * The mux has a single register, where bits 0 to 13 mux between GPIO co= ntroller + * 1's 14 GPIOs and GPIO controller 2's first 14 GPIOs. The remaining bi= ts mux + * between the first 18 GPIOs of controller 1 and the last 18 GPIOS of + * controller 2. If a bit in the mux's control register is set, the + * corresponding interrupt line for GPIO controller 0 or 1 will be put in + * "non-direct" mode. If cleared, the "fabric" controller's will. + * + * Register layout: + * GPIO 1 interrupt line 17 | mux bit 31 | GPIO 2 interrupt line 31 + * ... | ... | ... + * ... | ... | ... + * GPIO 1 interrupt line 0 | mux bit 14 | GPIO 2 interrupt line 14 + * GPIO 0 interrupt line 13 | mux bit 13 | GPIO 2 interrupt line 13 + * ... | ... | ... + * ... | ... | ... + * GPIO 0 interrupt line 0 | mux bit 0 | GPIO 2 interrupt line 0 + * + * As the binding mandates 70 items, one for each GPIO line, there's no = need to + * handle anything for GPIO controller 2, since the bit will be set for = the + * corresponding line in GPIO controller 0 or 1. + */ + if (controller =3D=3D 2) + continue; + + /* + * If in direct mode, the bit is cleared, nothing needs to be done as va= l is zero + * initialised and that's the direct mode setting for GPIO controller 0 = and 1. + */ + if (direct_mode) + continue; + + if (controller =3D=3D 0) + val |=3D 1U << gpio; + else + val |=3D 1U << (gpio + 14); + } + + regmap_read(regmap, MPFS_IRQMUX_CR, &old); + regmap_write(regmap, MPFS_IRQMUX_CR, val); + + if (val !=3D old) + dev_info(dev, "firmware mux setting of 0x%x overwritten to 0x%x\n", old,= val); + + return 0; +} + +static const struct of_device_id mpfs_irqmux_of_match[] =3D { + { .compatible =3D "microchip,mpfs-irqmux", }, + { } +}; +MODULE_DEVICE_TABLE(of, mpfs_irqmux_of_match); + +static struct platform_driver mpfs_irqmux_driver =3D { + .probe =3D mpfs_irqmux_probe, + .driver =3D { + .name =3D "mpfs_irqmux", + .of_match_table =3D mpfs_irqmux_of_match, + }, +}; +module_platform_driver(mpfs_irqmux_driver); + +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("Polarfire SoC interrupt mux driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Mon Apr 6 18:22:59 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C28233A7F57; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dzq9mikP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 34AD8C19424; Wed, 18 Mar 2026 11:04:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773831902; bh=o5FI3ztoAARK0LLXr0nwisM/p4BnlT3gUgABFxXU9WE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dzq9mikPCRvXNi8WOz6ET+aJeUsKvqy53m6B6Dd6Kudxbr+m2H6RuIJiK9OG3o8w/ VRMuFWWAvsqUDmq3RrSqkeAENaR9Jbi2CpGERLsz6JH9WUdV04abvvuNpGmX5OfNSV lNgSBtPCpOFbOIfNdfjSssa2R7aJmfWnDqqB/msE9sE4/lagiA00kRvV/PN8YfES53 WDHkp3f0kCtFYyQrHhRKmSDyx0p7ykxoBu1K/34OcWX57sqZgrWnkOfYS7BvvI28Ys wt2ZyjTnc4kw0jIOndz6DKbsArQW6rSQMgfSddweFkW4KmYTj0d00oKvg8tdVYbHMe 2DbCbHKSoosLg== From: Conor Dooley To: linux-gpio@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Thomas Gleixner , Herve Codina , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v13 5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC Date: Wed, 18 Mar 2026 11:04:36 +0000 Message-ID: <20260318-urology-arrest-655d9c341130@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260318-gift-nearest-fd3ef3e4819b@spud> References: <20260318-gift-nearest-fd3ef3e4819b@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=17764; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=XWsxtdZxXvcj6PnwDUoVQA8OLlHvYW4uL5uDH6Hr0Bw=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJm72o5WzpoV6B9aVzB9Yv+OqKefzk/afac7omjmhvwT7 9//7ryT2VHKwiDGxSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJyP9jZGjLNv9um2Dzzvfm VkPXeTHVtfNq4hiiZRn3/c1m2sBzjZPhf/YJ9d2WVZM4VvLa+8ntWNIzKW2DqdxOjzSdasvp6+t lGAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley There are 3 GPIO controllers on this SoC, of which: - GPIO controller 0 has 14 GPIOs - GPIO controller 1 has 24 GPIOs - GPIO controller 2 has 32 GPIOs All GPIOs are capable of generating interrupts, for a total of 70. There are only 41 IRQs available however, so a configurable mux is used to ensure all GPIOs can be used for interrupt generation. 38 of the 41 interrupts are in what the documentation calls "direct mode", as they provide an exclusive connection from a GPIO to the PLIC. The 3 remaining interrupts are used to mux the interrupts which do not have a exclusive connection, one for each GPIO controller. The mux was overlooked when the bindings and driver were originally written for the GPIO controllers on Polarfire SoC, and the interrupts property in the GPIO nodes used to try and convey what the mapping was. Instead, the mux should be a device in its own right, and the GPIO controllers should be connected to it, rather than to the PLIC. Now that a binding exists for that mux, fix the inaccurate description of the interrupt controller hierarchy. GPIO controllers 0 and 1 do not have all 32 possible GPIO lines, so ngpios needs to be set to match the number of lines/interrupts. The m100pfsevp has conflicting interrupt mappings for controllers 0 and 2, as they cannot both be using an interrupt in "direct mode" at the same time, so the default replaces this impossible configuration. Reviewed-by: Linus Walleij Signed-off-by: Conor Dooley --- .../boot/dts/microchip/mpfs-beaglev-fire.dts | 29 +++++++++++++ .../boot/dts/microchip/mpfs-disco-kit.dts | 43 +++++++++++++------ .../dts/microchip/mpfs-icicle-kit-common.dtsi | 37 ++++++++++++---- .../boot/dts/microchip/mpfs-m100pfsevp.dts | 41 ++++++++++++------ .../boot/dts/microchip/mpfs-polarberry.dts | 29 +++++++++++++ .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 37 ++++++++++++---- .../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 35 ++++++++++++--- arch/riscv/boot/dts/microchip/mpfs.dtsi | 37 ++++++++++++++-- 8 files changed, 237 insertions(+), 51 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/ris= cv/boot/dts/microchip/mpfs-beaglev-fire.dts index f44ad8e6f4e49..0e1b0b8d394b9 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -164,6 +164,35 @@ imx219_0: endpoint { }; }; =20 +&irqmux { + interrupt-map =3D <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &mac0 { status =3D "okay"; phy-mode =3D "sgmii"; diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/= boot/dts/microchip/mpfs-disco-kit.dts index c068b9bb5bfdf..f769c9d5d7b47 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts @@ -97,24 +97,10 @@ &core_pwm0 { }; =20 &gpio1 { - interrupts =3D <27>, <28>, <29>, <30>, - <31>, <32>, <33>, <47>, - <35>, <36>, <37>, <38>, - <39>, <40>, <41>, <42>, - <43>, <44>, <45>, <46>, - <47>, <48>, <49>, <50>; status =3D "okay"; }; =20 &gpio2 { - interrupts =3D <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; status =3D "okay"; }; =20 @@ -130,6 +116,35 @@ &ihc { status =3D "okay"; }; =20 +&irqmux { + interrupt-map =3D <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &mac0 { phy-mode =3D "sgmii"; phy-handle =3D <&phy0>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index e01a216e6c3a8..e25edc5f3b451 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -77,14 +77,6 @@ &core_pwm0 { }; =20 &gpio2 { - interrupts =3D <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; status =3D "okay"; }; =20 @@ -136,6 +128,35 @@ &ihc { status =3D "okay"; }; =20 +&irqmux { + interrupt-map =3D <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &mac0 { phy-mode =3D "sgmii"; phy-handle =3D <&phy0>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv= /boot/dts/microchip/mpfs-m100pfsevp.dts index a8d623ee9fa4c..86234968df486 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts @@ -52,11 +52,36 @@ &i2c1 { status =3D "okay"; }; =20 +&irqmux { + interrupt-map =3D <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &gpio0 { - interrupts =3D <13>, <14>, <15>, <16>, - <17>, <18>, <19>, <20>, - <21>, <22>, <23>, <24>, - <25>, <26>; ngpios =3D <14>; status =3D "okay"; =20 @@ -75,14 +100,6 @@ mmc-sel-hog { }; =20 &gpio2 { - interrupts =3D <13>, <14>, <15>, <16>, - <17>, <18>, <19>, <20>, - <21>, <22>, <23>, <24>, - <25>, <26>, <27>, <28>, - <29>, <30>, <31>, <32>, - <33>, <34>, <35>, <36>, - <37>, <38>, <39>, <40>, - <41>, <42>, <43>, <44>; status =3D "okay"; }; =20 diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv= /boot/dts/microchip/mpfs-polarberry.dts index ea0808ab10425..510d59153cd07 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -30,6 +30,35 @@ ddrc_cache_hi: memory@1000000000 { }; }; =20 +&irqmux { + interrupt-map =3D <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + /* * phy0 is connected to mac0, but the port itself is on the (optional) car= rier * board. diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/bo= ot/dts/microchip/mpfs-sev-kit.dts index f9a8905794383..8f1908a105671 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts @@ -56,15 +56,36 @@ &i2c0 { status =3D "okay"; }; =20 +&irqmux { + interrupt-map =3D <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &gpio2 { - interrupts =3D <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; status =3D "okay"; }; =20 diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/bo= ot/dts/microchip/mpfs-tysom-m.dts index d1120f5f2c015..bc15530a2979b 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts @@ -69,13 +69,36 @@ hwmon: hwmon@45 { }; }; =20 +&irqmux { + interrupt-map =3D <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &gpio1 { - interrupts =3D <27>, <28>, <29>, <30>, - <31>, <32>, <33>, <47>, - <35>, <36>, <37>, <38>, - <39>, <40>, <41>, <42>, - <43>, <44>, <45>, <46>, - <47>, <48>, <49>, <50>; status =3D "okay"; }; =20 diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 5c2963e269b83..4f0d5bdee3da6 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -254,7 +254,17 @@ pdma: dma-controller@3000000 { mss_top_sysreg: syscon@20002000 { compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; reg =3D <0x0 0x20002000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; #reset-cells =3D <1>; + + irqmux: interrupt-controller@54 { + compatible =3D "microchip,mpfs-irqmux"; + reg =3D <0x54 0x4>; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x7f>; + }; }; =20 sysreg_scb: syscon@20003000 { @@ -471,36 +481,57 @@ mac1: ethernet@20112000 { gpio0: gpio@20120000 { compatible =3D "microchip,mpfs-gpio"; reg =3D <0x0 0x20120000 0x0 0x1000>; - interrupt-parent =3D <&plic>; + interrupt-parent =3D <&irqmux>; interrupt-controller; #interrupt-cells =3D <1>; + interrupts =3D <0>, <1>, <2>, <3>, + <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>, + <12>, <13>; clocks =3D <&clkcfg CLK_GPIO0>; gpio-controller; #gpio-cells =3D <2>; + ngpios =3D <14>; status =3D "disabled"; }; =20 gpio1: gpio@20121000 { compatible =3D "microchip,mpfs-gpio"; reg =3D <0x0 0x20121000 0x0 0x1000>; - interrupt-parent =3D <&plic>; + interrupt-parent =3D <&irqmux>; interrupt-controller; #interrupt-cells =3D <1>; + interrupts =3D <32>, <33>, <34>, <35>, + <36>, <37>, <38>, <39>, + <40>, <41>, <42>, <43>, + <44>, <45>, <46>, <47>, + <48>, <49>, <50>, <51>, + <52>, <53>, <54>, <55>; clocks =3D <&clkcfg CLK_GPIO1>; gpio-controller; #gpio-cells =3D <2>; + ngpios =3D <24>; status =3D "disabled"; }; =20 gpio2: gpio@20122000 { compatible =3D "microchip,mpfs-gpio"; reg =3D <0x0 0x20122000 0x0 0x1000>; - interrupt-parent =3D <&plic>; + interrupt-parent =3D <&irqmux>; interrupt-controller; #interrupt-cells =3D <1>; + interrupts =3D <64>, <65>, <66>, <67>, + <68>, <69>, <70>, <71>, + <72>, <73>, <74>, <75>, + <76>, <77>, <78>, <79>, + <80>, <81>, <82>, <83>, + <84>, <85>, <86>, <87>, + <88>, <89>, <90>, <91>, + <92>, <93>, <94>, <95>; clocks =3D <&clkcfg CLK_GPIO2>; gpio-controller; #gpio-cells =3D <2>; + ngpios =3D <32>; status =3D "disabled"; }; =20 --=20 2.51.0