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There is SM7750 for mobiles and then QC7790S/M for IoT. One of the boards that comes with Eliza SoC is the MTP. So document both the SoC and MTP board compatibles. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d054a8f5632d..458c98d2c2d6 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -61,6 +61,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 =20 + - items: + - enum: + - qcom,eliza-mtp + - const: qcom,eliza + - items: - enum: - qcom,glymur-crd --=20 2.48.1 From nobody Mon Apr 6 18:24:11 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9778B378D9F for ; Wed, 18 Mar 2026 10:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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It comes in different flavors. There is SM7750 for mobiles and then QC7790S/M for IoT. Describe the common parts under a common dtsi. The initial submission enables support for: - CPU nodes with cpufreq and cpuidle support - Global Clock Controller (GCC) - Resource State Coordinator (RSC) with clock controller & genpd provider - Interrupt controller - Power Domain Controller (PDC) - Vendor specific SMMU - SPMI bus arbiter - Top Control and Status Register (TCSR) - Top Level Mode Multiplexer (TLMM) - Debug UART - Reserved memory nodes - Interconnect providers - System timer - UFS Reviewed-by: Dmitry Baryshkov Co-developed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/eliza.dtsi | 1317 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 1317 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom= /eliza.dtsi new file mode 100644 index 000000000000..190f10a77d74 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -0,0 +1,1317 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x0>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3>; + + l3: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x100>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x200>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + l2_2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x300>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_3>; + capacity-dmips-mhz =3D <1792>; + dynamic-power-coefficient =3D <238>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + l2_3: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x400>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_4>; + capacity-dmips-mhz =3D <1792>; + dynamic-power-coefficient =3D <238>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + l2_4: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x500>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_5>; + capacity-dmips-mhz =3D <1792>; + dynamic-power-coefficient =3D <238>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + l2_5: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x600>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_6>; + capacity-dmips-mhz =3D <1792>; + dynamic-power-coefficient =3D <238>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + l2_6: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-x3"; + reg =3D <0x0 0x700>; + + clocks =3D <&cpufreq_hw 2>; + + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_7>; + capacity-dmips-mhz =3D <1894>; + dynamic-power-coefficient =3D <588>; + + qcom,freq-domain =3D <&cpufreq_hw 2>; + + l2_7: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + + core6 { + cpu =3D <&cpu6>; + }; + + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cluster0_c4: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <550>; + exit-latency-us =3D <750>; + min-residency-us =3D <6700>; + }; + + cluster1_c4: cpu-sleep-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <550>; + exit-latency-us =3D <1050>; + min-residency-us =3D <7951>; + }; + + cluster2_c4: cpu-sleep-2 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-plus-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <500>; + exit-latency-us =3D <1350>; + min-residency-us =3D <7480>; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <750>; + exit-latency-us =3D <2350>; + min-residency-us =3D <9144>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x4100b344>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-eliza", "qcom,scm"; + interconnects =3D <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + qcom,dload-mode =3D <&tcsr 0x1a000>; + }; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,eliza-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,eliza-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0xa0000000 0x0 0x0>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster1_c4>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster1_c4>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster1_c4>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster1_c4>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster2_c4>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_0>, + <&cluster_sleep_1>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp@80000000 { + reg =3D <0x0 0x80000000 0x0 0xe00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-mem@80e00000 { + reg =3D <0x0 0x80e00000 0x0 0x40000>; + no-map; + }; + + cpucp_mem: cpucp@81200000 { + reg =3D <0x0 0x81200000 0x0 0x200000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog@81a00000 { + reg =3D <0x0 0x81a00000 0x0 0x40000>; + no-map; + }; + + aop_image_mem: aop-image@81c00000 { + reg =3D <0x0 0x81c00000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ + aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { + reg =3D <0x0 0x81c80000 0x0 0x74000>; + no-map; + }; + + /* Secdata region can be reused by apps */ + smem_mem: smem@81d00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x81d00000 0x0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + cpucp_scandump_mem: cpucp-scandump@82000000 { + reg =3D <0x0 0x82200000 0x0 0x180000>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi@82380000 { + reg =3D <0x0 0x82380000 0x0 0x20000>; + no-map; + }; + + soccp_sdi_mem: soccp-sdi@823a0000 { + reg =3D <0x0 0x823a0000 0x0 0x40000>; + no-map; + }; + + pmic_minii_dump_mem: pmic-minii-dump@823e0000 { + reg =3D <0x0 0x823e0000 0x0 0x80000>; + no-map; + }; + + pvmfw_mem: pvmfw@824a0000 { + reg =3D <0x0 0x824a0000 0x0 0x100000>; + no-map; + }; + + hyp_db_mem: hyp-db@825a0000 { + reg =3D <0x0 0x825a0000 0x0 0x60000>; + no-map; + }; + + global_sync_mem: global-sync@82600000 { + reg =3D <0x0 0x82600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat@82700000 { + reg =3D <0x0 0x82700000 0x0 0x100000>; + no-map; + }; + + qdss_mem: qdss@82800000 { + reg =3D <0x0 0x82800000 0x0 0x2000000>; + no-map; + }; + + dsm_partition_1_mem: dsm-partition-1@84a00000 { + reg =3D <0x0 0x84a00000 0x0 0x3700000>; + no-map; + }; + + mpss_mem: mpss@88100000 { + reg =3D <0x0 0x88100000 0x0 0xcd00000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@94e00000 { + reg =3D <0x0 0x94e00000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@94e80000 { + reg =3D <0x0 0x94e80000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@94e90000 { + reg =3D <0x0 0x94e90000 0x0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code@94e9a000 { + reg =3D <0x0 0x94e9a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera@94f00000 { + reg =3D <0x0 0x94f00000 0x0 0x800000>; + no-map; + }; + + camera_2_mem: camera-2@95700000 { + reg =3D <0x0 0x95700000 0x0 0x800000>; + no-map; + }; + + video_mem: video@95f00000 { + reg =3D <0x0 0x95f00000 0x0 0x800000>; + no-map; + }; + + soccp_mem: soccp@96700000 { + reg =3D <0x0 0x96700000 0x0 0x180000>; + no-map; + }; + + wpss_mem: wpss@97000000 { + reg =3D <0x0 0x97000000 0x0 0x1900000>; + no-map; + }; + + cdsp_mem: cdsp@98900000 { + reg =3D <0x0 0x98900000 0x0 0x1400000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@99d00000 { + reg =3D <0x0 0x99d00000 0x0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@99d80000 { + reg =3D <0x0 0x99d80000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi@99e00000 { + reg =3D <0x0 0x99e00000 0x0 0x2a00000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@a6400000 { + reg =3D <0x0 0xa6400000 0x0 0xc00000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump@b8000000 { + reg =3D <0x0 0xb8000000 0x0 0x1c0000>; + no-map; + }; + + /* Merged tz_reserved, xbl_sc, and qtee regions */ + tz_merged_mem: tz-merged@d8000000 { + reg =3D <0x0 0xd8000000 0x0 0x600000>; + no-map; + }; + + trust_ui_vm_mem: trust-ui-vm@f3800000 { + reg =3D <0x0 0xf3800000 0x0 0x4400000>; + no-map; + }; + + oem_vm_mem: oem-vm@f7c00000 { + reg =3D <0x0 0xf7c00000 0x0 0x4c00000>; + no-map; + }; + + llcc_lpi_mem: llcc-lpi@ff800000 { + reg =3D <0x0 0xff800000 0x0 0x180000>; + no-map; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,eliza-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f4200>; + + clocks =3D <&bi_tcxo_div2>, + <&sleep_clk>, + <0>, + <0>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <0>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + qupv3_2: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0x423 0x0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + uart14: serial@894000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart14_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + config_noc: interconnect@1600000 { + compatible =3D "qcom,eliza-cnoc-cfg"; + reg =3D <0x0 0x01600000 0x0 0x5200>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + cnoc_main: interconnect@1500000 { + compatible =3D "qcom,eliza-cnoc-main"; + reg =3D <0x0 0x01500000 0x0 0x16080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,eliza-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x40000>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + pcie_noc: interconnect@16c0000 { + compatible =3D "qcom,eliza-pcie-anoc"; + reg =3D <0x0 0x016c0000 0x0 0x11400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + #interconnect-cells =3D <2>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible =3D "qcom,eliza-aggre1-noc"; + reg =3D <0x0 0x016e0000 0x0 0x16400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + #interconnect-cells =3D <2>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,eliza-aggre2-noc"; + reg =3D <0x0 0x01700000 0x0 0x1f400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&rpmhcc RPMH_IPA_CLK>; + #interconnect-cells =3D <2>; + }; + + mmss_noc: interconnect@1780000 { + compatible =3D "qcom,eliza-mmss-noc"; + reg =3D <0x0 0x01780000 0x0 0x7d800>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + ufs_mem_phy: phy@1d80000 { + compatible =3D "qcom,eliza-qmp-ufs-phy", + "qcom,sm8650-qmp-ufs-phy"; + reg =3D <0x0 0x01d80000 0x0 0x2000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + + clock-names =3D "ref", + "ref_aux", + "qref"; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + power-domains =3D <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible =3D "qcom,eliza-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>, + <0x0 0x01da0000 0x0 0x15000>; + reg-names =3D "std", + "mcq"; + + interrupts =3D ; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 =3D <&ufs_opp_table>; + + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x60 0x0>; + dma-coherent; + + lanes-per-direction =3D <2>; + qcom,ice =3D <&ice>; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + #reset-cells =3D <1>; + + status =3D "disabled"; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz =3D /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-403000000 { + opp-hz =3D /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + ice: crypto@1d88000 { + compatible =3D "qcom,eliza-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x01d88000 0x0 0x18000>; + + clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: clock-controller@1fbf000 { + compatible =3D "qcom,eliza-tcsr", "syscon"; + reg =3D <0x0 0x01fbf000 0x0 0x21000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible =3D "qcom,eliza-lpass-ag-noc"; + reg =3D <0x0 0x07e40000 0x0 0xe080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible =3D "qcom,eliza-lpass-lpiaon-noc"; + reg =3D <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible =3D "qcom,eliza-lpass-lpicx-noc"; + reg =3D <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,eliza-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x40000>, + <0x0 0x174000f0 0x0 0x64>; + + qcom,pdc-ranges =3D <0 480 8>, <8 719 1>, <9 718 1>, + <10 230 1>, <11 724 1>, <12 716 1>, + <13 727 1>, <14 720 1>, <15 726 1>, + <16 721 1>, <17 262 1>, <18 70 1>, + <19 723 1>, <20 234 1>, <22 725 1>, + <23 231 1>, <24 504 5>, <30 510 8>, + <40 520 6>, <51 531 4>, <58 538 2>, + <61 541 5>, <66 92 1>, <67 547 13>, + <80 240 1>, <81 235 1>, <82 310 2>, + <84 248 1>, <85 241 1>, <86 238 2>, + <88 254 1>, <89 509 1>, <90 563 1>, + <91 259 2>, <93 201 1>, <94 246 1>, + <95 93 1>, <96 611 29>, <125 63 1>, + <126 366 2>, <128 374 1>, <129 377 1>, + <130 428 1>, <131 434 2>, <133 437 1>, + <134 452 2>, <136 458 2>, <138 464 11>, + <149 671 1>, <150 688 1>, <151 714 2>, + <153 722 1>, <154 255 1>, <155 269 2>, + <157 276 1>, <158 287 1>, <159 306 4>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + spmi: arbiter@c400000 { + compatible =3D "qcom,eliza-spmi-pmic-arb", + "qcom,x1e80100-spmi-pmic-arb"; + reg =3D <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x400000>, + <0 0x0c440000 0 0x80000>; + reg-names =3D "core", "chnls", "obsrvr"; + + qcom,ee =3D <0>; + qcom,channel =3D <0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + spmi_bus0: spmi@c42d000 { + reg =3D <0 0x0c42d000 0 0x4000>, + <0 0x0c4c0000 0 0x10000>; + reg-names =3D "cnfg", "intr"; + + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells =3D <4>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + spmi_bus1: spmi@c432000 { + reg =3D <0 0x0c432000 0 0x4000>, + <0 0x0c4d0000 0 0x10000>; + reg-names =3D "cnfg", "intr"; + + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells =3D <4>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x15000000 0x0 0x100000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + + dma-coherent; + }; + + intc: interrupt-controller@17100000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17100000 0x0 0x10000>, + <0x0 0x17180000 0x0 0x200000>; + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x40000>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: msi-controller@17140000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17140000 0x0 0x40000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + + interrupts =3D , + , + ; + + power-domains =3D <&cluster_pd>; + label =3D "apps_rsc"; + + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,eliza-rpmh-clk"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,eliza-rpmhpd"; + + operating-points-v2 =3D <&rpmhpd_opp_table>; + + #power-domain-cells =3D <1>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d3: opp-50 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l2: opp-224 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l2: opp-432 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l3: opp-448 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l4: opp-452 { + opp-level =3D ; + }; + + rpmhpd_opp_super_turbo_no_cpr: opp-480 { + opp-level =3D ; + }; + }; + }; + }; + + epss_l3: interconnect@17d90000 { + compatible =3D "qcom,eliza-epss-l3", "qcom,epss-l3"; + reg =3D <0x0 0x17d90000 0x0 0x1000>; + + clocks =3D <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + + #interconnect-cells =3D <1>; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible =3D "qcom,eliza-cpufreq-epss", "qcom,cpufreq-epss"; + reg =3D <0x0 0x17d91000 0x0 0x1000>, + <0x0 0x17d92000 0x0 0x1000>, + <0x0 0x17d93000 0x0 0x1000>; + reg-names =3D "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts =3D , + , + ; + interrupt-names =3D "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks =3D <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,eliza-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0xf00000>; + + interrupts =3D ; + + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio-ranges =3D <&tlmm 0 0 184>; + wakeup-parent =3D <&pdc>; + + qup_uart14_default: qup-uart14-default-state { + /* TX, RX */ + pins =3D "gpio18", "gpio19"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + gem_noc: interconnect@24100000 { + compatible =3D "qcom,eliza-gem-noc"; + reg =3D <0x0 0x24100000 0x0 0x163080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + nsp_noc: interconnect@320c0000 { + compatible =3D "qcom,eliza-nsp-noc"; + reg =3D <0x0 0x320c0000 0x0 0xe080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + + interrupts =3D , + , + , + ; + }; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Authority-Analysis: v=2.4 cv=bIcb4f+Z c=1 sm=1 tr=0 ts=69ba7c48 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=iKs3dpp2RB4k51ZqCjcyjQ==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=hvA-L96QmkH1ykFoo1wA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: PHJow_GBEaBpZ8Lp59ZpOMhEXCY_RHAq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDA4NiBTYWx0ZWRfXz7Tvr/zirJ6R ao5CPgu88ikQHXNDl5+ScKYwAyCCYfsDyWX1gFtWTqsGPIdfEaUWA8F6v8NQ58g8+qqnoiChDfs nnyZtYW1mIGmYbE682at3088Y+aIhbC5XEuXN557XSuYzRQxsx0AXsqlgHP9sT12SCvCzEElquP p8+VzEbj0WkdGFmBRSZWXb50nldGhqBo9dEacuDG0eCMw+XiI468jILUfP7j+93+RIZIeKFykWQ 21iqV0mjYVlDHKyM4tCC3+BBknFKin51jZZx5TNU4H063KeXULUxDlhnqw7vE3203CM8xLoSPVq adnI6cyCmCqrzgVv2aB+SQw9P9pFtof4PYRZ/egpR1AoSb9kQ332UftasawHZDwIAmsoW2pp1ij VLzaO+GESLST6E9s6vlyqdQcl/g6IGrlNsKPVa813AbcTFCAVk68jBvEuFSMHFRzpsNirKvVDR1 FBhTUU0uFdTRPn/aA5A== X-Proofpoint-GUID: PHJow_GBEaBpZ8Lp59ZpOMhEXCY_RHAq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-18_01,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180086 The MTP is a one of the boards that comes with the Eliza SoC. So add dedicated board dts for it. The initial support enables: - UART debug console - Ob-board UFS storage - Qualcomm RPMh regulators (PMIC) and VPH_PWR - board specific clocks & reserved GPIO ranges Co-developed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/eliza-mtp.dts | 407 +++++++++++++++++++++++++++++= ++++ 2 files changed, 408 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 02921a495b2c..e4dc0aab3bf6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D apq8094-sony-xperia-kitakami= -karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096sg-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D eliza-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-iot-evk.dtb =20 diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/q= com/eliza-mtp.dts new file mode 100644 index 000000000000..90f629800cb0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include "eliza.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Eliza MTP"; + compatible =3D "qcom,eliza-mtp", "qcom,eliza"; + chassis-type =3D "handset"; + + aliases { + serial0 =3D &uart14; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <76800000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm7550-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3b>; + vdd-l2-l3-supply =3D <&vreg_s3b>; + vdd-l4-l5-supply =3D <&vreg_s2b>; + vdd-l6-supply =3D <&vreg_s2b>; + vdd-l7-supply =3D <&vreg_s1b>; + vdd-l8-supply =3D <&vreg_s1b>; + vdd-l9-l10-supply =3D <&vreg_s1b>; + vdd-l11-supply =3D <&vreg_s1b>; + vdd-l12-l14-supply =3D <&vreg_bob>; + vdd-l13-l16-supply =3D <&vreg_bob>; + vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply =3D <&vreg_bob>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + vdd-bob-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "b"; + + vreg_s1b: smps1 { + regulator-name =3D "vreg_s1b"; + regulator-min-microvolt =3D <1850000>; + regulator-max-microvolt =3D <2040000>; + regulator-initial-mode =3D ; + }; + + vreg_s2b: smps2 { + regulator-name =3D "vreg_s2b"; + regulator-min-microvolt =3D <375000>; + regulator-max-microvolt =3D <2744000>; + regulator-initial-mode =3D ; + }; + + vreg_s3b: smps3 { + regulator-name =3D "vreg_s3b"; + regulator-min-microvolt =3D <375000>; + regulator-max-microvolt =3D <2744000>; + regulator-initial-mode =3D ; + }; + + vreg_s4b: smps4 { + regulator-name =3D "vreg_s4b"; + regulator-min-microvolt =3D <2156000>; + regulator-max-microvolt =3D <2400000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b: ldo2 { + regulator-name =3D "vreg_l2b"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + }; + + vreg_l3b: ldo3 { + regulator-name =3D "vreg_l3b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l4b: ldo4 { + regulator-name =3D "vreg_l4b"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l6b: ldo6 { + regulator-name =3D "vreg_l6b"; + regulator-min-microvolt =3D <866000>; + regulator-max-microvolt =3D <958000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b: ldo7 { + regulator-name =3D "vreg_l7b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b: ldo8 { + regulator-name =3D "vreg_l8b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b: ldo9 { + regulator-name =3D "vreg_l9b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b: ldo10 { + regulator-name =3D "vreg_l10b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11b: ldo11 { + regulator-name =3D "vreg_l11b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b: ldo12 { + regulator-name =3D "vreg_l12b"; + /* Voltage range for UFS 3.x and above */ + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l13b: ldo13 { + regulator-name =3D "vreg_l13b"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b: ldo14 { + regulator-name =3D "vreg_l14b"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b: ldo15 { + regulator-name =3D "vreg_l15b"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + + vreg_l16b: ldo16 { + regulator-name =3D "vreg_l16b"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b: ldo17 { + regulator-name =3D "vreg_l17b"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + }; + + vreg_l18b: ldo18 { + regulator-name =3D "vreg_l18b"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l19b: ldo19 { + regulator-name =3D "vreg_l19b"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + }; + + vreg_l20b: ldo20 { + regulator-name =3D "vreg_l20b"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l21b: ldo21 { + regulator-name =3D "vreg_l21b"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l22b: ldo22 { + regulator-name =3D "vreg_l22b"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + }; + + vreg_l23b: ldo23 { + regulator-name =3D "vreg_l23b"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_bob: bob { + regulator-name =3D "vreg_bob"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s2b>; + + qcom,pmic-id =3D "d"; + + vreg_l1d: ldo1 { + regulator-name =3D "vreg_l1d"; + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s2b>; + vdd-l3-supply =3D <&vreg_s2b>; + + qcom,pmic-id =3D "g"; + + vreg_l1g: ldo1 { + regulator-name =3D "vreg_l1g"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + }; + + vreg_l3g: ldo3 { + regulator-name =3D "vreg_l3g"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + }; + + }; + + regulators-3 { + compatible =3D "qcom,pmr735d-rpmh-regulators"; + + vdd-l1-l2-l5-supply =3D <&vreg_s3b>; + vdd-l3-l4-supply =3D <&vreg_s2b>; + vdd-l6-supply =3D <&vreg_s1b>; + vdd-l7-supply =3D <&vreg_s3b>; + + qcom,pmic-id =3D "k"; + + vreg_l1k: ldo1 { + regulator-name =3D "vreg_l1k"; + regulator-min-microvolt =3D <488000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l2k: ldo2 { + regulator-name =3D "vreg_l2k"; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <969000>; + regulator-initial-mode =3D ; + }; + + vreg_l3k: ldo3 { + regulator-name =3D "vreg_l3k"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D ; + }; + + vreg_l4k: ldo4 { + regulator-name =3D "vreg_l4k"; + regulator-min-microvolt =3D <960000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + }; + + vreg_l5k: ldo5 { + regulator-name =3D "vreg_l5k"; + regulator-min-microvolt =3D <866000>; + regulator-max-microvolt =3D <931000>; + regulator-initial-mode =3D ; + }; + + vreg_l6k: ldo6 { + regulator-name =3D "vreg_l6k"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l7k: ldo7 { + regulator-name =3D "vreg_l7k"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <958000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <20 4>, /* NFC SPI */ + <111 2>, /* WCN UART1 */ + <118 1>; /* NFC Secure I/O */ +}; + +&uart14 { + compatible =3D "qcom,geni-debug-uart"; + + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 185 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l12b>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1d>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l6b>; + vdda-pll-supply =3D <&vreg_l4b>; + + status =3D "okay"; +}; --=20 2.48.1