From nobody Mon Apr 6 14:59:12 2026 Received: from mail-24416.protonmail.ch (mail-24416.protonmail.ch [109.224.244.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 431FC2D7810; Thu, 19 Mar 2026 04:00:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773892809; cv=none; b=HWgL6rrjI0mVA/x5K/wQVJobRC82gxCriLQqOdnSlcasgrele9hOnMT4GKSq9ZN/WPSRKBOel9nZezejyn96+pihB6hoogrqtPWEZbxA8wdUd+mR1fs5x2ij8I/MK7ecaqd3hQJMc/I5LpnxzwqPj9IUMfjFL4AnC0guT58IFMc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773892809; c=relaxed/simple; bh=dD/BPKC5aT9eeNrRI4lDwbK6ytFidptagGuSLLMES4o=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QpC09eJAbdsmwq0ZC633XGsTkkPiwtKcU4eZHs4AzSpNwOAN8pVKghwaRBsUHOK6PE72Wlb0uS9sqdE+yUcuVZIM4oIGTMb5RZMmkLCnIQL45MR7KcNeM0JRzxVHY11IgWPQ8m99xwBzXy96PKpcjbgbaB+jebsxidO7poZ1nRs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=QfPzEGli; arc=none smtp.client-ip=109.224.244.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="QfPzEGli" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773892806; x=1774152006; bh=dD/BPKC5aT9eeNrRI4lDwbK6ytFidptagGuSLLMES4o=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=QfPzEGliEXKb8VbfjeqZep2AZal6LNwmNkzmhnHj5N+JxyBuw0LTlI/64MruOC90J 1WQEZRfpRCnLJnmyLs4gf7xZ0IysuKkOMGwsgrdXAvcxByXDgJeZ3NXXvQ0K3aSAoy dg7G8TlimFMYCNFEnRMsL/GiPx3B8vCL0q8lB4HdHLKSOt4jLL0fvp+oRi8hHqfErr ZDVcvC8a0Dgpt+j5O6wg6K5wsVkPN/mV0AoHBKCoRDGTw9BizvH3+p3Wprog7WIefl 90Aj5LhzTFm6pPK6adLWgsxs0ShmyDApiVdgDEElY8CETET2Tc6VbLkW2pKQJ8CEqa KRznc3Yjs13jg== Date: Thu, 19 Mar 2026 04:00:01 +0000 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten From: Alexander Koskovich Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Dmitry Baryshkov Subject: [PATCH v2 1/3] drm/mipi-dsi: add RGB101010 pixel format Message-ID: <20260318-dsi-rgb101010-support-v2-1-698b7612eaeb@pm.me> In-Reply-To: <20260318-dsi-rgb101010-support-v2-0-698b7612eaeb@pm.me> References: <20260318-dsi-rgb101010-support-v2-0-698b7612eaeb@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 885ab5d382f2949f45e29c33c5f5c86b683a34c0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MIPI_DSI_FMT_RGB101010 for 30 bit (10,10,10 RGB) pixel format, corresponding to the packed 30 bit pixel stream defined in MIPI DSI v1.3 Section 8.8.17. Reviewed-by: Dmitry Baryshkov Signed-off-by: Alexander Koskovich --- include/drm/drm_mipi_dsi.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 3aba7b380c8d..a822e9e876af 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -140,6 +140,7 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(str= uct device_node *node); #define MIPI_DSI_HS_PKT_END_ALIGNED BIT(12) =20 enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB101010, MIPI_DSI_FMT_RGB888, MIPI_DSI_FMT_RGB666, MIPI_DSI_FMT_RGB666_PACKED, @@ -235,6 +236,9 @@ extern const struct bus_type mipi_dsi_bus_type; static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format = fmt) { switch (fmt) { + case MIPI_DSI_FMT_RGB101010: + return 30; + case MIPI_DSI_FMT_RGB888: case MIPI_DSI_FMT_RGB666: return 24; --=20 2.53.0 From nobody Mon Apr 6 14:59:12 2026 Received: from mail-43101.protonmail.ch (mail-43101.protonmail.ch [185.70.43.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF2BB3019D7 for ; Thu, 19 Mar 2026 04:00:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773892815; cv=none; b=HJGKzfCQlhUYcX9DKHM0Xj1mtn6zPRyBUK1Jj1bDHnWLtaTT+GzPo3xCo5tGtDqyXcvtvKrOuT6rdN//1yVhPe8mnzSch3mexyCerozMcAzLkkRMMUdOiQVjUAIGIMtFJj9yoDgOctdGzdIaippSTamR2Nwkq15ndIv9c8Wvqxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773892815; c=relaxed/simple; bh=KytQ7DJApb7Lu6sR9iaCe4J/geuHSwUOzeOrHrLg7EQ=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GfHy1Yvr1wSie6mdnQPuC1nnGuurQSwiSETlFq14aag5JJjxWiJsGcX9N//Lva0ZJJYj1EuaLfngxyoiwJekim43sBgPIyDqLocndjeXqZPzvrcY9ylr/bkzh2+n4XvPvIhbDEmUZXnjvMWddWRJ+o/Ac2Gh14bg0L7S4B1uWAM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=bRiJ6h6G; arc=none smtp.client-ip=185.70.43.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="bRiJ6h6G" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773892810; x=1774152010; bh=FIhqYnvDqEqh4gLmHXirrSB58x2I5CZdQyjrMqWKARE=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=bRiJ6h6GjafcuLXpdRNN3yMXVTX20R+K1o6gxuUj94OzzguM7/st66UTjCRNLI6xz yqgSDgQjUQZFHd/mUj78CJCaPTYNJBUBAT4mm7QmXGBGYL5hk6Eq9Vq46oIDtfHfi+ tRZ8Jsj942bc99Mpl/ItCyUU79AtsWqokxOyfBXOd/aeS4ZuV1Dk+UjDjnnp4z+lqp orPkXRyFXZ3ECYTptRCX5DsdVg9Ybfqi1UBshyzFwEsanDbDUEvf+rTChXYvjN9/s4 cWDp9RhxDf/Zn2E1Q2CORzbUoTKb0CXx9rs5/djmOoMmeCaa13cIcZq48aGtZ8HYnI A13F6Mc0xCyRw== Date: Thu, 19 Mar 2026 04:00:05 +0000 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten From: Alexander Koskovich Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich Subject: [PATCH v2 2/3] drm/msm/dsi: Add support for RGB101010 pixel format Message-ID: <20260318-dsi-rgb101010-support-v2-2-698b7612eaeb@pm.me> In-Reply-To: <20260318-dsi-rgb101010-support-v2-0-698b7612eaeb@pm.me> References: <20260318-dsi-rgb101010-support-v2-0-698b7612eaeb@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 333f197c982a3645d0cf94f99cb8a44c643d3a4c Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add video and command mode destination format mappings for RGB101010, and extend the VID_CFG0 DST_FORMAT bitfield to 3 bits to accommodate the new format value. Make sure this is guarded behind MSM_DSI_6G_VER >=3D V2.1.0 as anything older does not support this. Required for 10 bit panels such as the BOE BF068MWM-TD0. Signed-off-by: Alexander Koskovich Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 8 ++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 9 +++++++++ drivers/gpu/drm/msm/registers/display/dsi.xml | 5 ++++- 4 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/ds= i_cfg.c index bd3c51c350e7..6a7ea2183a3b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -133,6 +133,7 @@ static const struct msm_dsi_config msm8998_dsi_cfg =3D { .io_start =3D { { 0xc994000, 0xc996000 }, }, + .has_rgb30 =3D true, }; =20 static const char * const dsi_sdm660_bus_clk_names[] =3D { @@ -152,6 +153,7 @@ static const struct msm_dsi_config sdm660_dsi_cfg =3D { .io_start =3D { { 0xc994000, 0xc996000 }, }, + .has_rgb30 =3D true, }; =20 static const char * const dsi_v2_4_clk_names[] =3D { @@ -173,6 +175,7 @@ static const struct msm_dsi_config sdm845_dsi_cfg =3D { { 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */ { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */ }, + .has_rgb30 =3D true, }; =20 static const struct regulator_bulk_data sm8550_dsi_regulators[] =3D { @@ -188,6 +191,7 @@ static const struct msm_dsi_config sm8550_dsi_cfg =3D { .io_start =3D { { 0xae94000, 0xae96000 }, }, + .has_rgb30 =3D true, }; =20 static const struct regulator_bulk_data sm8650_dsi_regulators[] =3D { @@ -203,6 +207,7 @@ static const struct msm_dsi_config sm8650_dsi_cfg =3D { .io_start =3D { { 0xae94000, 0xae96000 }, }, + .has_rgb30 =3D true, }; =20 static const struct msm_dsi_config kaanapali_dsi_cfg =3D { @@ -214,6 +219,7 @@ static const struct msm_dsi_config kaanapali_dsi_cfg = =3D { .io_start =3D { { 0x9ac0000, 0x9ac3000 }, }, + .has_rgb30 =3D true, }; =20 static const struct regulator_bulk_data sc7280_dsi_regulators[] =3D { @@ -230,6 +236,7 @@ static const struct msm_dsi_config sc7280_dsi_cfg =3D { .io_start =3D { { 0xae94000, 0xae96000 }, }, + .has_rgb30 =3D true, }; =20 static const struct regulator_bulk_data sa8775p_dsi_regulators[] =3D { @@ -246,6 +253,7 @@ static const struct msm_dsi_config sa8775p_dsi_cfg =3D { .io_start =3D { { 0xae94000, 0xae96000 }, }, + .has_rgb30 =3D true, }; =20 static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops =3D { diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/ds= i_cfg.h index 5dc812028bd5..15cb9b46fadf 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -48,6 +48,7 @@ struct msm_dsi_config { const char * const *bus_clk_names; const int num_bus_clks; const resource_size_t io_start[VARIANTS_MAX][DSI_MAX]; + bool has_rgb30; }; =20 struct msm_dsi_host_cfg_ops { diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index db6da99375a1..34fd0dc5f7c7 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -757,6 +757,7 @@ static inline enum dsi_vid_dst_format dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt) { switch (mipi_fmt) { + case MIPI_DSI_FMT_RGB101010: return VID_DST_FORMAT_RGB101010; case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; @@ -769,6 +770,7 @@ static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt) { switch (mipi_fmt) { + case MIPI_DSI_FMT_RGB101010: return CMD_DST_FORMAT_RGB101010; case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; case MIPI_DSI_FMT_RGB666_PACKED: case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; @@ -1698,6 +1700,13 @@ static int dsi_host_attach(struct mipi_dsi_host *hos= t, if (dsi->lanes > msm_host->num_data_lanes) return -EINVAL; =20 + if (dsi->format =3D=3D MIPI_DSI_FMT_RGB101010 && + !msm_host->cfg_hnd->cfg->has_rgb30) { + DRM_DEV_ERROR(&msm_host->pdev->dev, + "RGB101010 not supported on this DSI controller\n"); + return -EINVAL; + } + msm_host->channel =3D dsi->channel; msm_host->lanes =3D dsi->lanes; msm_host->format =3D dsi->format; diff --git a/drivers/gpu/drm/msm/registers/display/dsi.xml b/drivers/gpu/dr= m/msm/registers/display/dsi.xml index c7a7b633d747..e40125f75175 100644 --- a/drivers/gpu/drm/msm/registers/display/dsi.xml +++ b/drivers/gpu/drm/msm/registers/display/dsi.xml @@ -15,6 +15,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> + @@ -39,6 +40,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> + @@ -142,7 +144,8 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> - + + --=20 2.53.0 From nobody Mon Apr 6 14:59:12 2026 Received: from mail-24416.protonmail.ch (mail-24416.protonmail.ch [109.224.244.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32B3518AE2 for ; Thu, 19 Mar 2026 04:00:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773892816; cv=none; b=thYV9/TklkYiCIXbbiLprvnxiv0fbdb+RGAU0DwrgPY6NkTaTJN5LPW7ccC8MOfDpiwwJcaojSNEYjxrf1jdAZ6eI5onoCjp+NnqouTjmDsaX1oiKhpC7fNZphogTPTHHrV5Ls5FQzwh6LvulON2MZLO1pil1GIhINoVLS1vB9c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773892816; c=relaxed/simple; bh=aWHEptyM6a+34VtSHTwQvgBH2GrR4Nymj/lmmVkwGGY=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DdQXmOZ1+NBIcgV7OFHJpMkaYAM23UWwYYgY/ykN5ISwtJfaNlTZzhVuCUjumT8xgmIXq51PY1aUMVd/dXem12b75FQXY3R3K19qHtVpCMetkqyTJCvrpCY4wtP8SUG0ihxFPIKN5gu11PvZjmXhJXhZffT6Cs9iTCez0cPrOJw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=UhN5bDBk; arc=none smtp.client-ip=109.224.244.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="UhN5bDBk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773892813; x=1774152013; bh=pp3XZb0ALhTP7LyMnVusUzUvvZEvNzyavN4uuB4T2gk=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=UhN5bDBkmCfcdNt97E/HL8JATOmsyaFSgw+ELopBn/kg/8n1woYK7qjqYW5325CVL MQ/dF4ECsvnLl75Cg7eyHLCwLahfPOrT/KbpSVlYPVZMFmdh/vM+MyfyBPgSUC/rS2 P/ZlEkVcyiaVV5fna0WCp6oaYtHlzdnSHOzt4m6b2UnPDDlE9VPDf9EdgFmn16D3XH MDMDOpU+qTobcQBoK5esly3rZEXoQQ2aKQ0RGSaYe6uPAO1k/jg+8V7CJ06afDwP4c xWmle+lJrtROenaqrANYcMyjUILJ4RxXRzasC3vtqVUg0EP4Vhq/wy/LH1eoLewVKw vU/4+7nNTJvUg== Date: Thu, 19 Mar 2026 04:00:09 +0000 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten From: Alexander Koskovich Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich Subject: [PATCH v2 3/3] drm/msm/dpu: fix video mode DSC INTF timing width for non 8 bit panels Message-ID: <20260318-dsi-rgb101010-support-v2-3-698b7612eaeb@pm.me> In-Reply-To: <20260318-dsi-rgb101010-support-v2-0-698b7612eaeb@pm.me> References: <20260318-dsi-rgb101010-support-v2-0-698b7612eaeb@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 238f0046d0e42c76ca9eb882573e2f3d001a8b53 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Using bits_per_component * 3 as the divisor for the compressed INTF timing width produces constant FIFO errors for panels such as the BOE BF068MWM-TD0 which is a 10 bit panel. The downstream driver calculates the compressed timing width by dividing the total compressed bytes per line by 3 which does not depend on bits_per_component. Switch the divisor to 24 to match downstream. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 0ba777bda253..9b046a0e77aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -122,19 +122,21 @@ static void drm_mode_to_intf_timing_params( } =20 /* - * for DSI, if compression is enabled, then divide the horizonal active - * timing parameters by compression ratio. bits of 3 components(R/G/B) - * is compressed into bits of 1 pixel. + * For DSI, if DSC is enabled, use a fixed divisor of 24 rather than + * bits_per_component * 3 when calculating the compressed timing width. + * + * This matches the downstream driver and is required for panels with + * bits_per_component !=3D 8. */ if (phys_enc->hw_intf->cap->type !=3D INTF_DP && timing->compression_en) { struct drm_dsc_config *dsc =3D dpu_encoder_get_dsc_config(phys_enc->parent); + /* * TODO: replace drm_dsc_get_bpp_int with logic to handle * fractional part if there is fraction */ - timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / - (dsc->bits_per_component * 3); + timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / 24; timing->xres =3D timing->width; } } --=20 2.53.0