From nobody Mon Apr 6 20:00:42 2026 Received: from mail-43103.protonmail.ch (mail-43103.protonmail.ch [185.70.43.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA2433A63F9 for ; Wed, 18 Mar 2026 09:41:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.103 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773826887; cv=none; b=Mh1frTBPwGQl5M2P51CXaKGygeWkyrICmZ1/c7XYxoBD+e+N5xgG36+7JGQ1VmszQR98r1/LO1c6+JVr+FIAkbBcwjoEjPlkhjMSZQDemkGDcAWGp8XhWGEBy4+4mjRxsR6upm9rkk+5/Mly3Kq0xklQlS3HrtVCPro2HBLHEUc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773826887; c=relaxed/simple; bh=aWHEptyM6a+34VtSHTwQvgBH2GrR4Nymj/lmmVkwGGY=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tK+Leow4X4DZBYbC8q22/NmhbtcDIxMnsaYm+U8bnltP/iFlZYOln8SyhBbT7hmGRYrzP/cDLXwoTdM/hOXTmVrXxm/aiRCQhFfsf5nzcZ4U3+UvOG9cwVx6UMw+SLE3TXg7EtkpNoKcggVjMKZ+y8fQTZqLBs+j6hfNIvzBlxA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=TgCZIB3F; arc=none smtp.client-ip=185.70.43.103 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="TgCZIB3F" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773826872; x=1774086072; bh=pp3XZb0ALhTP7LyMnVusUzUvvZEvNzyavN4uuB4T2gk=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=TgCZIB3FYcuhgLiyqxCnROt5SGZHW2ZV8qQddZd18qOJVzdSwxjMWNA3n2L33r3Kr gRvXQdzzzSw4M/Tysrbp9S8j9Eq4IV8u9jHpC6cL/rREJOpEdV642dSzOvVye7eBOD DG5QFLsXJuj7BDQcJG+Moc79u/mep3yUVrtqilAeWbz8G9jRxiE+qxwT2wbujAVU4S 1dfn72rfiokGqOGcBoTrzF7IgfP7ffv5k7ln4QK622S82ucCuf7KCBXmiB04AO+h0N viSgKpaDH0AZm5ARdTgw0JgD4d0/irXbwWnZx6ng6P0wfFahBG7VHreGa5rL6lFBNx /w5UneVSx1d0Q== Date: Wed, 18 Mar 2026 09:41:09 +0000 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten From: Alexander Koskovich Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich Subject: [PATCH 3/3] drm/msm/dpu: fix video mode DSC INTF timing width for non 8 bit panels Message-ID: <20260318-dsi-rgb101010-support-v1-3-6021eb79e796@pm.me> In-Reply-To: <20260318-dsi-rgb101010-support-v1-0-6021eb79e796@pm.me> References: <20260318-dsi-rgb101010-support-v1-0-6021eb79e796@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 00294e59a403e87f8b55690d224023b92ed5dd9a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Using bits_per_component * 3 as the divisor for the compressed INTF timing width produces constant FIFO errors for panels such as the BOE BF068MWM-TD0 which is a 10 bit panel. The downstream driver calculates the compressed timing width by dividing the total compressed bytes per line by 3 which does not depend on bits_per_component. Switch the divisor to 24 to match downstream. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 0ba777bda253..9b046a0e77aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -122,19 +122,21 @@ static void drm_mode_to_intf_timing_params( } =20 /* - * for DSI, if compression is enabled, then divide the horizonal active - * timing parameters by compression ratio. bits of 3 components(R/G/B) - * is compressed into bits of 1 pixel. + * For DSI, if DSC is enabled, use a fixed divisor of 24 rather than + * bits_per_component * 3 when calculating the compressed timing width. + * + * This matches the downstream driver and is required for panels with + * bits_per_component !=3D 8. */ if (phys_enc->hw_intf->cap->type !=3D INTF_DP && timing->compression_en) { struct drm_dsc_config *dsc =3D dpu_encoder_get_dsc_config(phys_enc->parent); + /* * TODO: replace drm_dsc_get_bpp_int with logic to handle * fractional part if there is fraction */ - timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / - (dsc->bits_per_component * 3); + timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / 24; timing->xres =3D timing->width; } } --=20 2.53.0