From nobody Mon Apr 6 18:27:12 2026 Received: from mail-05.mail-europe.com (mail-05.mail-europe.com [85.9.206.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E1823ACA5E for ; Wed, 18 Mar 2026 09:41:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=85.9.206.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773826881; cv=none; b=f/TQNadE/8rHoG7f8Z6fgZtOUon10o9yIalj+Eq3xtVjxT9RIJWF2aR70KZLMXLGC8pmjchQPNv0fvC1wmMC2l/lT+NN/3sI7oHi1JKZ5kbOAyL98zxR7u71wzIpmKUQ8Aa8iHCkFx5xUP2y+NOUg+df6U3wEVcVlWH0TH0gPJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773826881; c=relaxed/simple; bh=e8BFK1m08UzgrYFFBt6dCGTjWCawWzRQ5mu9DCpAQCg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uou20wIhjdZTKIJZTtrkdIqCfzE0QjztY9wUe6mBVT/ZO5+UzQliiuUYNgSChKZqWuIC9sJG1VByXTqVu8ssPe1R1uPQWvH34T9w1VYMf+bpnWHQ8aE6wEDPjq4kGvlZHnnGiVnCQyQf4T+wBRLA7LkuPb0d3tKJq8d7J9PN24k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=jjDM9OCj; arc=none smtp.client-ip=85.9.206.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="jjDM9OCj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773826864; x=1774086064; bh=e8BFK1m08UzgrYFFBt6dCGTjWCawWzRQ5mu9DCpAQCg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=jjDM9OCjnNxJGlCevuNHFR54zEXe5xAXzA7i5vI39WRPNqqkJR3LON+BkdSFHa+4i XfHeOzHNQSA77F2z9YN10v/vNeCUlOIYMFsUYRcRGSix2Eb8F+N+nFcPkfoYd7Upst 5q34JC2I8cV0pH4IxtlNFcy+qxSEexXQH5FVjmRO6UYSEAvAVKi10TY209ppWSVwme n4NHoGbXwLeiH60mHANMsBkroiWzoNyQTzQh0apZbhAmQ8KSLwTj+sHoVg2GElt3Dk Ij7QfAkYhx8NGrUqT/qKUN4hAeTKlGIQB54LRdgnDOOo4IXZRGy1KHCdcrLau+d7fh 7HLqTtjaUMVMA== Date: Wed, 18 Mar 2026 09:41:00 +0000 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten From: Alexander Koskovich Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich Subject: [PATCH 1/3] drm/mipi-dsi: add RGB101010 pixel format Message-ID: <20260318-dsi-rgb101010-support-v1-1-6021eb79e796@pm.me> In-Reply-To: <20260318-dsi-rgb101010-support-v1-0-6021eb79e796@pm.me> References: <20260318-dsi-rgb101010-support-v1-0-6021eb79e796@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 9b2600adb2bed490e714af3ccd60263349fcbd2a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MIPI_DSI_FMT_RGB101010 for 30 bit (10,10,10 RGB) pixel format, corresponding to the packed 30 bit pixel stream defined in MIPI DSI v1.3 Section 8.8.17. Signed-off-by: Alexander Koskovich Reviewed-by: Dmitry Baryshkov --- include/drm/drm_mipi_dsi.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 3aba7b380c8d..a822e9e876af 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -140,6 +140,7 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(str= uct device_node *node); #define MIPI_DSI_HS_PKT_END_ALIGNED BIT(12) =20 enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB101010, MIPI_DSI_FMT_RGB888, MIPI_DSI_FMT_RGB666, MIPI_DSI_FMT_RGB666_PACKED, @@ -235,6 +236,9 @@ extern const struct bus_type mipi_dsi_bus_type; static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format = fmt) { switch (fmt) { + case MIPI_DSI_FMT_RGB101010: + return 30; + case MIPI_DSI_FMT_RGB888: case MIPI_DSI_FMT_RGB666: return 24; --=20 2.53.0 From nobody Mon Apr 6 18:27:12 2026 Received: from mail-43100.protonmail.ch (mail-43100.protonmail.ch [185.70.43.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10F2F3B8921 for ; Wed, 18 Mar 2026 09:41:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773826880; cv=none; b=gO/8Q7MlI1s7/aApuylPzwB/1DPfRm23e97K6gBmmdThbpyQv/quJ5EPDxU0FVEZSZRNs+6izY/PK5l86FhrMaBpaJ1M7p3BZFrQemLcQ4DIie7jUm65uA2o8hcdZOrXjg8YX1Nxm4dK6cNqow5ddv07b0qZoKVvRyD4+pA1A8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773826880; c=relaxed/simple; bh=ruYaGccTAKXK+P0Ge5dwgCX44x/fhBLVWW76X3wmX0I=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JoEvgKNw5jd+BVI/D5Lq2NKnDgJnQg86jCVA7S3H0Pc1dBs/KyIuLQwvAGjLQ4TuucYHTP4PJScbERPo1EZ17yIrKvHb/0bZ37YyfFAXmiXpJWOcCd8rHjReR2/gKqO02SrJyX1IBQMiKKjAL/aD0t9pOoUt7reRtjg7BuLdeBE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=AyQaD+9Q; arc=none smtp.client-ip=185.70.43.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="AyQaD+9Q" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773826868; x=1774086068; bh=cpbR1pI93xvVsMgjnenFLen8wZueCr5a35WmFg67pXU=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=AyQaD+9QGQ4g7rW28zwPEC6FX92gZ5WTDJaPbJ4OufoZ9cX9lIPNo/7+HpIl26P4D vb/54Wvq0SSa/hacytcUAJZERm3HY5BEb/VNGO2MBWsNpo37VaiMOh4/WLC3k8CjS9 2TcNSWOtH8uCsCb5FsNyx/OclRvUAolBnWsFvsVDVymgh54rE7FySAMbCqyKMTNj+L ZR3fCuzKfB0YJYGjbQxob+9PDrcuW+C4keZGQbvmZPWCD/Os7aFkQkEIhAG+yeuGKJ fUwD3F38slGcB7Fkcj1ZLH3tPVP2aJ3s6F9iiuP45JV2Qctm/w9WCT6m1BVK/v+zZR XXTO82pJP+YVw== Date: Wed, 18 Mar 2026 09:41:05 +0000 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten From: Alexander Koskovich Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich Subject: [PATCH 2/3] drm/msm/dsi: Add support for RGB101010 pixel format Message-ID: <20260318-dsi-rgb101010-support-v1-2-6021eb79e796@pm.me> In-Reply-To: <20260318-dsi-rgb101010-support-v1-0-6021eb79e796@pm.me> References: <20260318-dsi-rgb101010-support-v1-0-6021eb79e796@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: f8dd0542583259f10d8d10849af1a9bd91c952f8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add video and command mode destination format mappings for RGB101010, and extend the VID_CFG0 DST_FORMAT bitfield to 3 bits to accommodate the new format value. Required for 10 bit panels such as the BOE BF068MWM-TD0. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++ drivers/gpu/drm/msm/registers/display/dsi.xml | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index db6da99375a1..3e3d61b9390f 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -757,6 +757,7 @@ static inline enum dsi_vid_dst_format dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt) { switch (mipi_fmt) { + case MIPI_DSI_FMT_RGB101010: return VID_DST_FORMAT_RGB101010; case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; @@ -769,6 +770,7 @@ static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt) { switch (mipi_fmt) { + case MIPI_DSI_FMT_RGB101010: return CMD_DST_FORMAT_RGB101010; case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; case MIPI_DSI_FMT_RGB666_PACKED: case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; diff --git a/drivers/gpu/drm/msm/registers/display/dsi.xml b/drivers/gpu/dr= m/msm/registers/display/dsi.xml index c7a7b633d747..7636e9914078 100644 --- a/drivers/gpu/drm/msm/registers/display/dsi.xml +++ b/drivers/gpu/drm/msm/registers/display/dsi.xml @@ -15,6 +15,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> + @@ -39,6 +40,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> + @@ -142,7 +144,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> - + --=20 2.53.0 From nobody Mon Apr 6 18:27:12 2026 Received: from mail-43103.protonmail.ch (mail-43103.protonmail.ch [185.70.43.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA2433A63F9 for ; Wed, 18 Mar 2026 09:41:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="TgCZIB3F" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773826872; x=1774086072; bh=pp3XZb0ALhTP7LyMnVusUzUvvZEvNzyavN4uuB4T2gk=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=TgCZIB3FYcuhgLiyqxCnROt5SGZHW2ZV8qQddZd18qOJVzdSwxjMWNA3n2L33r3Kr gRvXQdzzzSw4M/Tysrbp9S8j9Eq4IV8u9jHpC6cL/rREJOpEdV642dSzOvVye7eBOD DG5QFLsXJuj7BDQcJG+Moc79u/mep3yUVrtqilAeWbz8G9jRxiE+qxwT2wbujAVU4S 1dfn72rfiokGqOGcBoTrzF7IgfP7ffv5k7ln4QK622S82ucCuf7KCBXmiB04AO+h0N viSgKpaDH0AZm5ARdTgw0JgD4d0/irXbwWnZx6ng6P0wfFahBG7VHreGa5rL6lFBNx /w5UneVSx1d0Q== Date: Wed, 18 Mar 2026 09:41:09 +0000 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten From: Alexander Koskovich Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich Subject: [PATCH 3/3] drm/msm/dpu: fix video mode DSC INTF timing width for non 8 bit panels Message-ID: <20260318-dsi-rgb101010-support-v1-3-6021eb79e796@pm.me> In-Reply-To: <20260318-dsi-rgb101010-support-v1-0-6021eb79e796@pm.me> References: <20260318-dsi-rgb101010-support-v1-0-6021eb79e796@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 00294e59a403e87f8b55690d224023b92ed5dd9a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Using bits_per_component * 3 as the divisor for the compressed INTF timing width produces constant FIFO errors for panels such as the BOE BF068MWM-TD0 which is a 10 bit panel. The downstream driver calculates the compressed timing width by dividing the total compressed bytes per line by 3 which does not depend on bits_per_component. Switch the divisor to 24 to match downstream. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 0ba777bda253..9b046a0e77aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -122,19 +122,21 @@ static void drm_mode_to_intf_timing_params( } =20 /* - * for DSI, if compression is enabled, then divide the horizonal active - * timing parameters by compression ratio. bits of 3 components(R/G/B) - * is compressed into bits of 1 pixel. + * For DSI, if DSC is enabled, use a fixed divisor of 24 rather than + * bits_per_component * 3 when calculating the compressed timing width. + * + * This matches the downstream driver and is required for panels with + * bits_per_component !=3D 8. */ if (phys_enc->hw_intf->cap->type !=3D INTF_DP && timing->compression_en) { struct drm_dsc_config *dsc =3D dpu_encoder_get_dsc_config(phys_enc->parent); + /* * TODO: replace drm_dsc_get_bpp_int with logic to handle * fractional part if there is fraction */ - timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / - (dsc->bits_per_component * 3); + timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / 24; timing->xres =3D timing->width; } } --=20 2.53.0