From nobody Mon Apr 6 19:49:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1EFB3B894E; Wed, 18 Mar 2026 10:09:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773828548; cv=none; b=iWgVtQrQyujjjbyqhv+GDLmAqOdM/IRKcvjtvr5w+mrsXd2wvoQFRyVzVroLfyEFVJ5lInr4mX6/uM5oAZsuaqfJ8K2fAGfJufPVSaEDCoxFKmsu7XIAO7xoogbmgA7j6iFM+Vy6qD6kM3CrlDMcenRL6tGLiwp4KPPj9g2uyHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773828548; c=relaxed/simple; bh=fATHKtAaCK43dNNL4W06mJeYlOuUU6Bj57tAhbY/8Og=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hWggu/394Su9hNMiRBSmejq2eMBAaB0b2QnIUbRi4Aqypejgxs4nZpH8YQHtqT/LRwjwOZ/VCnnVeRYz6szKGBuHIZDP2cb45ROzFeFQp38Q9vdXqEqsd02BBzP3ujOP3TtYNqeR6PuKA1FFm8EHkCpeIqEdg7M7o36cb5jCk4o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A+Gdp2lL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A+Gdp2lL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E28AEC2BC87; Wed, 18 Mar 2026 10:09:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773828548; bh=fATHKtAaCK43dNNL4W06mJeYlOuUU6Bj57tAhbY/8Og=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A+Gdp2lLtHarHnpWg3S4EsTnEG/7+vgtdp9nkb9UdC1TngcI7r5xze9ZgrjvFWu+V z0VfuB3AsG+dnJHsnR6Qw6QiewOxlYm1Pr0lkhq1e6jdmkhcfGATfQOd5CKMCA8tqt UHZmKc7h6dFTsWl8BF9NMGyAD4/rag6T4ZYsVAEScUepiiwTUfG/vq0m93tgeFlvhI 6buJq190ahtIXD020Zw1an2D30cC7nOrFU0TohRF9p/6aKDnWJyhGc+glL0YuGpFIX uLfxvd2AN+a67r63SXKUH8RYclXsLHFKQsdv3eUrdg2cOezc/WGxHtnjPItzhy24Bg jU2L290JjVR4A== From: Leon Romanovsky To: Selvin Xavier , Kalesh AP , Jason Gunthorpe , Leon Romanovsky Cc: linux-rdma@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH rdma-next 1/4] RDMA/bnxt_re: Simplify bnxt_re_init_depth() callers and implementation Date: Wed, 18 Mar 2026 12:08:50 +0200 Message-ID: <20260318-bnxt_re-cq-v1-1-381cb1b5e625@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260318-bnxt_re-cq-v1-0-381cb1b5e625@nvidia.com> References: <20260318-bnxt_re-cq-v1-0-381cb1b5e625@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.15-dev-18f8f Content-Transfer-Encoding: quoted-printable From: Leon Romanovsky All callers of bnxt_re_init_depth() compute the minimum between its return value and another internal variable, often mixing variable types in the process. Clean this up by making the logic simpler and more readable. Signed-off-by: Leon Romanovsky Acked-by: Selvin Xavier --- drivers/infiniband/hw/bnxt_re/ib_verbs.c | 81 ++++++++++++++--------------= ---- drivers/infiniband/hw/bnxt_re/ib_verbs.h | 9 ++-- 2 files changed, 42 insertions(+), 48 deletions(-) diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.c b/drivers/infiniband/= hw/bnxt_re/ib_verbs.c index 182128ee4f242..40ac546f113bc 100644 --- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c +++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c @@ -1442,7 +1442,6 @@ static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, struct bnxt_qplib_qp *qplqp; struct bnxt_re_dev *rdev; struct bnxt_qplib_q *rq; - int entries; =20 rdev =3D qp->rdev; qplqp =3D &qp->qplib_qp; @@ -1465,8 +1464,9 @@ static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, /* Allocate 1 more than what's provided so posting max doesn't * mean empty. */ - entries =3D bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx); - rq->max_wqe =3D min_t(u32, entries, dev_attr->max_qp_wqes + 1); + rq->max_wqe =3D bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, + dev_attr->max_qp_wqes + 1, + uctx); rq->max_sw_wqe =3D rq->max_wqe; rq->q_full_delta =3D 0; rq->sg_info.pgsize =3D PAGE_SIZE; @@ -1504,7 +1504,6 @@ static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, struct bnxt_re_dev *rdev; struct bnxt_qplib_q *sq; int diff =3D 0; - int entries; int rc; =20 rdev =3D qp->rdev; @@ -1513,7 +1512,6 @@ static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, dev_attr =3D rdev->dev_attr; =20 sq->max_sge =3D init_attr->cap.max_send_sge; - entries =3D init_attr->cap.max_send_wr; if (uctx && qplqp->wqe_mode =3D=3D BNXT_QPLIB_WQE_MODE_VARIABLE) { sq->max_wqe =3D ureq->sq_slots; sq->max_sw_wqe =3D ureq->sq_slots; @@ -1529,10 +1527,11 @@ static int bnxt_re_init_sq_attr(struct bnxt_re_qp *= qp, return rc; =20 /* Allocate 128 + 1 more than what's provided */ - diff =3D (qplqp->wqe_mode =3D=3D BNXT_QPLIB_WQE_MODE_VARIABLE) ? - 0 : BNXT_QPLIB_RESERVED_QP_WRS; - entries =3D bnxt_re_init_depth(entries + diff + 1, uctx); - sq->max_wqe =3D min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1); + if (qplqp->wqe_mode !=3D BNXT_QPLIB_WQE_MODE_VARIABLE) + diff =3D BNXT_QPLIB_RESERVED_QP_WRS; + sq->max_wqe =3D bnxt_re_init_depth( + init_attr->cap.max_send_wr + diff + 1, + dev_attr->max_qp_wqes + diff + 1, uctx); if (qplqp->wqe_mode =3D=3D BNXT_QPLIB_WQE_MODE_VARIABLE) sq->max_sw_wqe =3D bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true); else @@ -1559,16 +1558,15 @@ static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_= re_qp *qp, struct bnxt_qplib_dev_attr *dev_attr; struct bnxt_qplib_qp *qplqp; struct bnxt_re_dev *rdev; - int entries; =20 rdev =3D qp->rdev; qplqp =3D &qp->qplib_qp; dev_attr =3D rdev->dev_attr; =20 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { - entries =3D bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx); - qplqp->sq.max_wqe =3D min_t(u32, entries, - dev_attr->max_qp_wqes + 1); + qplqp->sq.max_wqe =3D + bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, + dev_attr->max_qp_wqes + 1, uctx); qplqp->sq.q_full_delta =3D qplqp->sq.max_wqe - init_attr->cap.max_send_wr; qplqp->sq.max_sge++; /* Need one extra sge to put UD header */ @@ -2086,7 +2084,7 @@ int bnxt_re_create_srq(struct ib_srq *ib_srq, struct bnxt_re_pd *pd; struct ib_pd *ib_pd; u32 active_srqs; - int rc, entries; + int rc; =20 ib_pd =3D ib_srq->pd; pd =3D container_of(ib_pd, struct bnxt_re_pd, ib_pd); @@ -2112,10 +2110,9 @@ int bnxt_re_create_srq(struct ib_srq *ib_srq, /* Allocate 1 more than what's provided so posting max doesn't * mean empty */ - entries =3D bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx); - if (entries > dev_attr->max_srq_wqes + 1) - entries =3D dev_attr->max_srq_wqes + 1; - srq->qplib_srq.max_wqe =3D entries; + srq->qplib_srq.max_wqe =3D + bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, + dev_attr->max_srq_wqes + 1, uctx); =20 srq->qplib_srq.max_sge =3D srq_init_attr->attr.max_sge; /* 128 byte wqe size for SRQ . So use max sges */ @@ -2296,7 +2293,7 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_= qp_attr *qp_attr, struct bnxt_re_dev *rdev =3D qp->rdev; struct bnxt_qplib_dev_attr *dev_attr =3D rdev->dev_attr; enum ib_qp_state curr_qp_state, new_qp_state; - int rc, entries; + int rc; unsigned int flags; u8 nw_type; =20 @@ -2510,9 +2507,9 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_= qp_attr *qp_attr, "Create QP failed - max exceeded"); return -EINVAL; } - entries =3D bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx); - qp->qplib_qp.sq.max_wqe =3D min_t(u32, entries, - dev_attr->max_qp_wqes + 1); + qp->qplib_qp.sq.max_wqe =3D + bnxt_re_init_depth(qp_attr->cap.max_send_wr, + dev_attr->max_qp_wqes + 1, uctx); qp->qplib_qp.sq.q_full_delta =3D qp->qplib_qp.sq.max_wqe - qp_attr->cap.max_send_wr; /* @@ -2523,9 +2520,9 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_= qp_attr *qp_attr, qp->qplib_qp.sq.q_full_delta -=3D 1; qp->qplib_qp.sq.max_sge =3D qp_attr->cap.max_send_sge; if (qp->qplib_qp.rq.max_wqe) { - entries =3D bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx); - qp->qplib_qp.rq.max_wqe =3D - min_t(u32, entries, dev_attr->max_qp_wqes + 1); + qp->qplib_qp.rq.max_wqe =3D bnxt_re_init_depth( + qp_attr->cap.max_recv_wr, + dev_attr->max_qp_wqes + 1, uctx); qp->qplib_qp.rq.max_sw_wqe =3D qp->qplib_qp.rq.max_wqe; qp->qplib_qp.rq.q_full_delta =3D qp->qplib_qp.rq.max_wqe - qp_attr->cap.max_recv_wr; @@ -3381,8 +3378,8 @@ int bnxt_re_create_user_cq(struct ib_cq *ibcq, const = struct ib_cq_init_attr *att struct bnxt_re_cq_resp resp =3D {}; struct bnxt_re_cq_req req; int cqe =3D attr->cqe; - int rc, entries; - u32 active_cqs; + int rc; + u32 active_cqs, entries; =20 if (attr->flags) return -EOPNOTSUPP; @@ -3397,17 +3394,16 @@ int bnxt_re_create_user_cq(struct ib_cq *ibcq, cons= t struct ib_cq_init_attr *att cctx =3D rdev->chip_ctx; cq->qplib_cq.cq_handle =3D (u64)(unsigned long)(&cq->qplib_cq); =20 - entries =3D bnxt_re_init_depth(cqe + 1, uctx); - if (entries > dev_attr->max_cq_wqes + 1) - entries =3D dev_attr->max_cq_wqes + 1; - rc =3D ib_copy_validate_udata_in_cm(udata, req, cq_handle, BNXT_RE_CQ_FIXED_NUM_CQE_ENABLE); if (rc) return rc; =20 if (req.comp_mask & BNXT_RE_CQ_FIXED_NUM_CQE_ENABLE) - entries =3D cqe; + entries =3D attr->cqe; + else + entries =3D bnxt_re_init_depth(attr->cqe + 1, + dev_attr->max_cq_wqes + 1, uctx); =20 if (!ibcq->umem) { ibcq->umem =3D ib_umem_get(&rdev->ibdev, req.cq_va, @@ -3480,7 +3476,7 @@ int bnxt_re_create_cq(struct ib_cq *ibcq, const struc= t ib_cq_init_attr *attr, rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); struct bnxt_qplib_dev_attr *dev_attr =3D rdev->dev_attr; int cqe =3D attr->cqe; - int rc, entries; + int rc; u32 active_cqs; =20 if (udata) @@ -3498,11 +3494,8 @@ int bnxt_re_create_cq(struct ib_cq *ibcq, const stru= ct ib_cq_init_attr *attr, cq->rdev =3D rdev; cq->qplib_cq.cq_handle =3D (u64)(unsigned long)(&cq->qplib_cq); =20 - entries =3D bnxt_re_init_depth(cqe + 1, uctx); - if (entries > dev_attr->max_cq_wqes + 1) - entries =3D dev_attr->max_cq_wqes + 1; - - cq->max_cql =3D min_t(u32, entries, MAX_CQL_PER_POLL); + cq->max_cql =3D bnxt_re_init_depth(attr->cqe + 1, + dev_attr->max_cq_wqes + 1, uctx); cq->cql =3D kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), GFP_KERNEL); if (!cq->cql) @@ -3511,7 +3504,7 @@ int bnxt_re_create_cq(struct ib_cq *ibcq, const struc= t ib_cq_init_attr *attr, cq->qplib_cq.sg_info.pgsize =3D SZ_4K; cq->qplib_cq.sg_info.pgshft =3D __builtin_ctz(SZ_4K); cq->qplib_cq.dpi =3D &rdev->dpi_privileged; - cq->qplib_cq.max_wqe =3D entries; + cq->qplib_cq.max_wqe =3D cq->max_cql; cq->qplib_cq.coalescing =3D &rdev->cq_coalescing; cq->qplib_cq.nq =3D bnxt_re_get_nq(rdev); cq->qplib_cq.cnq_hw_ring_id =3D cq->qplib_cq.nq->ring_id; @@ -3522,7 +3515,7 @@ int bnxt_re_create_cq(struct ib_cq *ibcq, const struc= t ib_cq_init_attr *attr, goto fail; } =20 - cq->ib_cq.cqe =3D entries; + cq->ib_cq.cqe =3D cq->max_cql; cq->cq_period =3D cq->qplib_cq.period; active_cqs =3D atomic_inc_return(&rdev->stats.res.cq_count); if (active_cqs > rdev->stats.res.cq_watermark) @@ -3560,7 +3553,8 @@ int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, st= ruct ib_udata *udata) struct bnxt_re_resize_cq_req req; struct bnxt_re_dev *rdev; struct bnxt_re_cq *cq; - int rc, entries; + int rc; + u32 entries; =20 cq =3D container_of(ibcq, struct bnxt_re_cq, ib_cq); rdev =3D cq->rdev; @@ -3584,10 +3578,7 @@ int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, s= truct ib_udata *udata) } =20 uctx =3D rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uct= x); - entries =3D bnxt_re_init_depth(cqe + 1, uctx); - if (entries > dev_attr->max_cq_wqes + 1) - entries =3D dev_attr->max_cq_wqes + 1; - + entries =3D bnxt_re_init_depth(cqe + 1, dev_attr->max_cq_wqes + 1, uctx); /* uverbs consumer */ rc =3D ib_copy_validate_udata_in(udata, req, cq_va); if (rc) diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.h b/drivers/infiniband/= hw/bnxt_re/ib_verbs.h index 3d02c16f54b61..dfe790ef42d75 100644 --- a/drivers/infiniband/hw/bnxt_re/ib_verbs.h +++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.h @@ -190,10 +190,13 @@ enum { BNXT_RE_UCNTX_CAP_VAR_WQE_ENABLED =3D 0x2ULL, }; =20 -static inline u32 bnxt_re_init_depth(u32 ent, struct bnxt_re_ucontext *uct= x) +static inline u32 bnxt_re_init_depth(u32 ent, u32 max, + struct bnxt_re_ucontext *uctx) { - return uctx ? (uctx->cmask & BNXT_RE_UCNTX_CAP_POW2_DISABLED) ? - ent : roundup_pow_of_two(ent) : ent; + if (uctx && !(uctx->cmask & BNXT_RE_UCNTX_CAP_POW2_DISABLED)) + return min(roundup_pow_of_two(ent), max); + + return ent; } =20 static inline bool bnxt_re_is_var_size_supported(struct bnxt_re_dev *rdev, --=20 2.53.0