From nobody Sun Apr 5 18:03:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2956B39D6CF; Wed, 18 Mar 2026 17:56:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773856572; cv=none; b=VzZoSb2NTO3tgyc90i9DjiMnOt66iQCD2Kb684DI752qtZ/2KPMbq5KZcZ8WAVuxJ7eGBtLjbMLywyZaM205aO3faxepMgmnmlHzUNLdpALQe/Q8pbwYgQP0UptuL/JvpgUu+MakNXK83YILoGhJpWxc2lKMIyQHIIPDKOSAAl8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773856572; c=relaxed/simple; bh=5eY3CdwHbhOcYqu2M3FfsZai0BgSLcl+0bIJzDOghj8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VFm8tMbdTP0JedxW0NBIbClTpVJVWsk/fYzAjhc7OtqeubYwFtdjZI+xHlak2QLRlPlzWnd98YSMnT4VRsir7bZim4xlHtxVK/IJx5ttCZkweWu7yOoqjNO3BMdpuqqgWmqCfxJUwun/ECtLFnJmIQvwxTEqR/dk1JJ6nbgffOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DIZGbHEN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DIZGbHEN" Received: by smtp.kernel.org (Postfix) with ESMTPS id 78112C2BCF4; Wed, 18 Mar 2026 17:56:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773856571; bh=5eY3CdwHbhOcYqu2M3FfsZai0BgSLcl+0bIJzDOghj8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DIZGbHEN1PdG/LTVb+qooFyudVeNXhKOcaDRf69DpAZxGGdnvTaoygIImYUW/he5V T+ovgiNX17Hrbe48kGTNwP7VQ0hxDGpxKpR506NMcWmy5cGDPcsMcxdRzhy4P5giPp HHHlqA7XHH//21yEqlsoijcDGCfFHcKYUC4Gs8+7nDIYDqERcaN82cIjdcmzTjfrHK +SsJVgdKcMRhmf6NRiowlmFVHMBWSZBvSvowaXH6Dve2E/nB7SGdu5eSm/KfyHQbvV TSnRhBsX8Rj08SAPeI0mkVnOT4JGafyQ9QD2ZcyxGAUjwEQlK6VY/rXUkytc7cKK8X X572fkcjmlUjA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F4E210775FC; Wed, 18 Mar 2026 17:56:11 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Wed, 18 Mar 2026 17:56:06 +0000 Subject: [PATCH RFC v2 6/9] iio: frequency: ad9910: add output shift keying support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260318-ad9910-iio-driver-v2-6-e79f93becf11@analog.com> References: <20260318-ad9910-iio-driver-v2-0-e79f93becf11@analog.com> In-Reply-To: <20260318-ad9910-iio-driver-v2-0-e79f93becf11@analog.com> To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Jonathan Corbet , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773856569; l=9534; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=nUoR28p1cCg5N7pqZqDgKJBKPqzJj/RqPnZdE1Mkogc=; b=Brbt9rD0/n+JoIKh++v4wQdUbuvXi3EaSK8VBtl1rcRMAXpnqWmywpZ70vN4l7hyqkWlyeSqY nvYiS+WSshiAWom2UsoRwJNfKAqA2KW/JCkZJ7pdZQcEBDFGnF2TCUf X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add OSK channel with amplitude envelope control capabilities: - OSK enable/disable via IIO_CHAN_INFO_ENABLE; - Amplitude ramp rate control via IIO_CHAN_INFO_SAMP_FREQ; - Amplitude scale readback via IIO_CHAN_INFO_SCALE (ASF register); - Manual/external pin control via pinctrl_en ext_info attribute; - Automatic OSK step size configuration via scale_increment ext_info; attribute with selectable step sizes (61, 122, 244, 488 micro-units) The ASF register is initialized with a default amplitude ramp rate during device setup to ensure valid readback. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/ad9910.c | 152 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 151 insertions(+), 1 deletion(-) diff --git a/drivers/iio/frequency/ad9910.c b/drivers/iio/frequency/ad9910.c index 747f4f407536..35572d60d6d2 100644 --- a/drivers/iio/frequency/ad9910.c +++ b/drivers/iio/frequency/ad9910.c @@ -232,6 +232,7 @@ * @AD9910_CHANNEL_DRG_RAMP_UP: DRG ramp up channel * @AD9910_CHANNEL_DRG_RAMP_DOWN: DRG ramp down channel * @AD9910_CHANNEL_RAM: RAM control output channel + * @AD9910_CHANNEL_OSK: Output Shift Keying output channel */ enum ad9910_channel { AD9910_CHANNEL_PHY =3D 100, @@ -241,6 +242,7 @@ enum ad9910_channel { AD9910_CHANNEL_DRG_RAMP_UP =3D 131, AD9910_CHANNEL_DRG_RAMP_DOWN =3D 132, AD9910_CHANNEL_RAM =3D 140, + AD9910_CHANNEL_OSK =3D 150, }; =20 /** @@ -317,6 +319,8 @@ enum { AD9910_DRG_AMP_STEP, AD9910_RAM_START_ADDR, AD9910_RAM_END_ADDR, + AD9910_OSK_MANUAL_EXTCTL, + AD9910_OSK_AUTO_STEP, }; =20 struct ad9910_data { @@ -405,6 +409,10 @@ static const char * const ad9910_ram_oper_mode_str[] = =3D { [AD9910_RAM_MODE_SEQ_CONT] =3D "sequenced_continuous", }; =20 +static const u16 ad9910_osk_ustep[] =3D { + 0, 61, 122, 244, 488, +}; + /** * ad9910_rational_scale() - Perform scaling of input given a reference. * @input: The input value to be scaled. @@ -802,6 +810,10 @@ static ssize_t ad9910_ext_info_read(struct iio_dev *in= dio_dev, val =3D FIELD_GET(AD9910_PROFILE_RAM_END_ADDR_MSK, ad9910_ram_profile_val(st)); break; + case AD9910_OSK_MANUAL_EXTCTL: + val =3D FIELD_GET(AD9910_CFR1_OSK_MANUAL_EXT_CTL_MSK, + st->reg[AD9910_REG_CFR1].val32); + break; default: return -EINVAL; } @@ -873,6 +885,12 @@ static ssize_t ad9910_ext_info_write(struct iio_dev *i= ndio_dev, FIELD_MODIFY(AD9910_PROFILE_RAM_END_ADDR_MSK, &st->reg_profile[st->profile], val32); break; + case AD9910_OSK_MANUAL_EXTCTL: + val32 =3D val32 ? AD9910_CFR1_OSK_MANUAL_EXT_CTL_MSK : 0; + ret =3D ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_OSK_MANUAL_EXT_CTL_MSK, + val32, true); + break; default: return -EINVAL; } @@ -1105,6 +1123,80 @@ static ssize_t ad9910_drg_attrs_write(struct iio_dev= *indio_dev, return ret ?: len; } =20 +static ssize_t ad9910_osk_attrs_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int vals[2]; + bool auto_en; + u32 raw_val; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_OSK_AUTO_STEP: + auto_en =3D FIELD_GET(AD9910_CFR1_SELECT_AUTO_OSK_MSK, + st->reg[AD9910_REG_CFR1].val32); + raw_val =3D FIELD_GET(AD9910_ASF_STEP_SIZE_MSK, + st->reg[AD9910_REG_ASF].val32); + vals[0] =3D 0; + vals[1] =3D auto_en ? ad9910_osk_ustep[raw_val + 1] : 0; + + return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals); + default: + return -EINVAL; + } +} + +static ssize_t ad9910_osk_attrs_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad9910_state *st =3D iio_priv(indio_dev); + int val, val2; + int ret; + u32 raw_val; + + ret =3D iio_str_to_fixpoint(buf, MICRO / 10, &val, &val2); + if (ret) + return ret; + + guard(mutex)(&st->lock); + + switch (private) { + case AD9910_OSK_AUTO_STEP: + if (val !=3D 0) + return -EINVAL; + + raw_val =3D find_closest(val2, ad9910_osk_ustep, + ARRAY_SIZE(ad9910_osk_ustep)); + if (raw_val) { + /* set OSK step and get automatic OSK enabled */ + raw_val =3D FIELD_PREP(AD9910_ASF_STEP_SIZE_MSK, + raw_val - 1); + ret =3D ad9910_reg32_update(st, AD9910_REG_ASF, + AD9910_ASF_STEP_SIZE_MSK, + raw_val, true); + if (ret) + return ret; + + raw_val =3D AD9910_CFR1_SELECT_AUTO_OSK_MSK; + } + + ret =3D ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_SELECT_AUTO_OSK_MSK, + raw_val, true); + break; + default: + return -EINVAL; + } + + return ret ?: len; +} + #define AD9910_EXT_INFO_TMPL(_name, _ident, _shared, _fn_desc) { \ .name =3D _name, \ .read =3D ad9910_ ## _fn_desc ## _read, \ @@ -1122,6 +1214,9 @@ static ssize_t ad9910_drg_attrs_write(struct iio_dev = *indio_dev, #define AD9910_DRG_EXT_INFO(_name, _ident) \ AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, drg_attrs) =20 +#define AD9910_OSK_EXT_INFO(_name, _ident) \ + AD9910_EXT_INFO_TMPL(_name, _ident, IIO_SEPARATE, osk_attrs) + static const struct iio_enum ad9910_drg_destination_enum =3D { .items =3D ad9910_destination_str, .num_items =3D AD9910_DRG_DEST_NUM, @@ -1189,6 +1284,12 @@ static const struct iio_chan_spec_ext_info ad9910_ra= m_ext_info[] =3D { { } }; =20 +static const struct iio_chan_spec_ext_info ad9910_osk_ext_info[] =3D { + AD9910_EXT_INFO("pinctrl_en", AD9910_OSK_MANUAL_EXTCTL, IIO_SEPARATE), + AD9910_OSK_EXT_INFO("scale_step", AD9910_OSK_AUTO_STEP), + { } +}; + static const struct iio_chan_spec ad9910_channels[] =3D { [AD9910_CHAN_IDX_PHY] =3D { .type =3D IIO_ALTVOLTAGE, @@ -1269,6 +1370,18 @@ static const struct iio_chan_spec ad9910_channels[] = =3D { BIT(IIO_CHAN_INFO_SAMP_FREQ), .ext_info =3D ad9910_ram_ext_info, }, + [AD9910_CHAN_IDX_OSK] =3D { + .type =3D IIO_ALTVOLTAGE, + .indexed =3D 1, + .output =3D 1, + .channel =3D AD9910_CHANNEL_OSK, + .address =3D AD9910_CHAN_IDX_OSK, + .scan_index =3D -1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_ENABLE) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .ext_info =3D ad9910_osk_ext_info, + }, }; =20 static int ad9910_read_raw(struct iio_dev *indio_dev, @@ -1296,6 +1409,10 @@ static int ad9910_read_raw(struct iio_dev *indio_dev, *val =3D FIELD_GET(AD9910_CFR1_RAM_ENABLE_MSK, st->reg[AD9910_REG_CFR1].val32); break; + case AD9910_CHANNEL_OSK: + *val =3D FIELD_GET(AD9910_CFR1_OSK_ENABLE_MSK, + st->reg[AD9910_REG_CFR1].val32); + break; default: return -EINVAL; } @@ -1374,6 +1491,12 @@ static int ad9910_read_raw(struct iio_dev *indio_dev, *val =3D 0; *val2 =3D tmp64 * NANO >> 32; return IIO_VAL_INT_PLUS_NANO; + case AD9910_CHANNEL_OSK: + tmp64 =3D FIELD_GET(AD9910_ASF_SCALE_FACTOR_MSK, + st->reg[AD9910_REG_ASF].val32); + *val =3D 0; + *val2 =3D tmp64 * MICRO >> 14; + return IIO_VAL_INT_PLUS_MICRO; default: return -EINVAL; } @@ -1394,6 +1517,10 @@ static int ad9910_read_raw(struct iio_dev *indio_dev, tmp32 =3D FIELD_GET(AD9910_PROFILE_RAM_STEP_RATE_MSK, ad9910_ram_profile_val(st)); break; + case AD9910_CHANNEL_OSK: + tmp32 =3D FIELD_GET(AD9910_ASF_RAMP_RATE_MSK, + st->reg[AD9910_REG_ASF].val32); + break; default: return -EINVAL; } @@ -1453,6 +1580,11 @@ static int ad9910_write_raw(struct iio_dev *indio_de= v, return ad9910_reg32_update(st, AD9910_REG_CFR1, AD9910_CFR1_RAM_ENABLE_MSK, tmp32, true); + case AD9910_CHANNEL_OSK: + tmp32 =3D FIELD_PREP(AD9910_CFR1_OSK_ENABLE_MSK, val); + return ad9910_reg32_update(st, AD9910_REG_CFR1, + AD9910_CFR1_OSK_ENABLE_MSK, + tmp32, true); default: return -EINVAL; } @@ -1585,6 +1717,14 @@ static int ad9910_write_raw(struct iio_dev *indio_de= v, return ad9910_reg64_update(st, AD9910_REG_DRG_LIMIT, AD9910_DRG_LIMIT_LOWER_MSK, tmp64, true); + case AD9910_CHANNEL_OSK: + tmp64 =3D ((u64)val * MICRO + val2) << 14; + tmp64 =3D DIV_U64_ROUND_CLOSEST(tmp64, MICRO); + tmp32 =3D min(tmp64, AD9910_ASF_MAX); + tmp32 =3D FIELD_PREP(AD9910_ASF_SCALE_FACTOR_MSK, tmp32); + return ad9910_reg32_update(st, AD9910_REG_ASF, + AD9910_ASF_SCALE_FACTOR_MSK, + tmp32, true); default: return -EINVAL; } @@ -1621,7 +1761,12 @@ static int ad9910_write_raw(struct iio_dev *indio_de= v, return ad9910_reg64_update(st, AD9910_REG_PROFILE(st->profile), AD9910_PROFILE_RAM_STEP_RATE_MSK, tmp64, true); - + break; + case AD9910_CHANNEL_OSK: + return ad9910_reg32_update(st, AD9910_REG_ASF, + AD9910_ASF_RAMP_RATE_MSK, + FIELD_PREP(AD9910_ASF_RAMP_RATE_MSK, tmp32), + true); default: return -EINVAL; } @@ -1916,6 +2061,11 @@ static int ad9910_setup(struct ad9910_state *st, str= uct reset_control *dev_rst) return ret; =20 /* configure step rate with default values */ + reg32 =3D FIELD_PREP(AD9910_ASF_RAMP_RATE_MSK, 1); + ret =3D ad9910_reg32_write(st, AD9910_REG_ASF, reg32, false); + if (ret) + return ret; + reg32 =3D FIELD_PREP(AD9910_DRG_RATE_DEC_MSK, 1) | FIELD_PREP(AD9910_DRG_RATE_INC_MSK, 1); ret =3D ad9910_reg32_write(st, AD9910_REG_DRG_RATE, reg32, false); --=20 2.43.0