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charset="utf-8" Replace the hardcoded 47-bit DMA mask with per-architecture values. Hopper and Blackwell support 52-bit DMA addresses, while Turing, Ampere, and Ada use 47-bit. Add Architecture::dma_mask() as a const method with an exhaustive match, so new architectures get a compile-time reminder to specify their DMA mask width. Move Spec creation into probe() so the architecture is known before setting the DMA mask, and pass the Spec into Gpu::new(). Cc: Danilo Krummrich Cc: Gary Guo Signed-off-by: John Hubbard --- drivers/gpu/nova-core/driver.rs | 28 +++++++-------- drivers/gpu/nova-core/gpu.rs | 60 +++++++++++++++++++-------------- 2 files changed, 47 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 84b0e1703150..41227d29934e 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -5,7 +5,6 @@ device::Core, devres::Devres, dma::Device, - dma::DmaMask, pci, pci::{ Class, @@ -23,7 +22,10 @@ }, }; =20 -use crate::gpu::Gpu; +use crate::gpu::{ + Gpu, + Spec, // +}; =20 /// Counter for generating unique auxiliary device IDs. static AUXILIARY_ID_COUNTER: Atomic =3D Atomic::new(0); @@ -38,14 +40,6 @@ pub(crate) struct NovaCore { =20 const BAR0_SIZE: usize =3D SZ_16M; =20 -// For now we only support Ampere which can use up to 47-bit DMA addresses. -// -// TODO: Add an abstraction for this to support newer GPUs which may suppo= rt -// larger DMA addresses. Limiting these GPUs to smaller address widths won= 't -// have any adverse affects, unless installed on systems which require lar= ger -// DMA addresses. These systems should be quite rare. -const GPU_DMA_BITS: u32 =3D 47; - pub(crate) type Bar0 =3D pci::Bar; =20 kernel::pci_device_table!( @@ -84,18 +78,20 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInfo= ) -> impl PinInit())? }; - let bar =3D Arc::pin_init( pdev.iomap_region_sized::(0, c"nova-core/bar0"), GFP_KERNEL, )?; + let spec =3D Spec::new(pdev.as_ref(), bar.access(pdev.as_ref()= )?)?; + dev_info!(pdev, "NVIDIA ({})\n", spec); + + // SAFETY: No concurrent DMA allocations or mappings can be ma= de because + // the device is still being probed and therefore isn't being = used by + // other threads of execution. + unsafe { pdev.dma_set_mask_and_coherent(spec.chipset().arch().= dma_mask())? }; =20 Ok(try_pin_init!(Self { - gpu <- Gpu::new(pdev, bar.clone(), bar.access(pdev.as_ref(= ))?), + gpu <- Gpu::new(pdev, bar.clone(), bar.access(pdev.as_ref(= ))?, spec), _reg <- auxiliary::Registration::new( pdev.as_ref(), c"nova-drm", diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 8f317d213908..9e140463603b 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -3,6 +3,7 @@ use kernel::{ device, devres::Devres, + dma::DmaMask, fmt, pci, prelude::*, @@ -162,6 +163,19 @@ pub(crate) enum Architecture { Blackwell =3D 0x1b, } =20 +impl Architecture { + /// Returns the DMA mask supported by this architecture. + /// + /// Hopper and Blackwell support 52-bit DMA addresses, while earlier + /// architectures (Turing, Ampere, Ada) support 47-bit. + pub(crate) const fn dma_mask(&self) -> DmaMask { + match self { + Self::Turing | Self::Ampere | Self::Ada =3D> DmaMask::new::<47= >(), + Self::Hopper | Self::Blackwell =3D> DmaMask::new::<52>(), + } + } +} + impl TryFrom for Architecture { type Error =3D Error; =20 @@ -211,7 +225,7 @@ pub(crate) struct Spec { } =20 impl Spec { - fn new(dev: &device::Device, bar: &Bar0) -> Result { + pub(crate) fn new(dev: &device::Device, bar: &Bar0) -> Result { // Some brief notes about boot0 and boot42, in chronological order: // // NV04 through NV50: @@ -292,38 +306,34 @@ pub(crate) fn new<'a>( pdev: &'a pci::Device, devres_bar: Arc>, bar: &'a Bar0, + spec: Spec, ) -> impl PinInit + 'a { - pin_init::pin_init_scope(move || { - let spec =3D Spec::new(pdev.as_ref(), bar)?; - dev_info!(pdev, "NVIDIA ({})\n", spec); - - let chipset =3D spec.chipset(); + let chipset =3D spec.chipset(); =20 - Ok(try_pin_init!(Self { - // We must wait for GFW_BOOT completion before doing any s= ignificant setup - // on the GPU. - _: { - gfw::wait_gfw_boot_completion(bar) - .inspect_err(|_| dev_err!(pdev, "GFW boot did not = complete\n"))?; - }, + try_pin_init!(Self { + // We must wait for GFW_BOOT completion before doing any signi= ficant setup + // on the GPU. + _: { + gfw::wait_gfw_boot_completion(bar) + .inspect_err(|_| dev_err!(pdev, "GFW boot did not comp= lete\n"))?; + }, =20 - sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar, ch= ipset)?, + sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar, chipse= t)?, =20 - gsp_falcon: Falcon::new( - pdev.as_ref(), - chipset, - ) - .inspect(|falcon| falcon.clear_swgen0_intr(bar))?, + gsp_falcon: Falcon::new( + pdev.as_ref(), + chipset, + ) + .inspect(|falcon| falcon.clear_swgen0_intr(bar))?, =20 - sec2_falcon: Falcon::new(pdev.as_ref(), chipset)?, + sec2_falcon: Falcon::new(pdev.as_ref(), chipset)?, =20 - gsp <- Gsp::new(pdev), + gsp <- Gsp::new(pdev), =20 - _: { gsp.boot(pdev, bar, chipset, gsp_falcon, sec2_falcon)= ? }, + _: { gsp.boot(pdev, bar, chipset, gsp_falcon, sec2_falcon)? }, =20 - bar: devres_bar, - spec, - })) + bar: devres_bar, + spec, }) } =20 --=20 2.53.0