From nobody Mon Apr 6 21:32:23 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011050.outbound.protection.outlook.com [40.107.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 168393A6406; Tue, 17 Mar 2026 22:54:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788052; cv=fail; b=huukdzw2o8IgoRAJDy3umFQEp/Kg5LC+KguHFPANpbe33PV9dibfYJNCzzBei7CBhZ7CbuYsb3XSsLzbGujhlTrNEX77ZYXxRdZEiMf69zRsI8deP5Wqq7Jhh3Ud594Nj5elcFmnHCIigLGKVksQqkNPAa2XQj/4tEIcn9YUOkA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788052; c=relaxed/simple; bh=Ija8YIpxjpmRoDARx1VwtKjQ9xFyXVyTXW4MaBdCVGI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=XNYoZw3kUS2TUHUAk65XbaAi8KXRhNHN04+PjFggG6r/Q30vX75dEnN1lv+LNBVX3nl1BMBx19oAi/S/7NHfjJfqTa7VX7xabIdGTjAB0JcfeenATUk68Tq7aEYC5ZwDlQzrfJh9gsR/Y2QDh/KOOpKo51PYNhx+YBiQ+LmzJFI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=CxLCoFi6; arc=fail smtp.client-ip=40.107.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="CxLCoFi6" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=xTOjbOi6yW7rZQLwiJ8k3Ltx2QMsvbhSxXVixRUSjCM0hGdzr7jU5DNax6GqjmcVLuDRk4aNWgvC0dGt4Mmvl9EMRbHKpLpHJn8UkOk5/MQ27dTTZ5i26xM6SzVeuD/q43ulGS1CPdLIUFLZdDM77PjFLUa8HCwjm7pDU5Dv0oXzXA/3ekVF+Cd2LAOFlL7xIXuiF2lq15VBByx2X23DbWu9qqU9l8+sYu7VfEJZ3GxlGt8cqyjM2i8We8dd9Pmy0vkHIYv2slpcgVE3LU7GsNWSi4STCPInpbgvVUthdHfYBfO9qUzfU7UnUqNw122o0yMJfLTG0DrIWVO2rNVD0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CQ5AUknuuz92nKYLsSEI10VQa2+9U4fn0S+1vhKeJH4=; b=mUscIIj9M84/aGKOkt662kjp5ci6z4fVu8PFZJkLIjy/xPMykVap3KWCmlw8SSKT7jM/2ISyIfO4EdpFhOnqh/AX6V+AAyjGlFWWJJuz3AvpqNs3EvERj55upeZL2K8X8jWdWr0arGaNLLHr45tvRgpLdv2I1yUiyzYrl3irpshVA921HNb37wFZUaEe5hnkz/el+Y6+BT09UrbF/B8q8JiX7DgHYP4xmCzCb6r1btlQJGCSW4LAjt1lV85QKtRoZpU4z84oaIR4xViOM3gHEvntp9C9H6N8cEzNX/7H2x42uucoJG6lsD5f/9b9FKp3aBHkHvHQ5mvCedVrwZzFVQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CQ5AUknuuz92nKYLsSEI10VQa2+9U4fn0S+1vhKeJH4=; b=CxLCoFi6mquAr7aMOx9C+qzOzRuABtx2V3DL5Ul/X5obLODf7EOtk09Ew5Zj4gGNWzWzj4mgz8MKtFdpqQKOWHTLMIiJkzcbZm1iXSNVP6RyJQlyqdJ8IrbV9C7za7pGT24RKrMAUy5VD5EquTNphYFeCckKYpQdZuAHkWXMOjwcFUYkRGk0yF9fRU/JbH2iHtjW6SyCLX6eG03BMQ9hllJHlWzpqvyOM5wdacOlOrGW+Sn+2Wd67D9NsntZ+Q4F+CLMYbybGWzWDW6QhcCVrUmOkCaunIlhKXidAMAwl+uy+9O/svg8a1m6OooZhxxY4AshQwks2hcsK6/RBRBE5A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:53:59 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:53:59 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 01/31] gpu: nova-core: Hopper/Blackwell: basic GPU identification Date: Tue, 17 Mar 2026 15:53:25 -0700 Message-ID: <20260317225355.549853-2-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR13CA0022.namprd13.prod.outlook.com (2603:10b6:a03:2c0::27) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: d5e86bc1-4380-4200-f0b3-08de8478134d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: kGYNrHMSC6lXd72jEZHYZfvKY8cOM0Km/mR2fIyiXD2Bpc81Y9huLPzh5BtDL/blcoM1wNVZcAVCJpLL8ZLdnoI/VslD6wo0lueSeP6RKcx8mISx8A5zWXC4PkMz58yS84kehiaL8A644ikUrzA58P4WrqkvqmqnpIFIvVw7VC8YtwJ5x5apUsGRV1SLsXTAKR+aM1Qfowlr1JuKrKEa4/IZ9ySpcY5KOA3H9KU12YnGGXjusIYjUjC3DJac1RwbhGB3zLkmQrbyGXYOrFeiNT2NpisTQMutFgcTpaub2VzUUSrIbfnpMdDPsdKOkNnfunFdT2DH1QIH6hT5sfhSVTOhGknf9tMY/D5/wZcquLhk1xbKr8aRg/IxfJdOc50uy/cIieyQNnKLu5Rb1f3Rr6hYn9ktCk2s8At61BzhdbOrkTEhflJ/aGVmsV5c1qnFoiqSS7MJVQA/O6WNMjLdwiyrk8HHN5pilvMtPne0SSWVX62y9Bki+A/G6DOG8PRyOtZNKf+qoItQTv4n1G60Z93KyeY5KHhahLra3vhwaCMVuHslid7Q52UgeLkRHOwJJHcJuQVb6BPPsNhXsEGgL7Ub78kPruK/2we+i+35KZ3qp7klTl8BDHD2kJEB89+SW5wx7PaZ3YeFBFKawsccNYnm2HMulb7GuV0jzXvrseLp27El7MES0hCTpnE2z8z8WS9IS8qQeeUS7KsBwDo6H4xnf1F9VqXizebpqsRG+2I= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?WDvUzJvIfvR5zog/iEmvN16df4433avTo+QxlFEbcbJiQekrzYw4j1ijWUTP?= =?us-ascii?Q?3GqekfKU0rnCY1BYpv8LdX2o5nO5paj8e6HUg5Yey3m7+xFqXb6VHKcQyS49?= =?us-ascii?Q?g8yxfjQCyWWFIKQftsBTWrTaE0OQkbIS8nzITiIvP8y6gyKaZqVRfqPyNm0V?= =?us-ascii?Q?stWCL4hdzbIPFUbGpZtf1WLGiMVVMY2ISxK0Kr5BW3TM8bqDJZy/7N7/B5M8?= =?us-ascii?Q?9jDKs7QmZysSB8YAg9ePA55C8Ov1DJlBzaFX3xuI0XK7Or3Q03wI8mAizo7G?= =?us-ascii?Q?4zsucYiN4VqG4y38XSw3YxrmrTNSK17PS5+ooFbSafjp62fJ6m5rcPDaPsPq?= =?us-ascii?Q?C2Kz2ZO2yQ8djwMniWp+zA5b+5xlqEZlTHjLeD7cAqOg8JDLMq4ZF5uJ37VF?= =?us-ascii?Q?yPES6giRbhbiqFOxuQAgwMUDAzwQcn7KqkXWUwPBgCt1WDy0zL1kAm+3zvWR?= =?us-ascii?Q?koP3Bk0jSJhBs0PphSkbJzKFE7iURTYjKJN8oYYYDskMQn+WDdhzcHOk8/kU?= =?us-ascii?Q?J56pjzWEQ39vJND4/LFMY+cWxM3E5+BvUmsrJiyEZxzzfLg17OXNLsSuQO8c?= =?us-ascii?Q?MNZXT6uPTIqdbFyGMeSA1dsQMaEO+R34VnOXwhxrTGLVkDpV7j179LU8u/9O?= =?us-ascii?Q?cqEJ3xD0RWd4h2MC3t+hy28Lb1+8616aAd7gpflnMFgWRsamohJvhnytc5pl?= =?us-ascii?Q?7oSu5fVgxl/MzYhNqPY9LjTyr/WVMbjYQ/t3zCR/ijiOs/WgVnJ+egZJr/tW?= =?us-ascii?Q?qAvWjAESF/dRp8wpDMU22B1Xfew9/xeXCLkzd/u7uvep79Dbb68T63tBDDgy?= =?us-ascii?Q?rNc8xUlmxHXIKfo2ZVSIMjSFK6kmXZTUZ9Nr5wLVQPJdY/ICDJxqFPGBCrb3?= =?us-ascii?Q?eloCIs8nZotmosnXLXoSp3cwJc4ac2A+oSpKMq51bzqd18F9tAlP1wAMeNAy?= =?us-ascii?Q?l7MAcEeAb41l4fXoPEpeA8p7LWwcb9vlYtq7P93Wehff44A2BulmOGDHfvRT?= =?us-ascii?Q?tN1kiW3YP0j/qsdRFa0E3XaDnX2E1xOkf6H3agaCbw3edc/+GWCeyk1xUO0c?= =?us-ascii?Q?qnBLMgc7mw7n7QsB6nCrq4/S2Cna0wQa365r1ZYUKVHQS1+KeatSECAdWFZe?= =?us-ascii?Q?1woTiAAs4Ra1v2Cy9jckSCdzHXzW+E903NQshpwDsiRmwKsIeUym/z7jmEhx?= =?us-ascii?Q?xt+xk6kTVlyBYRHrM4PO1bS89g/A+r8jzm1EeFzgUbi4OchzZrafnJ3PqU2f?= =?us-ascii?Q?7twvnKl/axyzRm2cKGUJrmSr7jqm0SQjL6Dq7kgRPqjSS4q3w+Zb/zDUCaH5?= =?us-ascii?Q?2713PEO7/QcnhSiDtGwDvt6FaaVlCSsY4mt0XUkmj6gNRQr+GWtdiLxFrX6e?= =?us-ascii?Q?Ux3tq9u+WSZbinugAQAyIPRQBVax6NORRoRytd0ZY2+urFPBWyFOJFLFtQBi?= =?us-ascii?Q?zHhj/pBNXfxTkV8v2n8O4vgqJris4O7d5iqPRnJwX/m0u6qFnWtDH1sE3uVN?= =?us-ascii?Q?vBOPIYrhRjrV0xZmM9CLLAfPSpf52Io3PR4FKiRwHTL1cvc+ktIH01KeOO9Q?= =?us-ascii?Q?0tivqRjZNA+fFlmeRg6qu7MYdh1AgFN2enWmVGOjJ9L9U8q3K2v4EyqTCCrA?= =?us-ascii?Q?nbt5hnFcog5SJp5eH+3wHv6V+s/+UrGRWsATPY5Gtx2HIIb+vuCA+/DL5EsN?= =?us-ascii?Q?36QYFXuRnkirWYI+ZcJBDMhx3GMZM1vs2CRtQDoUO0810LukAS9H5l5nhHqo?= =?us-ascii?Q?IIZAWki5cA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: d5e86bc1-4380-4200-f0b3-08de8478134d X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:53:58.9610 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cBMVb/9ZsBmm6t469wRn8ZSV1xwlWPkzdxVSP1YoztzshtTqvx+gcnEY7bg1fbhocr7r5IEumGeEHM4GhePPVg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Hopper (GH100) and Blackwell identification, including ELF .fwsignature_* items. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/hal.rs | 3 ++- drivers/gpu/nova-core/fb/hal.rs | 5 ++--- drivers/gpu/nova-core/firmware/gsp.rs | 9 +++++++-- drivers/gpu/nova-core/gpu.rs | 22 ++++++++++++++++++++++ 4 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/hal.rs b/drivers/gpu/nova-core/fa= lcon/hal.rs index a7e5ea8d0272..c7f12f2a7a35 100644 --- a/drivers/gpu/nova-core/falcon/hal.rs +++ b/drivers/gpu/nova-core/falcon/hal.rs @@ -80,7 +80,8 @@ pub(super) fn falcon_hal( TU102 | TU104 | TU106 | TU116 | TU117 =3D> { KBox::new(tu102::Tu102::::new(), GFP_KERNEL)? as KBox> } - GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD= 106 | AD107 =3D> { + GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD= 106 | AD107 | GH100 + | GB100 | GB102 | GB202 | GB203 | GB205 | GB206 | GB207 =3D> { KBox::new(ga102::Ga102::::new(), GFP_KERNEL)? as KBox> } _ =3D> return Err(ENOTSUPP), diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index aba0abd8ee00..e709affaa7e8 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -34,8 +34,7 @@ pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn Fb= Hal { match chipset { TU102 | TU104 | TU106 | TU117 | TU116 =3D> tu102::TU102_HAL, GA100 =3D> ga100::GA100_HAL, - GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD= 106 | AD107 =3D> { - ga102::GA102_HAL - } + GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD= 106 | AD107 | GH100 + | GB100 | GB102 | GB202 | GB203 | GB205 | GB206 | GB207 =3D> ga102= ::GA102_HAL, } } diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/= firmware/gsp.rs index 9488a626352f..c1f0a606f5c0 100644 --- a/drivers/gpu/nova-core/firmware/gsp.rs +++ b/drivers/gpu/nova-core/firmware/gsp.rs @@ -213,8 +213,7 @@ pub(crate) fn new<'a>( signatures: { let sigs_section =3D match chipset.arch() { Architecture::Turing - if matches!(chipset, Chipset::TU116 | Chipset:= :TU117) =3D> - { + if matches!(chipset, Chipset::TU116 | Chipset:= :TU117) =3D> { ".fwsignature_tu11x" } Architecture::Turing =3D> ".fwsignature_tu10x", @@ -222,6 +221,12 @@ pub(crate) fn new<'a>( Architecture::Ampere if chipset =3D=3D Chipset::GA= 100 =3D> ".fwsignature_tu10x", Architecture::Ampere =3D> ".fwsignature_ga10x", Architecture::Ada =3D> ".fwsignature_ad10x", + Architecture::Hopper =3D> ".fwsignature_gh10x", + Architecture::Blackwell + if matches!(chipset, Chipset::GB100 | Chipset:= :GB102) =3D> { + ".fwsignature_gb10x" + } + Architecture::Blackwell =3D> ".fwsignature_gb20x", }; =20 elf::elf64_section(firmware.data(), sigs_section) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 8579d632e717..3b4ccc3d18b9 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -83,12 +83,22 @@ fn try_from(value: u32) -> Result { GA104 =3D 0x174, GA106 =3D 0x176, GA107 =3D 0x177, + // Hopper + GH100 =3D 0x180, // Ada AD102 =3D 0x192, AD103 =3D 0x193, AD104 =3D 0x194, AD106 =3D 0x196, AD107 =3D 0x197, + // Blackwell + GB100 =3D 0x1a0, + GB102 =3D 0x1a2, + GB202 =3D 0x1b2, + GB203 =3D 0x1b3, + GB205 =3D 0x1b5, + GB206 =3D 0x1b6, + GB207 =3D 0x1b7, }); =20 impl Chipset { @@ -100,9 +110,17 @@ pub(crate) const fn arch(self) -> Architecture { Self::GA100 | Self::GA102 | Self::GA103 | Self::GA104 | Self::= GA106 | Self::GA107 =3D> { Architecture::Ampere } + Self::GH100 =3D> Architecture::Hopper, Self::AD102 | Self::AD103 | Self::AD104 | Self::AD106 | Self::= AD107 =3D> { Architecture::Ada } + Self::GB100 + | Self::GB102 + | Self::GB202 + | Self::GB203 + | Self::GB205 + | Self::GB206 + | Self::GB207 =3D> Architecture::Blackwell, } } =20 @@ -139,7 +157,9 @@ pub(crate) enum Architecture { #[default] Turing =3D 0x16, Ampere =3D 0x17, + Hopper =3D 0x18, Ada =3D 0x19, + Blackwell =3D 0x1b, } =20 impl TryFrom for Architecture { @@ -149,7 +169,9 @@ fn try_from(value: u8) -> Result { match value { 0x16 =3D> Ok(Self::Turing), 0x17 =3D> Ok(Self::Ampere), + 0x18 =3D> Ok(Self::Hopper), 0x19 =3D> Ok(Self::Ada), + 0x1b =3D> Ok(Self::Blackwell), _ =3D> Err(ENODEV), } } --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011050.outbound.protection.outlook.com [40.107.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A8F33EB80C; Tue, 17 Mar 2026 22:54:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788054; cv=fail; b=nNFOToSOqQtW0kaLeCL/mqSi1FW/XxS6KKosh6uR2PzzS/EtgEToR8hfLuzOODhpiONyRBHc6Ah/MtG/XkQ4tCegqPvwNn6NkdKiqJIHR6i6J00YrPbvQLbIRuxYUF+Hp6r+K8xoAH/Y4cya07oMW1mtzXNi8YlU/wOVJe3AAM0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788054; c=relaxed/simple; bh=KC2ucIDfXAxqvRr1F1DH9KIChd1pAr1Le+dyzzANGus=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=aefxc6pvw8aH9rCs1SO2ysLzuK23R0zhukbLuMK3vr/AqS7TGUADwrSkcQykK9WcxzKe3ihbZp05bC7o+KyMsPTcnvmjrl1Afmtqy9axNZ3kXQFW9tUL9U2NRpemOhkBaAZT7HLnVztd19ZsdpOlMWo1gTVHATM9STI0Z/iaM2s= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=cljygy/J; arc=fail smtp.client-ip=40.107.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="cljygy/J" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pmwwR8/WrEYcFfYEjPDDfe9neyjLITXLu6r5Tc1l79aCNQtoWDNsSPCx8MBcJi/3nbxvejcuec2Nr89KCE/m0wsgOuFrvPBBg+h+aPzOQ+fGpJ+LGT768O1Ztlvej6ip3TeuPSgLu5nH/nQ9MNTwfCVGRbRr01eN3nfw13ZUoK2UJ+3fSEQG8F9+HELDJgeqH3xhMtXpz9FqbQwG8KtlG4/7U4XFTUaP0hD2l1bI+z5x+DcL9CyTR1il+qrh13xhWeJ8C3ldMTOFVFtJc3OqjfsZEkOO2mF8fUgwmCiaxj/3YabYNdPlqdFsnqE1xdTysIs4XQRhUkC1pCMIzVv6Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uv7SwPecmmncG6cRG6fVOJqKT2hQh0muFNuLY/Mj9DE=; b=F4GieFCDqwDOSxq/cQxzBPn7zHH2U+IBVP1U7scqKvvKO+lnNZoF0cSEhVrP8fDaAUGrYNb/77hDlXEWlV+Y0bEPdDU4xaHzr1PVNQo2k8a4kXf/5DCNLaNUTpak+IUkEkZe/Sdaac0C1tz536qFDGKczmrHgX0eEjbr+DRPWuA7XHg7S7Ni4rk1MofWu+8GMASqwc4IuGc+qhzFnrLwtgFTM6ruxgTpJatcH6n+3JFrN/SMMibkBg+TosY2GghXxr6UILZsHvxKxqbEkyJiKGDYe5W8ocn7JswAxccTT7y/dVS5UVVCYYfO+3bmPKYWex8SwGOr89M72/F5scnaZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uv7SwPecmmncG6cRG6fVOJqKT2hQh0muFNuLY/Mj9DE=; b=cljygy/JrcObG6cIGFGRveurjvHyYyixdd0bcJU6ekzGvv3AK2kcSdL5zPiKD2GM0NmdvZLFvzAe9MlJqSIRo1nyWy27LO72eUas0o6gGtD/SGVeGqupfaERAp6/k0gQwKPvSukSb4O2+yPlE8VQFnzhp93BUjerGW/Qc6dejPe2raq/HYFQ/dVvO9x+/YDMH20eb2ZNetzUts+F+tSBG9gvKBFBZDuSLCW/HYgscSlOLxHrX8uPoQwmKuVFx1PDzetmIb4mEZgvpFeAKcoqf2ZwmmkOOP9sOxII6aHH3QnOsmLhv9RtLeWRPikjN/njVnWPP+Wr5csyRjYcWwMSSA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:01 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:01 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 02/31] gpu: nova-core: factor .fwsignature* selection into a new find_gsp_sigs_section() Date: Tue, 17 Mar 2026 15:53:26 -0700 Message-ID: <20260317225355.549853-3-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR05CA0056.namprd05.prod.outlook.com (2603:10b6:a03:33f::31) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 8034970a-9412-4744-e731-08de847814b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|7053199007|56012099003; X-Microsoft-Antispam-Message-Info: GhDUZz5tHWMxqdWGBOyqJG8whoO6lHsWrtj62eNeniHwppOb8qfF8qWJ/r/QR3cGblrscPBEDXnqr8lanRwXYLcoyYLtGV5ACyDVPXbfGWkhk6OXXV2mg6+0GpY2hS9HnaKVOf+nLctTrgbPsvjlNYopUQS92wZ7uU/89q0pK+jSPQPDQdmHCpAWsXVpeXkfKRIf9RbdMYoclp1hZijelCOIyo0690CaJk5FIrOpfklLAX2g2x3v/GfLAR9PiyLwhnVYZPmNiOPlgnDBVVoae+Z+DDomNNmLTQwRK6brA2GuA8ymB5LClamVQI1lAzpbpDlQEUOCV2sNOkpOLmzF/RvvWMa8+OMsRp/eC4/4AtH6RL44mmtzW+dZamW3gglB9W3EnWvl4jn/oopn0lS2ZrYNdoFzBvwaO+iwkjJp0/jUHz62xaaJLCZp7IN5ElHQ6ydWg8ReHUWSh51JpiCgdmcgHY3AlVY1GzSDdaHnQkcWiOBj9KwHCECmlsRjYAbv+/CJtAv9DBl4F+4W5RIGcMwfGEZdP1f0IrThrj4DP/UvDbs+jYzYlhB+1iOWaO6WK2VtY7kfF43bGcyFnY4Kl0AtV6eUJ1plznGtbwP0gBfrehSU9dTMDA8tQzU9GR5PLCH69n+mXBMo03ttRcFn9yvsXWfq6tYElwTV6T/ZLxBu4v2zoIOEm+jGxuzminYXucR0R1ralqOZJdi0v3cIskd18e4eROEwQefm2v+JhoU= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(7053199007)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?uIh7bRkGxZS+EbtAosKf6mh9hhtRtxVdKkkuh9pzq4IqzaNIZ2z++a60xdtY?= =?us-ascii?Q?UzNVQKc2k3FTiYU+SWk4R4P203HFjiy4Tk7lVkHDLre/SsKfYduijxAv42Ky?= =?us-ascii?Q?494D0Q04j7xHrvhXXh2HjyWBsP1SO2kIJ/YmuIb8t3pUg4GPgqIIVjiXtNNN?= =?us-ascii?Q?8KLONDFhN5yPeGd/NcF5a5e9EMp5fegWMAVhBTR9+x6X9QJSelDHyjUDwXjE?= =?us-ascii?Q?otAcksJYSZqiOgrRezN1OBmbFlJibhfgOSQV6LhkEfmKsiFOeM6dWZLQNT7h?= =?us-ascii?Q?cokA2YzIqEz6IRU+G9H4z2B6VJM8PR0xoRhq/atgo5DJSz/B1rVbCRIIC3/g?= =?us-ascii?Q?ZAdEF9mUpGeT0q1qrH6CxzkVtaJjJ31B3evnX8OTKL/HCDMGRXxh/UnjWWtu?= =?us-ascii?Q?eBbd4D0Y481Ki0gND++PKqSaiX0BvWCSx41PLPz7mY3XdJNk85CR/AGfR495?= =?us-ascii?Q?fNCzfgcVqdmASLsxiXusJsGs0vbx5IY3T5DpWOfl/3pBV4fKUfvY9wwTDkW+?= =?us-ascii?Q?eEbqTjPPI1nUXgjqAQcLC3nzYnmEKFnj7lz6BMmG7tpbLLCboqmnNLvuduDQ?= =?us-ascii?Q?ieTfZYT5JFunPSM3MMPih+MhektA0L8Ts75zocNICNVwamj71nLVW1Fw8zkK?= =?us-ascii?Q?RJ6D351MiRvn+rHHL5qzIjUKM7As7iEDwj7GyTczFbQXyYxKCXZfQ8/pY+0A?= =?us-ascii?Q?rSH+0Whjq6q+o1hC5DjnFScB342KzP1Saarm/y9GLwd2+C5mthOmZ1F9CyF2?= =?us-ascii?Q?Rniw9k1U5qNypXuZnHPzro91zOGB/mILzhQI11iYoT1p5oUBCZ8RpE9Na7pu?= =?us-ascii?Q?w4q9CshlY6RM3s7g8WuXZtQwEieSI6u+QHbfY1zk63wYi4sN+NtpMuacqPKf?= =?us-ascii?Q?6WL6RS6/2jyqd3iRONHSEDcY8EHfEfAqRxbK6TMlAnXUFjtf5KlCyjCL75Sk?= =?us-ascii?Q?BcyRJeLujx48s96nIDtXjbOoyZGL4wZ7m8XNV3G8qcA9LLlTfDntDbUnvho4?= =?us-ascii?Q?3S46IqM+1pfbKCHUHEH/84T1QIf8SNIsreK+nh9oR1SUeyo8WmG7rDv6JhQJ?= =?us-ascii?Q?sK0j/v6N6ZMCu7Y9VFYGIETp8ogwlkz1COKk0819PbxjejnlOJ5ztvunGbj2?= =?us-ascii?Q?x7H6lCT9K2v4Wl2rHyPVeC8LVZwqfHyHyktvf32Sqoqg7McrwS5wjwXMfNjX?= =?us-ascii?Q?XGIHeci7h7Ib5wvgz/oNzB8LKOb6u+fgzt4QBAxj9/1rb7uLS/5tRSxA/f0D?= =?us-ascii?Q?kqqUG3ktcNHua6BQlDqWtGTAZ5Xry6z0vXdjOAUDvst8wsiITNi7Al3n0JPE?= =?us-ascii?Q?O8b8Zpd2HivXCBOwLGULV8qjAbJZUoyMBFLEBbF1+rof5HQooWKD1p6+AYPf?= =?us-ascii?Q?QzQg0WgFPxfu19lP5DlSUeOq4tacNdU7JC24a+vYznhH8+sv2+LC3lxo4AI+?= =?us-ascii?Q?8O0PQBZfy/i/EBp96BRbUkrbVKEyTT3lVn9hjxQ5rU3IrOMeazdDVL1WCXXZ?= =?us-ascii?Q?qqfJWyhiM1CXBKqprrRBOCJsNM23Mbn8Zz4UWTtWo6YaRbRUDqlZT97G3F1F?= =?us-ascii?Q?SgxvQ/1gHjOtHKVlHSq38AilE4P0JPFdtR3RLME8rKprC8kjusy+FU6CYhO/?= =?us-ascii?Q?mjZV4vJUx/k7iGDtBdJA7n5R7UVw8Tdjz3Lr3i4FdiPx6CVSE3wBLFVBxOh0?= =?us-ascii?Q?t0v3A2wuCoUdUP9o4QQV4oYH4VWFVCj04mmqbb02o6As+lUbyhWKcme7aN6E?= =?us-ascii?Q?tbcElhNYew=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8034970a-9412-4744-e731-08de847814b7 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:01.2976 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6WWEP4fdoHTjKtvsG0Fpvb3a6NsIgm1DcmK52BrCq0ptVPfFXGhWvJ7TvkKLaj3iDEfHHGUmuADv2qNs9/G0tQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Keep Gsp::new() from getting too cluttered, by factoring out the selection of .fwsignature* items. This will continue to grow as we add GPUs. Cc: Danilo Krummrich Reviewed-by: Gary Guo Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware/gsp.rs | 36 ++++++++++++++------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/= firmware/gsp.rs index c1f0a606f5c0..8bbc3809c640 100644 --- a/drivers/gpu/nova-core/firmware/gsp.rs +++ b/drivers/gpu/nova-core/firmware/gsp.rs @@ -146,6 +146,24 @@ pub(crate) struct GspFirmware { } =20 impl GspFirmware { + fn find_gsp_sigs_section(chipset: Chipset) -> Option<&'static str> { + match chipset.arch() { + Architecture::Turing if matches!(chipset, Chipset::TU116 | Chi= pset::TU117) =3D> { + Some(".fwsignature_tu11x") + } + Architecture::Turing =3D> Some(".fwsignature_tu10x"), + // GA100 uses the same firmware as Turing + Architecture::Ampere if chipset =3D=3D Chipset::GA100 =3D> Som= e(".fwsignature_tu10x"), + Architecture::Ampere =3D> Some(".fwsignature_ga10x"), + Architecture::Ada =3D> Some(".fwsignature_ad10x"), + Architecture::Hopper =3D> Some(".fwsignature_gh10x"), + Architecture::Blackwell if matches!(chipset, Chipset::GB100 | = Chipset::GB102) =3D> { + Some(".fwsignature_gb10x") + } + Architecture::Blackwell =3D> Some(".fwsignature_gb20x"), + } + } + /// Loads the GSP firmware binaries, map them into `dev`'s address-spa= ce, and creates the page /// tables expected by the GSP bootloader to load it. pub(crate) fn new<'a>( @@ -211,23 +229,7 @@ pub(crate) fn new<'a>( }, size, signatures: { - let sigs_section =3D match chipset.arch() { - Architecture::Turing - if matches!(chipset, Chipset::TU116 | Chipset:= :TU117) =3D> { - ".fwsignature_tu11x" - } - Architecture::Turing =3D> ".fwsignature_tu10x", - // GA100 uses the same firmware as Turing - Architecture::Ampere if chipset =3D=3D Chipset::GA= 100 =3D> ".fwsignature_tu10x", - Architecture::Ampere =3D> ".fwsignature_ga10x", - Architecture::Ada =3D> ".fwsignature_ad10x", - Architecture::Hopper =3D> ".fwsignature_gh10x", - Architecture::Blackwell - if matches!(chipset, Chipset::GB100 | Chipset:= :GB102) =3D> { - ".fwsignature_gb10x" - } - Architecture::Blackwell =3D> ".fwsignature_gb20x", - }; + let sigs_section =3D Self::find_gsp_sigs_section(chips= et).ok_or(ENOTSUPP)?; =20 elf::elf64_section(firmware.data(), sigs_section) .ok_or(EINVAL) --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011050.outbound.protection.outlook.com [40.107.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9CD23E866D; Tue, 17 Mar 2026 22:54:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788060; cv=fail; b=fIZ/tDSt8afHNMHBIIHVZmZEMLucCWq9vpbVvB6Q11sO5zwbQMU9VuRoz7VgYO/HTTzoSBlSJjtyddZctUws4nSmpBZbuCLR5dzjBvxyqGJjiFJyuglL/DuFgVXTBbk5wZIoGs8eB3bX9+SrKuGDzNPMKSxPwasgGvTFF3FLaek= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788060; c=relaxed/simple; bh=TAJKGRXFKGRrb9Uxsn4wPwawQlU++wiPLveNOozUxyM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=J8WDJFClwsEMvCiQkdBtWz1arK44eWcsxn1zIwOYQMncE521Qjw2UR19NNj+wC0Ww4cbCfkn/TrdihPzyiICnCH6vyD8/FN+2PVsis5ycbv4xSrCIyy1f5OTuXUXLJYYDGXRRU5h2azQonMVR6SNeqS7L3uLYyW8U5rxawZFgYo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=i9JyK6Bb; arc=fail smtp.client-ip=40.107.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="i9JyK6Bb" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=a9ya7ptQIjFAxP4TxcBcSV7NLNa/YlECD8E31vKR8g/WCIp/aQsBzt56yIB55yB4Tie7XQ/9wgEmByScIfSp9CLgtXod0V8lcJIt9wQwa/EQf1wmn1R17tTZQAHHK8O9aVmt34va5WtfXq07kvYDjAjaDQAuYptxK3YQOHmK/vH+pHJXjMEp84dXEmaLMCNS94TdQ1PYq+DTy3dWruuRwdsjfbajh3QqYOEmNHuLGctVCSHvqd8y4lYgVbqQ/Vqzf6LiNzIXcwEOK3GwCepIP2eGTLfSnzcbEkVHCH1s3cLato56XB3kFu9Qcf83PIRZsMNunRNx0ii3yg7kzptpNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MtXynqz+dK5MHq399KbbebQm50z6eyjYaBpIt0SwMtU=; b=zHo5zvO1SpUo92dVwl2lmJnfCEVp1v37XDxeVILre5Go8CilPzjvvcv4UwGX73bawoMTlMpRAwsr1w/9vzZnVV73gyHR+cpZFXn8WhLtSS38oxO1IQBSGhsXYQjkMiEm5jdttb+HBwzPRNrMk9NAJU2OUkX+0YHsUJ0mVS98vhXshhUhAc8dBW2AEPo0IKpDfJQ/jUi10qpMzqWiS9L8/oDsZ1jpA645CN6ah5EQlXGMuAWUnCJIU8JChkPu87EiAUeru1F8hITXK6QpnGi6ZQAhvDrYmEzeL3Pg0gyEbvejTgSGeO9RTAyrG1JjW77lNWIiHwCCVkrQy+bK3rQI1A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MtXynqz+dK5MHq399KbbebQm50z6eyjYaBpIt0SwMtU=; b=i9JyK6Bbs2MHepajSG79h9QNkqUVjDKq3yrDlJxuTAE8dpkqK3lG1nyUAQozu/iAd+bdsKunZnkUgTlGZRdQNM/yRrvt33sMjOAFeu3LYrxUpBu2sWWTg2Of5XO5ToekIeNHgZvWiPkUFfUop1GbAUZTK83Mo5pTXBYVuCM2GoFGjiZLuVqW0/U6NH7GEBvn+Dg5vXoDNjutAUShYkHxM3Ir5dVgpHuPdquS9VDzgBGuu+UqUAUgXqSkzqJ6tDRx0s/dIS/D+41XQLFdxMX2zLlUs/Yf92Fp4PMrgh8iAMM+/PZUZRwRPRszkZf6kPY42fv9IbUIiTdauqy4nxO8Fg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:02 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:02 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 03/31] gpu: nova-core: use GPU Architecture to simplify HAL selections Date: Tue, 17 Mar 2026 15:53:27 -0700 Message-ID: <20260317225355.549853-4-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0219.namprd03.prod.outlook.com (2603:10b6:a03:39f::14) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 8e9f6fbd-2da2-496e-c7b3-08de8478158d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: tumCbNxYcAH45piqePyOSYpEXOLIp7xUGaab7OQjKFimpsUc+3PSWEqG5reAOUuwWc0N6Gbnd2dgqOss1GjlAyiB6eakAwwSWrUzu4tLd5agRJdI6aX/xBczYLFMErvD2E++M6dsf9Rn26ZfZINDlWdi5SO8prlW9zPQRCVCXR/+qdpPQi32UDSvff78xApJwFK8hqPgIvZ7cwMPPBDs/RLKPKO0MHBw+Kqq7t5M58fRFrU9NkEHSXvDCdfJ0Q3n2yaFf0XWghEaOTO3hq63IKTXZfFW0H9mkrUfuqD6yjjxkoPX/5tPRJeVvg84AXFyCIRkym2Gtre50kbE6ovyTPrwNhMYpgShCSMkLSSI3PFn3Bh5WH20EhD6Hko8l3VHhxYqmtiCO1LnAv1CwVcE42k2X664y+atx90PBOD+VOgK5f07J3OlOnT2jpyvX4qZpKhTn4TvZdqqULLnSFL11YOoSFPQbvGGwxyiNyg90I7N46x4GXODx2twIdn98n+QmBiPit2QS/hDgMbWrq7NfyihaPWG8oTeJyz1hijRZ5ERjc7ZQypX5hPyWnFMgTtxLB2BvD1N+xZOok08sxqyPnOiJyKd2b23nWmjwugpeqCpH77CVp3gIoNva+5haIh+uweyJ5Nta1EKXuboKNipcQHkzTCXdJqGp6tRIemwxliE54WUEizenhN78YQd17rV+9bvctAG7aVUpLzuSts7mZxYc4gnm75q7ZAU0mPi+9Q= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?GVWrb78Zs+jyPlXNJq8vBaJcJNTsPGyPndT4PJKtgw3KrA5TZXtwMDSuX7+r?= =?us-ascii?Q?SjwMAUR/JwR4t0chA9r2A71rPLGnip3l69RId0P8Tf9cZ8Im8IAF/v/aLzL8?= =?us-ascii?Q?S6Et63z/4x+QX+f1AqpHeLu64ITffZj7B5NISgT0jXaMtIHn/h8KP+gt9WcO?= =?us-ascii?Q?AuiwjQC9FBW1EwTkhewI5NQRUAFFsQrgkckNSXtrSZQYhl4biVj0Y7QCoDKm?= =?us-ascii?Q?2+QYwYfTbWnyOBEyJpVwfCZG7gXBOXt7/YUiFX4WLlgP/Wx6J+5X8M4NjvpJ?= =?us-ascii?Q?sSCOq5fk/REKkXsIh6vHu1REwb3LjJDJFgAVBV8KGXE0d0+KhSKJJc4vmT6S?= =?us-ascii?Q?k80FmxJYYqVtD4m2od0Tgu/DE3zrHG7/3xswEQQFmZqb0dX3dFatlyhsESBn?= =?us-ascii?Q?WYE2zgqHVxk6tRbtDd8M6FlpBvm55j26IvmN1PjNto/J1cwRjJkg8iEBRYmI?= =?us-ascii?Q?gdwodfQpi8OqYzTP5ZM82tOTAe6R2YsPqd0U5bJtGO+eiHqu9Psv73V3B66a?= =?us-ascii?Q?fKOGPImACCNeLQZV6+DH15IyrjFvSR0u9MrBoniHd9FmJlmaDxbPuBjLpUqb?= =?us-ascii?Q?MCOH8IqpIkWaIag4OEMzHc4v63jziF89OxVA29XCgYAcYTdUjeFs50yIUvgp?= =?us-ascii?Q?RIQ+eu4rHExILkqbYsmrO5EHGolBLYYSh9YbcGMvXAqy/05J2X8JR/7jYQA2?= =?us-ascii?Q?XuiADIokwPXogR+Xfhde3BuliEmIaFDV1WCnMqiTXejV9kE5hLssQIYbijCc?= =?us-ascii?Q?WpVMjWUz87tmeSEB8XXqW8LUOJQIzoLlBGlbloypDEqG0tCye1Soazch/yyU?= =?us-ascii?Q?7JrJU+4U+WUOA6A4QksVkzzO+zCpg0aJe8B2c25U0lLcOTwf+WU2Rf5dMsej?= =?us-ascii?Q?oHcf8U+kXa1X/6/C9CGwuRKDWLrlNeGmtM6cTpWbRhGHoCFSHO/MRrLtJPm3?= =?us-ascii?Q?mgQssMbvk1fP4rcv0hv4fs/1yMX2mNy1MNADhdRk8NXYHxQSu69x1Do4s034?= =?us-ascii?Q?flF7fO09JhOzcLoph2BNZGxdZjOrZbQlw4qNmqIpF4cmVJRHkVLYkMyP+2zZ?= =?us-ascii?Q?jLfbdlytTezoVwc48w3V22ObOs4fLwCIfgOvBAKTyb+E88I90gHwYZqVpA74?= =?us-ascii?Q?OLzadnJswFjc3Fn9rsTV9bHvY5yJB1xeP+Lja1kIKzYqbRhcXS7RN1s7yw44?= =?us-ascii?Q?ZGQYanNoF20wYEiVI20aiuPruugOxjlHQH40TwS3ttgr8m11FO7FfZ+43hRC?= =?us-ascii?Q?5wvVnAdXIZgMxskKL/rWSzDjYt6jcChYm9LXbAjdkyfspYkDlCSKqDF32G7v?= =?us-ascii?Q?ghF5tGgkbl9uCR0zZkk9sDywp5/ASywZMA9KX8a/049SB4iz1mRvk9QNwRud?= =?us-ascii?Q?vz1vdpotRBAo/4cIz1v+D4TyjeZtA8bXozzu58jj2aSk8ZzJDSjnBUNORJUb?= =?us-ascii?Q?+PPnNAZgsl/6oD8WQys2Yz+z/uZ7bPOY75gc3CodLywK/27otw51ynSnYolC?= =?us-ascii?Q?jNK7W3+O/rajg9KysXMnITasZZWi9kzfmQLrD8Baq+6yvXXdV5HtRDybfefS?= =?us-ascii?Q?+nuvUJtl1l60JvMxHZoG+Fe6ZMY3zllJZs4fQsesWVPKdAQavEqFiZSDNnf6?= =?us-ascii?Q?f1Q5V7l1NzXFmXqQRuihdjrwhNtQRjsQx+DSA5v0Ry4Lt8WNLQk6mvOFFUpK?= =?us-ascii?Q?rdCdnPhfRQsjkknlxZK+v2yi3ZKtTTeiNgeL2I6xBWsbl3AUrOWq/reVPOxW?= =?us-ascii?Q?PCZ6XBMPng=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8e9f6fbd-2da2-496e-c7b3-08de8478158d X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:02.7534 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OtOyfyhJQDp3HZ9U6YtPSusDJir0AP0Zc51Ca10+R9kXHgRmWKlV9WKoi/Pj3iEsA4r4K5nHgqArVzNeOxX/UQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Replace per-chipset match arms with Architecture-based matching in the falcon and FB HAL selection functions. This reduces the number of match arms that need updating when new chipsets are added within an existing architecture. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/hal.rs | 21 +++++++++++++-------- drivers/gpu/nova-core/fb/hal.rs | 17 +++++++++-------- 2 files changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/hal.rs b/drivers/gpu/nova-core/fa= lcon/hal.rs index c7f12f2a7a35..721c82f6a831 100644 --- a/drivers/gpu/nova-core/falcon/hal.rs +++ b/drivers/gpu/nova-core/falcon/hal.rs @@ -9,7 +9,10 @@ FalconBromParams, FalconEngine, // }, - gpu::Chipset, + gpu::{ + Architecture, + Chipset, // + }, }; =20 mod ga102; @@ -74,17 +77,19 @@ fn signature_reg_fuse_version( pub(super) fn falcon_hal( chipset: Chipset, ) -> Result>> { - use Chipset::*; - - let hal =3D match chipset { - TU102 | TU104 | TU106 | TU116 | TU117 =3D> { + let hal =3D match chipset.arch() { + Architecture::Turing =3D> { KBox::new(tu102::Tu102::::new(), GFP_KERNEL)? as KBox> } - GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD= 106 | AD107 | GH100 - | GB100 | GB102 | GB202 | GB203 | GB205 | GB206 | GB207 =3D> { + // TODO: support GA100. Its boot sequence is a lot like Turing, ex= cept that it handles the + // FRTS steps differently (specifically, it skips FWSEC-FRTS). + Architecture::Ampere if chipset =3D=3D Chipset::GA100 =3D> return = Err(ENOTSUPP), + Architecture::Ampere + | Architecture::Hopper + | Architecture::Ada + | Architecture::Blackwell =3D> { KBox::new(ga102::Ga102::::new(), GFP_KERNEL)? as KBox> } - _ =3D> return Err(ENOTSUPP), }; =20 Ok(hal) diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index e709affaa7e8..d33ca0f96417 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -4,7 +4,10 @@ =20 use crate::{ driver::Bar0, - gpu::Chipset, // + gpu::{ + Architecture, + Chipset, // + }, }; =20 mod ga100; @@ -29,12 +32,10 @@ pub(crate) trait FbHal { =20 /// Returns the HAL corresponding to `chipset`. pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal { - use Chipset::*; - - match chipset { - TU102 | TU104 | TU106 | TU117 | TU116 =3D> tu102::TU102_HAL, - GA100 =3D> ga100::GA100_HAL, - GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD= 106 | AD107 | GH100 - | GB100 | GB102 | GB202 | GB203 | GB205 | GB206 | GB207 =3D> ga102= ::GA102_HAL, + match chipset.arch() { + Architecture::Turing =3D> tu102::TU102_HAL, + Architecture::Ampere if chipset =3D=3D Chipset::GA100 =3D> ga100::= GA100_HAL, + Architecture::Ampere =3D> ga102::GA102_HAL, + Architecture::Ada | Architecture::Hopper | Architecture::Blackwell= =3D> ga102::GA102_HAL, } } --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012058.outbound.protection.outlook.com [52.101.43.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F3134104E; Tue, 17 Mar 2026 22:54:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788057; cv=fail; b=fZ78bVfk5O1lRw4+l5BE4XBiMoEP9MtR+hNfTRBS8/0HVV5UnFkCt8t0Y724MWM1mANnhU/Q5aRCiK4zi9U0VbhAGVOM1jgnLj9Kwf4fiMuqJcEpkvEhfwiVVXgXJ6U4l6Zk7D0zViaBO32n7+0oFRqiPKoKbRWZT7Of9aKuYis= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788057; c=relaxed/simple; bh=6UjxlWXvdqSI2p8zfrzCkCu/jhNLO8kW3eu+vLIb7aE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=MwCKj+iKuows3V2QniqOxApUQjfP/fUZxWk+pOJFo6bcgoN+jN4jFj43TZkZrKGGBxtbMF7HgE/UqZZ0ex84KuRR67Huq55YWIzWnJSz9kptEKK01cA9BIXeEPMe1dEL0EZnwhfF/8Je84xdJadjoKpPDYDP52+cc0faWWj54L0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=dsd2x2Q/; arc=fail smtp.client-ip=52.101.43.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="dsd2x2Q/" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=RxbtPnzYdXVKwrmButi8l+NcXUgWr8LlXEJOWdKpPjq7Rasg3aOjnFwTgIda7ljFUdZ9AuE/3g4QhWraXyP/5X8PPr43BUMfrF15CJGqYNQWvUevzKDVDbU1tzdy1gFr+AGQknbABmZxHBPqpiXLfiymlDmCGFvCtN9b4OpG9k7La4q+IfyC0gwMx4+uiDkbI2kzvird4EUvb4/b7yUk5IwF56ty59OTnXbwAXyurr1az6uP5/4MIY92xpxIFpqrI6lMTpKjYHSb5ygk4oQnPDeeRcn3TLwWPofklZLICFtnxSpEUffLkcFEtM3YCaNtefJbHeXJLMvKi5HCXKRU1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=wDC7V6N1u8Qd29esawTAkeYfOLonaVAiX1RjPOs4S7E=; b=DymGpk6vNlHZtwrXH+msAE5jLJ+ai9Iq5w6VnQc+xahjyGZM3DepxK8pr0v+WgRZk745XZR6Mx6Zbp5dMS3HuKd/vjHl/np8tydUBk1GNhh/uiR262cY+9SZsTdZPsmxL5E0PmHUxWM4W2x2olSnHPT3fRTlZRTgzpldPMplEICJ8v3YUScxvGJjDKBggt2ATfvUt//YVA8NLOwEvIaMH6o6NbGPtYKIHYhBLgDY5UnbvG90q9kzr0nPLvPQkiczS3wo07cS50vhGOPObFXcPpJo0XJSiLba7TggGOa+nf1qcb0aglWRpSzpurc+8o3T1CFDFJXVoJ3WuPGZUdGfYA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wDC7V6N1u8Qd29esawTAkeYfOLonaVAiX1RjPOs4S7E=; b=dsd2x2Q/x3mFExJUvQN40+67BSqA5BEjYfCrsUMNIXMfZ4Tpl53KBPxtLpnvpNgdywmPLwcmbdtuXGECjU39Xuy0hw0rzvfjuKOrRPKsa8pRNrhrA+12jDsC7jZZJvLZ3SnP7hCgs3ZoPKSru/uGghDkDk1Qxhw3BVjaA5mZgrI1OzRNkDOsADIjbC/ixkJQmKoRK1lVyzsNPfgi2Pe/ycTufpabGrjExhh1JSeTFmb8W3RNHqipjvXnT1zMNPEIxCk5HM2s7MCDbKnRzW/R5qEzEk6rhC2aulQuALPS7GN3YlW5+3x2Mo/A1jwiOSFj3KRQDG2JXAsJOAkYXWXolQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:04 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:03 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 04/31] gpu: nova-core: move GPU init into Gpu::new() Date: Tue, 17 Mar 2026 15:53:28 -0700 Message-ID: <20260317225355.549853-5-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR02CA0019.namprd02.prod.outlook.com (2603:10b6:a02:ee::32) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 2323fb4d-2a8d-480a-ba0c-08de84781643 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|7053199007|56012099003; X-Microsoft-Antispam-Message-Info: z0wVUuL8CE1QBVOATX6NTfgGVbszQWJA7zXxd9wUEKaSqDPucRH0RxfE/0ugdBJjzteDvziGUu2ds7ZPlae2Y24D7V557KsFGgKUgKywf81LVI9g0wI3CY+DPggkBYvorNjkyRrCd1azsR/Xsbj0TDhcgaYJsZFnfGm6PIurtC136Du0cUH5qLbwpM1ZwjdHHate3ZVesvV9vMwowoqXNm/F1vHdx/zMM0iLHMSflUAy/tpIToHnOe7lEkGHobkNSof5krOu+r/q+Gja+WEx5H2/MzWWGCxZ6uJ/BKZBVW1b1qlfxyn1WbhzdNVPRwc5Wu7tZvqVgI9mselP80womnfcU/vRYTQyrDw4Nc3WTAhqbNpiEEUc0UTi5yn+9NbzRJVXa2AYcSQLiztLksYyrEZRdSYYBzjtwOhjgt4GpLa2xJivwutI6fMmGMMUSF7/EEyWQris6w8s//IpoHdzCBwRtO+i1tvhBmMk+VlP7fwms9pNAOVJJFPPGxA3e5kqmcszeCwTugM95fR9KbsheVPRHCW+G6FAHyQ/LzRRO18IP4lDdw9jOKEPwz2Yxn7l56ThnASqC/XtUycRk+tKL/APdmRgfXxn8UXE78QE6qSGbbSIhl7P0X1VQZzngzpgEx4SoPLD9NzfFLoZCiAATnSRNhtuEpR//He6vvjnU+/fZJ0FJJ/e759+AtM6upeUvTHrrVzcxDzZ/ey3D2c8nhFtvCrz2WDkNXeP6N1NFA0= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(7053199007)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?T1yBbK4D3lkU0vYXRkXMTi2sBT6IVkNOUmVNO8IkpGfYlHApD7cX/zCOhBwW?= =?us-ascii?Q?EFc+n1GXmF7T5II41wKDnx9reblbqUN8K9eaQlVgb+y8gKBTNYbsXFR1CpOH?= =?us-ascii?Q?x8Z3VIFEqXbJrB0Jd8d3nD0wQgTGO1xDk47NUMqn5LJI+2ZDDir+0FOMNZ3Y?= =?us-ascii?Q?tnvypICyRmvvj0DyHiTNqsQFFd1N+ZlbUrwoRwOHvI8UhWJweFn0pnj7Vf8l?= =?us-ascii?Q?KgyD/AZJTOvrX+ofBcoYIKn/7e8fZioRPA02ndbSW+HStOQq86WL8HXW2X+U?= =?us-ascii?Q?CxVKEh1+gQele5JDTU+Mkbjw4Fnjsjqgr9Qe1s6c5cGn9ooZef3wTop8eu+x?= =?us-ascii?Q?+6KXxZAkzIJ1n97PmyQRe7LliCRT/DmZUqb5dC0NNioTdaNrKMbh50kcOTLl?= =?us-ascii?Q?N1RWpUcr36kfyUD6WgqjBXmjXekm3w920NhmRZ5ToMUbXQBr0aTzjM4y5vk4?= =?us-ascii?Q?l1Rl3/CR5VtJiN/y8ooAcCUDEAWJ1OuYU8JUaCXyfGAmpqIOerr2WliMQ9nd?= =?us-ascii?Q?NAgSR2XQZedgTgF96B4wYTGiKVSqlrAA5X215sO8VYE23xLj5GT6uQ3BZxaw?= =?us-ascii?Q?R99FTcYLfNa/EEBGpc1Z/Q3hjf7LZZ8s6HXKfkS9pKsP7j1fMnhNZ2/cZ/tc?= =?us-ascii?Q?DsBZ14do43MZqvJkcl2asH36lzVwDUJ65pnDUFaCIRaP14kiODTIvZc+EiIA?= =?us-ascii?Q?LAhzYRY8qNzvidZPjp4AgSF4d8BjffVQEeyKy7AoCZW3LFj5PWTn2jW2FuB3?= =?us-ascii?Q?EdQvBS2Jd5xSJd7oERwatn22Q+evkEQKlSkC65v9IDz5jTrU+t4qyKE+bqTF?= =?us-ascii?Q?uXjoHUlLEGCp6Np7M8ZHzbEMEYysPWWbuYuTqSydHQ8pgvb1HmeqRoJj7P6m?= =?us-ascii?Q?OrfhUBiieoaosplBdYb0iSdXemxZaObCMeYROie20yTJ2T+43PGbDnjnNEFs?= =?us-ascii?Q?JR7iDP2ilgql+iMamY+xE8U+JFgG1Jf/MO8gh33rU9soe36n+20WSyp+0ucR?= =?us-ascii?Q?aZSD50tCz75pui4DxVsTJdLLAISFkSQrR9moNDWprJB/q7XjHejxgW1HymDF?= =?us-ascii?Q?1tPGuaw95f/M+BucZ2TP/AXrMiEmiDz3twlcYuqbpGMD+gsaGRFwe0ePYWya?= =?us-ascii?Q?WwCOKR3mpQGkqUuNROcrjIqUCQYnNF5opcrWQYWmGLMqCRRzVfUxcQp+CvKa?= =?us-ascii?Q?T83X2zEmQT122P7IVfpcJsbOoL2KSuzCQeM5lDOunyZBa7Lu1DsjWkxnWy0z?= =?us-ascii?Q?5raMQwcQfcLPtiqk11/dK0oHMw70dc9KN1v0vJjSpiFtlFxTZ9XcgOVPdQTN?= =?us-ascii?Q?9kWBuECelzr5VkvN9obgbewOcRqzzphB6q1ObrIOxoxcrGQXC4VTW3SIxrib?= =?us-ascii?Q?kbm+05i5RrD3w7inRA4C3SqdclSXDznlUT0CRKqooykRGi3QDbk58PLTbquV?= =?us-ascii?Q?9IT07/BAguWyb2CqelNpiKfsJABWZ1iVguOn/9TzFrLoNTXCLjZ5JxBTGn1d?= =?us-ascii?Q?q91CNkioDJwtHMtn9o051FvaQQTODZ4s2bo6ZrJDwrgMW3NoOPvgF87l7jkM?= =?us-ascii?Q?LfLm4c+bg57f8bnp1i40K46CIKw9KrbSvqCrEpVslReH4RoXMf3Dz1Hpdiv7?= =?us-ascii?Q?pu3A4UnmxOBLv16i8qzt1D6IAzvrziAL+lL+WhpzoUFzdhanMVSBdQCMaZzN?= =?us-ascii?Q?0UOtCoNVHV++IVyEatpMuC2WacbL7Qwr3GZWShjVGdd/CLJzlHqxGYdWWfdu?= =?us-ascii?Q?5TgbnTCYHA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2323fb4d-2a8d-480a-ba0c-08de84781643 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:03.8938 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7FVmdO04AbYCZm6t+ZAINLe22nHLT4lAHzcrc8j7Juh6MF1QfOOVr7dyff+etTuxpVjqze/QvRGyJbkLXMSZdA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Move Spec creation and the dev_info log from the driver's probe() into Gpu::new(), so that GPU-specific identification lives in the Gpu constructor. Restructure Gpu::new() to use pin_init_scope wrapping try_pin_init!, which allows running fallible setup code (Spec::new) before the pin-initializer. Add Spec::chipset() accessor for use by later patches. The DMA mask setup stays in probe() where the safety argument for dma_set_mask_and_coherent is straightforward. Cc: Danilo Krummrich Cc: Gary Guo Signed-off-by: John Hubbard --- drivers/gpu/nova-core/gpu.rs | 49 +++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 3b4ccc3d18b9..8f317d213908 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -102,7 +102,7 @@ fn try_from(value: u32) -> Result { }); =20 impl Chipset { - pub(crate) const fn arch(self) -> Architecture { + pub(crate) const fn arch(&self) -> Architecture { match self { Self::TU102 | Self::TU104 | Self::TU106 | Self::TU117 | Self::= TU116 =3D> { Architecture::Turing @@ -241,6 +241,10 @@ fn new(dev: &device::Device, bar: &Bar0) -> Result { dev_err!(dev, "Unsupported chipset: {}\n", boot42); }) } + + pub(crate) fn chipset(&self) -> Chipset { + self.chipset + } } =20 impl TryFrom for Spec { @@ -289,32 +293,37 @@ pub(crate) fn new<'a>( devres_bar: Arc>, bar: &'a Bar0, ) -> impl PinInit + 'a { - try_pin_init!(Self { - spec: Spec::new(pdev.as_ref(), bar).inspect(|spec| { - dev_info!(pdev,"NVIDIA ({})\n", spec); - })?, + pin_init::pin_init_scope(move || { + let spec =3D Spec::new(pdev.as_ref(), bar)?; + dev_info!(pdev, "NVIDIA ({})\n", spec); + + let chipset =3D spec.chipset(); =20 - // We must wait for GFW_BOOT completion before doing any signi= ficant setup on the GPU. - _: { - gfw::wait_gfw_boot_completion(bar) - .inspect_err(|_| dev_err!(pdev, "GFW boot did not comp= lete\n"))?; - }, + Ok(try_pin_init!(Self { + // We must wait for GFW_BOOT completion before doing any s= ignificant setup + // on the GPU. + _: { + gfw::wait_gfw_boot_completion(bar) + .inspect_err(|_| dev_err!(pdev, "GFW boot did not = complete\n"))?; + }, =20 - sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar, spec.c= hipset)?, + sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar, ch= ipset)?, =20 - gsp_falcon: Falcon::new( - pdev.as_ref(), - spec.chipset, - ) - .inspect(|falcon| falcon.clear_swgen0_intr(bar))?, + gsp_falcon: Falcon::new( + pdev.as_ref(), + chipset, + ) + .inspect(|falcon| falcon.clear_swgen0_intr(bar))?, =20 - sec2_falcon: Falcon::new(pdev.as_ref(), spec.chipset)?, + sec2_falcon: Falcon::new(pdev.as_ref(), chipset)?, =20 - gsp <- Gsp::new(pdev), + gsp <- Gsp::new(pdev), =20 - _: { gsp.boot(pdev, bar, spec.chipset, gsp_falcon, sec2_falcon= )? }, + _: { gsp.boot(pdev, bar, chipset, gsp_falcon, sec2_falcon)= ? }, =20 - bar: devres_bar, + bar: devres_bar, + spec, + })) }) } =20 --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012058.outbound.protection.outlook.com [52.101.43.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 806523F7E9A; Tue, 17 Mar 2026 22:54:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788058; cv=fail; b=fzf3BgChNmlAi86DQUB5lVS4AZEWZa/L/EekdC1cIuGRROyiuTM4Q0FwVcQdyNust5RBxak0dCFy7hdOpaSRc5wpbXmqab1sXqeDa+NoKSKUNL+nuXX0o8iJHQa5pcq7hei8xOFOqJHocGmP8zn6cIjaYhTjUwX76wfojdrBh3E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788058; c=relaxed/simple; bh=HGGxnZAhH3ZQS29Zg9b5FbR8pj81XIsnn5OWf552kVo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=o2MmvOMao/GWITumNr37n6Neil+FWJ7oVsu8Rz4zCna3vUbqZiYz7fxMQ8jgUnKrhedzympLttiMLjfPzPVhQ97B82UMDr6SkyT5HkBKUWqcsDPP6MvrkVphnfnbDHJXXH8Q4CvxvS304IhqNFiJpWLxRq0mVbO5ZXnAVKsn2Mc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=RJdCwl3V; arc=fail smtp.client-ip=52.101.43.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="RJdCwl3V" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=l2d6zXMucAq+r/dS0Jss+Y4asvErr0iYPxpi6eCHkqhZsfKURMwUEcYJt6enUIQWMhnp+6xXiP8iKwOMT1XdODAloFBnaX8akYLrXzHRNQJXC2fVMJSwlgbV+7MFUh556fx4EFUMMqqT4Vmje7/UtY1/QniddL7o9+ApjPh5cbgRIeV+vwGL+DwhsQie3NAJ6Pw9XCR9s6IubmRtZqvQF/jPwNwnzlo7exNvQrjLlv0D7u0XT8E3jrYiBTUVNS2DYDohqU/MsPyuzqJUuR5qa0N+SSlIrDF8FkvIyErJ5WxqQXVUlpWCcnLYyp7NNKek27UImwooznswnsb1BcLHXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZLSyv8qCQlbZEoL5LOvLGSsg0FF553hpaFOyZaNpzks=; b=ejGR9JXeba3y9DGNyjwKV4pWWrXo2Jz7uWAMri3/cbZFxvkkUlAHc/2uDlqkY8h4KwJY02ycdUG65uk428zEmAmoayCuMuV8hH8flNhRtkWwQtA8rZUCelcmU/kIH1ydq7D+XprozRYFqR1eCYivpe4UaIMzUG6GiLUqzTB6MbbAHetPNo6ePpwWYEhytkhyJZNL1LHygjO6plOaEgbZB/ZoRu4EYNnFeYdsWc5aOLI3VzDYbHGbS3JgEMjkfd60+FxuDN/EqbK28aiun9DUuFsylCsJzAn+hXzwy96KhD9oCsTmjBAwlqDZqpCKC8FVv/4MX4FV95z4AImCaQ/lrA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZLSyv8qCQlbZEoL5LOvLGSsg0FF553hpaFOyZaNpzks=; b=RJdCwl3Vt2XFxyN7FDnQTFkPZMBvaWxpJtcXkFghAuLCNoPyqkjTDX4ADW2qIpb6x9cJqBUmsu9vBNF3jx4lP07ZgaA0iifvUE+51Z7e8ds2dGhKzshZ+0vJBbnKAhg2k6D5pvamS6t7+ll9AiZ1yYrZINMENmZHSUaluEGTH2ElZhsvHoL981osAlBs3CBVoF2hw3l+cBIGbk0NugEF+v4vLRLmlfYWMALizGaDGTSwq2OB2sHhdapSVD/24qkqbWJCfqXQu1xnEzHPYJhgG1fVsmqGMB3VudHN7WJJ3s4OfrCeDEo65eBZUjTwB4vDJP4JDBQpumZcBIN6RjoRHQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:05 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:05 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 05/31] gpu: nova-core: set DMA mask width based on GPU architecture Date: Tue, 17 Mar 2026 15:53:29 -0700 Message-ID: <20260317225355.549853-6-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0237.namprd03.prod.outlook.com (2603:10b6:a03:39f::32) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d2a25eb-2f74-4801-10f9-08de84781709 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|7053199007|56012099003; X-Microsoft-Antispam-Message-Info: esZyps3v9hv4ClnPxrJ0O442pLLn6tglDZFT/om4XCAVOGigp7ch5peTTQx0VT1zmmWYgYl38WAprNPCyXZKgwSQ1h/Tb/w2l4NsrJHr8B5bnXDVcabqS86l6JWFof1uLnFj+MENlwlnZyQstklgAYCSvBXCxtrwGxRjEIe95OQ97DiVuQCyahFid8IifbY1MRpUTRTEx6ys/5l1RDtWHGX9K5r1W+ik+TWRyrWW/cPbWr/sZWb5lEDY5TYc6emAbk/axxQPgJk6Gm1sLe5fPMQHEYiRVGnCcjY8u/cNcgXt9zNCJt+5+in+hOlve2q2hezpVLU7Kl8wmzWfapnUjl8z7LYU6vL+lX8hkrhV3MFLF+Hp3h/LDP6ZMgo05JMXcLjNkfy4IZkHPw3Pd3DxB/SbIE/+B8W6dQTBt0IzpPSuHSrVhWMOQFCTCn9yJMM7h6k58JCJd8ycEdsTkA0RbLngvQnWgJlOiQksav/0Qjy+QQHqhSii9kQu5SQjFFySRDxI3gYq1rsrrcEZGZhd1eDwS6nP9UW7GYbpwIYuqf6GGqQbx/NcsxGjGEHvtlLpPGPBDi2sLpHys8ZTTyir0Wsp0DMwlPHepqo257q7zMuI3fayiFzPg9pFmM8yCJbLuOQJ8uoNQnsR5JrMXgxCKEX+bU3SxgVbS/mPmlPR10o3jWB7B68NiDWJCJYnsOIAIlZWkUvETvwyspcdGfCe+GE847DnX9TLro+mICtx/8A= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(7053199007)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?/7zJonF7X5e4XjPB3E7P2s1TB0hqMkmuW08++PPlE/lkyWutIN2EmP6/BGnx?= =?us-ascii?Q?C6HswUTeW0eNdP5A6dUHCEsgMQ6GDEGPWAG6shlLptvx9hXV/m86RP4xIgau?= =?us-ascii?Q?ulk3PYOiHOsz+jB7dZzeB0dek39EXVYMYYk/lZsaGkgzcJDRu2C6xKwPKt3G?= =?us-ascii?Q?GPoW6+hoDH9ynfEoSsOn0Mg4Am+cxEB5KyIBvWfZPzmIsuv5SeEzxGjY3THz?= =?us-ascii?Q?o6h9Ve74hIJgZnrYeOCWKw3WqthBA/Cu+8ecBHZVHs0udH10mFjWVB8Et4Um?= =?us-ascii?Q?MMRwPUWRylBXsReJ/IRwCnU+T9kAzW7jsNS0rNJivOxVGzQZQTVV7BM4p4nJ?= =?us-ascii?Q?8VJZDylRtUvnqMTk+/eyF5kxS9iLJfoIgmdLBMwxfAtTJjDj3WHDQT1bYdDb?= =?us-ascii?Q?EJGcZnxfEQqqCN4C2RQ3F5vmHEG9IiFgewfQSpSzeYE5RIjA/Q2GobUD5SgC?= =?us-ascii?Q?g0qPdNJ5PuyeQz/906tC/Kbuo3dsswVS8zsgIal0BpL55Fn5BohFZCmV5STZ?= =?us-ascii?Q?LEjB09sLypJ0t76PIrtTJ5tzRpOjcM8CsmNG+hilw3NGvIkBXOxCzPv5Hn2r?= =?us-ascii?Q?YFMB8rnr7STeR1MfN2Hev1dNNhqv5WJGeCR//a6/FJ67qy78x++xi0vTACSq?= =?us-ascii?Q?ILBDVBhRVq2RJSuCRBaxeBiu9LqvPUAMQ0BBsUQ6cvQBt/bcOBk3fz7jqh6l?= =?us-ascii?Q?3kavxxCKL7aJPyzQ+UCyV8Dbc5i8tZn/DpB+72YnP0GmGwRy0P8M2G5kCrS1?= =?us-ascii?Q?ACVlaamewnuPDiBDel3IS8Dj2UXrUw/X/fonJR+JacEzAmZu4jO+mB04Uc4B?= =?us-ascii?Q?N7JUHWlnkrYyfKYH3bEaReXCbbi3HhNDQiSh9mtfpaiHRlQIrZY9QJOHD2m1?= =?us-ascii?Q?ZKyZwtT3ZfTOKDZazDBs8qwSqzziQk3tFarybpjGw5nKOK8TYLNiDnWoQZc7?= =?us-ascii?Q?AM55wamhRs2frt6WN+hJEtrirszj1GZ2VdkfIYyG3XpExl0WMgIxo0Hr/fq/?= =?us-ascii?Q?N9AIwMMVA+XKXTHs2WTt38VktMp7H+ZmsbAYbq05BfZmzlK72JGpwM3mEXKq?= =?us-ascii?Q?BSS3fLTDwqeGmEy2RKlxkfPFm7KnBRDe5paBcW8MD356K0FpNFJMtJsnrBNo?= =?us-ascii?Q?ZG7GxNEhwiy3QLWszZnm2QpB9JB91kw3d6g/hwCHJfMBX5DIzI6QIloR1kxA?= =?us-ascii?Q?jRTsvDy+624YPIhxXN2R/tppwGduoKeTqaaVItC2vcxw3pSAr5t2BZfMlgwi?= =?us-ascii?Q?G3vZfZY6kAmwNu/JRN7dt7jccUXU4xMAtkHQcQQAGdcPsLwvETEpN3BkLoKE?= =?us-ascii?Q?NeuagXwa0mt+hAORLgUtk57aOWJbJi2iGcgMD7Im8vaG4nFmqk6+inN7mOc4?= =?us-ascii?Q?WZCkG2Cxlq4bdL+4xhaw4Hz4vRicQvFo+tIJ1u0T9PdNXLyKQ6UISVyCmX5m?= =?us-ascii?Q?Y084H9P/DahDaX76DEZ0ODU9FcCB2+/n92s+MuM42qKr4e6paxZYCElsKz1n?= =?us-ascii?Q?VH3CL9nDHEvSNd4aFC8OwjpwvnkksaObkqQ9rrAIFhMgC5/YNYZyg3NqWZkH?= =?us-ascii?Q?/j3G0ZJMR9kaxpSvy2Ym3p88pwpaOGgzTAkyVaxjpHfspKmEwJYyFMPyWK99?= =?us-ascii?Q?UuYzAZYRBYQa7Hi4VgyKxpT4x8+aECEEzMBdXSwNasZmuCV1vl1DqQqhWXA9?= =?us-ascii?Q?RPFBGXxGPPoFyf8bX4XZSjwwUPd314QnGGTZLNPGbvow+C40ThPw1NuGwS0Q?= =?us-ascii?Q?z2HRbvsEDQ=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8d2a25eb-2f74-4801-10f9-08de84781709 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:05.2438 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: oY+YW/mig5/Qv5RM+vVIIfHsivxL4YZGoUJcZqkah1cZp0Fq6XRFjumrJLnDfGFLXswJbO1HCFlDmYvGg3xtEQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Replace the hardcoded 47-bit DMA mask with per-architecture values. Hopper and Blackwell support 52-bit DMA addresses, while Turing, Ampere, and Ada use 47-bit. Add Architecture::dma_mask() as a const method with an exhaustive match, so new architectures get a compile-time reminder to specify their DMA mask width. Move Spec creation into probe() so the architecture is known before setting the DMA mask, and pass the Spec into Gpu::new(). Cc: Danilo Krummrich Cc: Gary Guo Signed-off-by: John Hubbard --- drivers/gpu/nova-core/driver.rs | 28 +++++++-------- drivers/gpu/nova-core/gpu.rs | 60 +++++++++++++++++++-------------- 2 files changed, 47 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 84b0e1703150..41227d29934e 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -5,7 +5,6 @@ device::Core, devres::Devres, dma::Device, - dma::DmaMask, pci, pci::{ Class, @@ -23,7 +22,10 @@ }, }; =20 -use crate::gpu::Gpu; +use crate::gpu::{ + Gpu, + Spec, // +}; =20 /// Counter for generating unique auxiliary device IDs. static AUXILIARY_ID_COUNTER: Atomic =3D Atomic::new(0); @@ -38,14 +40,6 @@ pub(crate) struct NovaCore { =20 const BAR0_SIZE: usize =3D SZ_16M; =20 -// For now we only support Ampere which can use up to 47-bit DMA addresses. -// -// TODO: Add an abstraction for this to support newer GPUs which may suppo= rt -// larger DMA addresses. Limiting these GPUs to smaller address widths won= 't -// have any adverse affects, unless installed on systems which require lar= ger -// DMA addresses. These systems should be quite rare. -const GPU_DMA_BITS: u32 =3D 47; - pub(crate) type Bar0 =3D pci::Bar; =20 kernel::pci_device_table!( @@ -84,18 +78,20 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInfo= ) -> impl PinInit())? }; - let bar =3D Arc::pin_init( pdev.iomap_region_sized::(0, c"nova-core/bar0"), GFP_KERNEL, )?; + let spec =3D Spec::new(pdev.as_ref(), bar.access(pdev.as_ref()= )?)?; + dev_info!(pdev, "NVIDIA ({})\n", spec); + + // SAFETY: No concurrent DMA allocations or mappings can be ma= de because + // the device is still being probed and therefore isn't being = used by + // other threads of execution. + unsafe { pdev.dma_set_mask_and_coherent(spec.chipset().arch().= dma_mask())? }; =20 Ok(try_pin_init!(Self { - gpu <- Gpu::new(pdev, bar.clone(), bar.access(pdev.as_ref(= ))?), + gpu <- Gpu::new(pdev, bar.clone(), bar.access(pdev.as_ref(= ))?, spec), _reg <- auxiliary::Registration::new( pdev.as_ref(), c"nova-drm", diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 8f317d213908..9e140463603b 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -3,6 +3,7 @@ use kernel::{ device, devres::Devres, + dma::DmaMask, fmt, pci, prelude::*, @@ -162,6 +163,19 @@ pub(crate) enum Architecture { Blackwell =3D 0x1b, } =20 +impl Architecture { + /// Returns the DMA mask supported by this architecture. + /// + /// Hopper and Blackwell support 52-bit DMA addresses, while earlier + /// architectures (Turing, Ampere, Ada) support 47-bit. + pub(crate) const fn dma_mask(&self) -> DmaMask { + match self { + Self::Turing | Self::Ampere | Self::Ada =3D> DmaMask::new::<47= >(), + Self::Hopper | Self::Blackwell =3D> DmaMask::new::<52>(), + } + } +} + impl TryFrom for Architecture { type Error =3D Error; =20 @@ -211,7 +225,7 @@ pub(crate) struct Spec { } =20 impl Spec { - fn new(dev: &device::Device, bar: &Bar0) -> Result { + pub(crate) fn new(dev: &device::Device, bar: &Bar0) -> Result { // Some brief notes about boot0 and boot42, in chronological order: // // NV04 through NV50: @@ -292,38 +306,34 @@ pub(crate) fn new<'a>( pdev: &'a pci::Device, devres_bar: Arc>, bar: &'a Bar0, + spec: Spec, ) -> impl PinInit + 'a { - pin_init::pin_init_scope(move || { - let spec =3D Spec::new(pdev.as_ref(), bar)?; - dev_info!(pdev, "NVIDIA ({})\n", spec); - - let chipset =3D spec.chipset(); + let chipset =3D spec.chipset(); =20 - Ok(try_pin_init!(Self { - // We must wait for GFW_BOOT completion before doing any s= ignificant setup - // on the GPU. - _: { - gfw::wait_gfw_boot_completion(bar) - .inspect_err(|_| dev_err!(pdev, "GFW boot did not = complete\n"))?; - }, + try_pin_init!(Self { + // We must wait for GFW_BOOT completion before doing any signi= ficant setup + // on the GPU. + _: { + gfw::wait_gfw_boot_completion(bar) + .inspect_err(|_| dev_err!(pdev, "GFW boot did not comp= lete\n"))?; + }, =20 - sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar, ch= ipset)?, + sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar, chipse= t)?, =20 - gsp_falcon: Falcon::new( - pdev.as_ref(), - chipset, - ) - .inspect(|falcon| falcon.clear_swgen0_intr(bar))?, + gsp_falcon: Falcon::new( + pdev.as_ref(), + chipset, + ) + .inspect(|falcon| falcon.clear_swgen0_intr(bar))?, =20 - sec2_falcon: Falcon::new(pdev.as_ref(), chipset)?, + sec2_falcon: Falcon::new(pdev.as_ref(), chipset)?, =20 - gsp <- Gsp::new(pdev), + gsp <- Gsp::new(pdev), =20 - _: { gsp.boot(pdev, bar, chipset, gsp_falcon, sec2_falcon)= ? }, + _: { gsp.boot(pdev, bar, chipset, gsp_falcon, sec2_falcon)? }, =20 - bar: devres_bar, - spec, - })) + bar: devres_bar, + spec, }) } =20 --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012058.outbound.protection.outlook.com [52.101.43.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 183363F880D; Tue, 17 Mar 2026 22:54:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788063; cv=fail; b=jjS090u0uh8kDHTHPtOVS9ag4MjnLMjTHvLCDTr8Cms6C9ruAITQT0uL3zHSKsvRkZsasziQh497jjTBk7SaQx6u520O26ev/SGFt0voa+2sNyosA78I2STP+44zwzOTN1JqexbPcT8Y92Deon/wIBRydxjL2YfzH/3WDhlltZQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788063; c=relaxed/simple; bh=CoZMlWWGxUBFiBndeZB0uSMxCQtkcaoW9hF8YN/f0SE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=Kz2CZHZXXCppMeUVxgbmdIys4eT99yIMJ9x8ScTIa+bqxhH251RxPgxyfGw7unloVZS3aglnpCILJBxNd+ajd68SBJbHaMiCFLyWwz6/GTY7BfTF25nFDnSNNQ7jrYlpI/V1QRuqhPkY2biiPLTK8kGmoiB/fcdpBM//J07ZlMg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Fq0k17WI; arc=fail smtp.client-ip=52.101.43.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Fq0k17WI" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ddOLtOT1sU3W4TB11GdOuT0CO7n6635DIQXajjArt2jF1Vg6q4SWe6zr/SNdbBMsIjZCmWOGqBh/4UVaMpUZ4U/8Ehgz/99VWP+2y+cr2exf0dSh+G3Xl6K7dW/J0SYX2SbRa2sDPPUByaaEZXXlvtM850RuOn0ia9fmM6J3xAGO7yURbWwPs0pJX4bQw8/UkxvL10GwQxopwdmSlSg4t9/jQX2dNiouyJnAn2+Wq0Wl1RlQHnSzHqzg3S2e+7J3+WS28dQkDbBQAxycEjEZ9vUHog2vIkGBqiOkT87zq9T1O0CgOboCmGgIYodPdc/AqXYZQMLebB4vZp7Sk3RkzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qgG/OtMe6MHK45OQfykbm5eYd/0iMW9zxrMDcNg2Hz0=; b=h5eaFCbmXSie/jkbaXsPg7hponVRcMmdK1s+nzcZgwO21VAx1bZvGbzBTkGnEYbR+mrGOm9aOb793LaPTxnImIMu8YOYOeljuiFTAOJuYjBWHEu96vH8ZJiDistWdJD85zRPKbqrg25Q8Z8LqCv+JVNIrE6i2NPWqqwA9GvBYD0/Ls3lD5ZpRGr5Lt5E4XamqTxcPJ3kDOTyIfOI+3vtR7VK+MzH77AOLNpnLWKET8JY+5nziQAMuD560B7Kr9XhTxrnxFsraDqbdFFH7x2Wn8rJeg6I+Jn4pYvg3vSN9fgGyWSP78pUO7O0RVFgckZKvm50+Vi1OvtFiZAJPlO6fw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qgG/OtMe6MHK45OQfykbm5eYd/0iMW9zxrMDcNg2Hz0=; b=Fq0k17WIB8okVSAewdowlTjU90IAeY3ws9v7E3HBavGWJj6g638V1yr/feBHuZb4GJjCp3Ml48BYMcpm7dhxoWvZdFLodv0p7qphh3bQ7O4EQDICuQVRSr5x1tfl5MOu3IlAvqyMMvU8/P78foyevItsKLpOi+9Poc1D/blwY5cMMrRSHliBjaEtGfvYSecInp8k9gRPeJbuwOv8GhYQuhf+45JdfLPEV1khQ2thF4vMbGtd+6xfyYAkwmRTItdhwBmMxuRFYxpT7fHS0Eo3XAe+JnPlkHK/oevkBS0sWaVelhYzqHE6aK9CyPSl64SNxhyYgBcwkjNEcdR+SRGS2Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:06 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:06 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 06/31] gpu: nova-core: Hopper/Blackwell: skip GFW boot waiting Date: Tue, 17 Mar 2026 15:53:30 -0700 Message-ID: <20260317225355.549853-7-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR05CA0032.namprd05.prod.outlook.com (2603:10b6:a03:33f::7) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: d79b7aaf-0ca3-4c29-d242-08de847817b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|7053199007|56012099003; X-Microsoft-Antispam-Message-Info: YPidnYRV7/toa3cFR+NwBo046Gv6hztxqAg9rTcD5r8CJMlKDozHPTkurkdU0bnTkL05WfXUuIl007myAmbj8Tycn9mTYl2lvZiU1NNulBuLhZTSF+xPS8kgUMNL/P1Gl6dOLDRbUKZBlRik12IwLv++ypjvflTFNOfrqF0V8uE48fLaz+rcZE1OmwrCKR7OdrVH0tfFBA10VbKISFvyWmsrhxZFIaMuNee5W7p33yAXb2n/4V/Ts8emLPW9D2TrwuR6Y7No1tfQe7CuOxV8FoC6Uy5cN3l8+X4pewC3DCX+iUt1wNeBi3jDvRkkalOpajLbAPUmNln2PSKaGDDqBK8mGqVAU6M3UQKO+iWuzj/OlzUUdwh9PtcqWeMUJYZf9r8ASdv40/KTazycxU32RUvjl+K/IYcUwaUCRF2Yd/gLCVhbf7lZK+cPiHrmEulzKsjMnNSyEazXHdSDsfQnFz5CTyaEOMeFUQnW8nzgZiBu+oMfX1kPhsUxrscsJCNkRaIVP3+Czlqg0rWE6BB3EN6d+uTvrgXmxGa1xDGTX2IRW9ueW+sONigAwHXB7PllMuHZDcqFlXhPGEGgUgoCMm0+qFNPwaiUsSBSfGRIb+dazBE4qlWme6KyUfXz68EH2L4hQiHqw0NdNCHoBs9CriXByc/lNrekVq9G23Beba4whBFnfNsKxccb+/A/tCdYhNFeIPSSzwaZ4hKZzfU9FfSyPVGoiPdMRNtNHq3h9YY= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(7053199007)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?uNXHv2bco4Qo5Rk16Ge/KFSN72GFlzP7wRNahfCQiBgyPjU9g1GnU+ayRCrg?= =?us-ascii?Q?G3HJtPDpjUeflVSGZJ8R1jN7HIvqD9mPbZBZGYvzTcDzYeshGdq589IAYtJ+?= =?us-ascii?Q?fRWt4fsMTyiIzL+gOaSGHaEcwlO2+2veRJ/Uqfxny7g02siyXEZ0GxrXM9az?= =?us-ascii?Q?zNlMd5mG7KtZe7cYw5Tu1D6tJDJJXJMaeYEfHiYrpUUjXiPhf7EDKgSvuMrS?= =?us-ascii?Q?hHEMOcO86kS2Oyo1ayOLoj3iDyWvaShMGeQgwBJcL07sZx3rdGQAcjZyVx4F?= =?us-ascii?Q?rltxueEvzonlzB+W/xfbAZSwMBu2g2SNrDY023IQ30XfFnMSYrgSsInsZn6R?= =?us-ascii?Q?puoeMXoSbfDlXshiDNZqwa76sAvbtquEeeK8SM3Ad0r8cdMahAzimTcDvfbE?= =?us-ascii?Q?gGLQkyeWe8N2huJ9rdADcmWnCO4A9tqy7a9xg54aX+zC6xyOQpdn9Oc5j6de?= =?us-ascii?Q?m9kuZZ6/z+ok23SefmtS0sxm/+fRbdS5m4MCGKYKh2FW88tqzdefnXJBgfgx?= =?us-ascii?Q?17F0BGSlpba+OwRqbM9CCLen1SxZzNliAGEFTyLVtuorZMTx13jddHUXjXt+?= =?us-ascii?Q?Z0MNRx3gQ8wtHYIlw/nA8Tq3qGnG+5HBMsGa3gGfeblSpOVKdmqmSNJFs0bz?= =?us-ascii?Q?gjFY15wwMV6hJbRjT3aWZoTMMeuLjNAHAPK29eZGM6fEtZbOlHWPDo78ZWjE?= =?us-ascii?Q?Ip3RWpvY6jD1S8H/WW3NXfIzy8dZcCsEcTka6zdRYFFFaeje+zv4Kvc6bIX1?= =?us-ascii?Q?369V8J2a4A11lsySu2c9bf+684LPnaua7e4bII4Jpd3HTy3LUUGz1aSbHaKT?= =?us-ascii?Q?2j970NcxIjxX4qlzq1nXden4ZRWf7XzduXl25aj1AdyNxB2lFjlXVy/hg4XA?= =?us-ascii?Q?33v8NkQMYvY7IpviPBoD3/Mhqy8aT/PhyztbTDVhR+mfEPRf+4BOuuNKMhlJ?= =?us-ascii?Q?sH1REFPmV6a9hEsSIA1AfPQvGFthPWMDvS3iplmfUPQAkXvyGn7vltuQ1IfA?= =?us-ascii?Q?BFncT4uAayv1k4+EW7vq/GGoy4ztlKG6XVm335kJIChLwPjFMSU1jNciv2kz?= =?us-ascii?Q?d8bfh7PdERWmGffBLDd9Vk5sSS6HGlF6Bg+7GX/b6y02TSCkldcZAz9Ss3g1?= =?us-ascii?Q?58VhY3zXWP5c+4ZuwfOPIgrb1UP8Yr2DBcKxsUTBzILBh1yCyy8Zk5rT30uL?= =?us-ascii?Q?hRauRzpfUG9HzUtzihyodv0OOXe/GeeZMU4jP6VTRK9icOvjyqqQ469ByoxF?= =?us-ascii?Q?mL0y5aN5RTl8RQZzutZWOj52ZUIQCz6oUJL9uNJKOq6KaPa+km9tbfQlSmKj?= =?us-ascii?Q?HQmdnqQaGqyvyfRz+bGNyygNwc/VG5ZbirfKABtNXK8UbWBRMrJEOc5km6cI?= =?us-ascii?Q?MclXrc8RV7DPrh26RpPMShcUlhzaHvaZJguoxD9Fb/4ORbRQVjfuBmJUWqMV?= =?us-ascii?Q?UNFaykZ+z/mgvX6kBhY5HRs9/kFuW3O46AUSaKevlhzYZLO0E+iM3+vVVwbE?= =?us-ascii?Q?nJlbcvL78Ycq/csb+wdp/N/QcYpXGiu7OAAA0Ra83Nad3/pN0e+UBELh+Bxs?= =?us-ascii?Q?MPt2iNtRtMH6aOTyQO2hcfH3hHPKgl5Z8IV2EDRPmM/GFLSGm6ARqjlwk35B?= =?us-ascii?Q?wh0rv9L9DXaCBDSvf5eXzsZDh7v2egIqpbJgfQqCQYcxm2hTipZd/tR++gyZ?= =?us-ascii?Q?Hs4XLiBExZqxwA0mxkI78+WSiHS1o32plxECLJgmXZ49Z10tAhqcIinbw5Kb?= =?us-ascii?Q?Yl6/3dL3Mg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: d79b7aaf-0ca3-4c29-d242-08de847817b6 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:06.3767 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Zukfquqp5HmTZO/lEDwkt6j2S5EOfisWCKDZd0C+bLXncq9wEO0QPeju+CibtLiV4jqUcnFrMJQt0rFuZzZvkw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Hopper and Blackwell GPUs use FSP-based secure boot and do not require waiting for GFW_BOOT completion. Skip this step for these architectures. Move the GFW_BOOT policy into a dedicated GPU HAL in gpu/hal.rs. This keeps the decision out of gpu.rs while avoiding unrelated subsystems such as fb. Pre-Hopper families still wait for GFW_BOOT completion, while Hopper and later use the FSP Chain of Trust boot path instead. Cc: Danilo Krummrich Signed-off-by: John Hubbard --- drivers/gpu/nova-core/gpu.rs | 14 ++++++--- drivers/gpu/nova-core/gpu/hal.rs | 54 ++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/nova-core/gpu/hal.rs diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 9e140463603b..93f861ba20f3 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -23,6 +23,8 @@ regs, }; =20 +mod hal; + macro_rules! define_chipset { ({ $($variant:ident =3D $value:expr),* $(,)* }) =3D> { @@ -309,13 +311,17 @@ pub(crate) fn new<'a>( spec: Spec, ) -> impl PinInit + 'a { let chipset =3D spec.chipset(); + let hal =3D hal::gpu_hal(chipset); =20 try_pin_init!(Self { - // We must wait for GFW_BOOT completion before doing any signi= ficant setup - // on the GPU. _: { - gfw::wait_gfw_boot_completion(bar) - .inspect_err(|_| dev_err!(pdev, "GFW boot did not comp= lete\n"))?; + // GFW_BOOT is the "GPU firmware boot complete" signal for= the + // legacy devinit/FWSEC path. Pre-Hopper GPUs must wait fo= r it + // before most GPU initialization. Hopper and later boot v= ia FSP. + if hal.needs_gfw_boot() { + gfw::wait_gfw_boot_completion(bar) + .inspect_err(|_| dev_err!(pdev, "GFW boot did not = complete\n"))?; + } }, =20 sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar, chipse= t)?, diff --git a/drivers/gpu/nova-core/gpu/hal.rs b/drivers/gpu/nova-core/gpu/h= al.rs new file mode 100644 index 000000000000..859c5e5fa21f --- /dev/null +++ b/drivers/gpu/nova-core/gpu/hal.rs @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 + +use crate::gpu::{ + Architecture, + Chipset, // +}; + +pub(crate) trait GpuHal { + /// Returns whether this hardware family still requires waiting for GF= W_BOOT. + fn needs_gfw_boot(&self) -> bool; +} + +struct Tu102; +struct Ga100; +struct Ga102; +struct Fsp; + +impl GpuHal for Tu102 { + fn needs_gfw_boot(&self) -> bool { + true + } +} + +impl GpuHal for Ga100 { + fn needs_gfw_boot(&self) -> bool { + true + } +} + +impl GpuHal for Ga102 { + fn needs_gfw_boot(&self) -> bool { + true + } +} + +impl GpuHal for Fsp { + fn needs_gfw_boot(&self) -> bool { + false + } +} + +const TU102: Tu102 =3D Tu102; +const GA100: Ga100 =3D Ga100; +const GA102: Ga102 =3D Ga102; +const FSP: Fsp =3D Fsp; + +pub(super) fn gpu_hal(chipset: Chipset) -> &'static dyn GpuHal { + match chipset.arch() { + Architecture::Turing =3D> &TU102, + Architecture::Ampere if chipset =3D=3D Chipset::GA100 =3D> &GA100, + Architecture::Ampere | Architecture::Ada =3D> &GA102, + Architecture::Hopper | Architecture::Blackwell =3D> &FSP, + } +} --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011050.outbound.protection.outlook.com [40.107.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 416583F7897; Tue, 17 Mar 2026 22:54:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788063; cv=fail; b=uaRKvMarIF18qlvXGFINeqDtFYLv1XYpVu4iTZ6U6XvaaSQ4Gmoqc1YfibvLWEaqGlYIsldXYkEWIGMDmqEId8BaXpBbnNfo7Q3701I8swGzk0jwdBfpssISjROUQ7uJmRxDyEdAYMd4sDDiV1mLxNgF2q/TYGw7reCjszbWYLE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788063; c=relaxed/simple; bh=ZND9T1qy8PGDVKj0AUdnQVghUXeBCu2IaYStYDMrt4I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=OzqXur4fbmlU8NGny7WG5FapeyLhEwDVjNYlkM5Dhr9W+D2CuX7dRSnrBD6xAQS0qAY7lv/vmsvfzOvpZdsNjfuwXSE2BYvoUVcCPGCe970z33zT/8Oe+wfFaZkjA5KRLJBGVkgp4GBcukE32MtKwirnE9+il2MXxMD42GoRqvM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=qgsPPAeH; arc=fail smtp.client-ip=40.107.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="qgsPPAeH" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=cAi36eSjBgXNs5IIpi3g7UxxebqlrywKLBLJ+hmNpWRmXqg9OEoLkuZHjlWHPN0IQDHHt7H/NgSpqokfJCsXdCiFDI+9iWsYE0abQFUiKc0t2lnHU+GT8q85krXQmXFiTs7N59lK7/YUoMLzQex9oUZs6GcynSBr5bMDJvWkUtaZj69TGi6BCJMbOd2vg+yfE/qcHKWtm49LvokzmaKMr/BcBZwgk5SMEy71IRu5+ew0cZdYKH3aIdAH1zmJLyTd3UKiTxbGyRZiuVPrMuKojppwsdtpsLWt6tCIRppmdWjtsZk7Li7X/0B3/k8oidTBmQeJrDu2cCRxzi1AkBojag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6ZiO5O6MG5ofTZp9FR+rwIZtnrrXIRdY2DIwPxZ/QBo=; b=NiQhdkBdH9KWPw1P5HvQqFMit85wbJslNMJnN28BJSyhf50D9i/0bnwj5Av6mJewJxizYjf8u/npdujLTmKf2S+6gOnnX9a/KEtTNdG5ioTdkvvqE4rqVcH+5kqvkT6gV21RQa8Dp/Drqu0c6daaW+z23HwARfcftuTBmoRyKi7cGnLRHDkoqfQiGcM2Y2kxrFPslr9Qb0sKqn6vlvNELCe5Y6i7uya6qme8UAGl1QvMoRb9Itw+1+yWS3dEo2TnOhUVp1B6lvGOF1KmZo345Z1RdU9Ix2zmUM4+LaJIRFSheW/GWtxR3vdbT153K0FXY2Lle2hH4MlUEuvYk7Sc8g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6ZiO5O6MG5ofTZp9FR+rwIZtnrrXIRdY2DIwPxZ/QBo=; b=qgsPPAeHZZfPg2AdzSccwTW2269p+9kCTLJUQxXljb+LAOHkhDQlxPRJ2KNNNDtp9+hKvStyX3vMYF1emb7EJve9fqPknZaqLjSif1LoS8cDjzQyZwi1nlEpn4gVu0UXh69s1je3DTekBejp24uAppNDmJ5Gd7h0gCZjFJ63m8LIWExORr+PUB5CcrdGI/HOlJjGyYRDHsynHwk35RGkXKa5WGmQc32JxJvr1HutsoXOWDPrMU7zOK6lBWNxJqGqdyFQUjzYnRlhygAhFHCWQVcnhrltwPszia2XXNYPThbW6kKPbll9WXG0mn7Nb4dauz0NH2hP5iq2In4eMhT42A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:07 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:07 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 07/31] gpu: nova-core: move firmware image parsing code to firmware.rs Date: Tue, 17 Mar 2026 15:53:31 -0700 Message-ID: <20260317225355.549853-8-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR13CA0008.namprd13.prod.outlook.com (2603:10b6:a03:2c0::13) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 78ae53ba-e0f6-486b-5fe8-08de8478187e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: AzAp1+P8QC/klCg3TY9I10iF/a3fSedjKhzQpGu881PecmfnSZTNsrQlQ5UD5szCFX8f1VUd6fUqcIPphcOWoy/Z4aHZbj+fSFBVG0E+QMPF0PVOBaClR4rDOB9qS0/9hoxb9898LKh5YVCaP9jn4rMiF/Nqqdts95GHW9XPNI/EH6GBIFXmkIPoWpgwEGMikXoRj/apIDoqfiJrXDa514XrA1bqech8JXvnpwkcBwB8Sjinqv8UVmBKFFBEy6i9h0ePxjnKS7vqs4ieTMSYvCJlY9kCW87OgldM+JtztLMa1nX4XeBVbY0kCaUwVUQZgkkrIxKg36uYNaU3TrN7hadnUe5pkNUtDh8SFDiCsDiU+KR3Dmabaw6ty4SQ/zIz8GhCk3kB9/42NrjlY4Asq0rV4SbO6SY5gJOUP2GXXpnAZ69g+t1ueZZZIAiNx8c3/bDWq3pPm4DjEO52C0XjY9CapbTEq5QQzbNFTjFAQkDgrMLO/3qWDLj+Nk6SbktbnCdLg9xfArt/hYmtcv+le6nVLoiQjUMxi7yGUpzEfigYJcXDfs0b3ZFAY88vUS9oGTWVWqtQ1flI6buONPQcKdDJORA6lw4w3WQAIJkkn2R5Lq4gGgDvLoOaLed8NAGkwbxLJYJGI4p4l2NDbd34atzkqYAnEj2C1XD9TdTwCRHNZ/V9wHdkpB5fjhDFzsTb732Hv4zz4k6CUwzSQckM7OTomTm68ryG1I36mXlI3R0= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?nUPv8ZjfPVjSyA83bZSXJx20HlzArhTvP9h8NcOTe7UKqcl/fq5E/A9t32xm?= =?us-ascii?Q?sSbsaLGNfU+SxA+MPpkGn6i7/LDu174Yxaq72cdvjxyM8vb5gDMVK6zPxs6f?= =?us-ascii?Q?+4beVyr9QRr0FdBnu7Zo2zCeA0cJ08Cf/sWzmEDCUrunVFWCRpI5/+PQKUHI?= =?us-ascii?Q?4sKitLl7H0KyszEWvlKhG7Mbr10dFxSZZdfSCtDINDBJOD4NLPRBGr3AoGJT?= =?us-ascii?Q?lImLm5FqrWEHAKpmIvUK1bqGux1xwCxN8CE/NLNeGJtDF46R9SEpvzmc4iIa?= =?us-ascii?Q?GFpZvt5rZZGDihx1jOhSGk75PxLNukP12CO+bNGptBLetr1Y+a/PCVpm5EXo?= =?us-ascii?Q?zmAJJQbsDXv0bgGKYo0ACJLaf+4rQUayBMveUs9pEcdwAFvKOgaGNY+czT59?= =?us-ascii?Q?ofAtnTpYphWQy+hHzeQIx4BBi3gj1Jb9jtKrkhvCgJ/PqtC9dZVhxFjQ49yQ?= =?us-ascii?Q?EAfGCIAAEjseI+nZBhom3qEuw25h/4uV0q/cgOqTqdQE5DUwRWbVqEgk4hh+?= =?us-ascii?Q?wTEvP6s0sB/tdyYX4lL82Mm5H4C9S5UeUs+Si9s7fwzFL1jsmPrLHIKd90AW?= =?us-ascii?Q?16i90bdgJ+2GulOasmaauetrpLxIqx9qROda/ummltcKcpODHIDtuHqIOdWX?= =?us-ascii?Q?pVRBv0FQe4f3OcjQLpjGprnk92vnN+A1KXRM7Wxfwpb2yTC0mShlw93+5Xr4?= =?us-ascii?Q?Qdv+WnfxcH5t5aRNGIy+sN5YxJmDkkMxU5WK1y/HSXp4vPMnJEPfulm0JIXm?= =?us-ascii?Q?WBhzBPa0CHrDZpdwvKNv/ICo9YpOh8QbHs5OouOiM+TpkzEqT6I/wnKZismL?= =?us-ascii?Q?ZPNnUv1ko+zwIJbaMUlBy1NYFSm7UOG0rPKESScD/+/GUfeR1aUgj5b6f+1p?= =?us-ascii?Q?VtUEf+WtPD/Uc5g2elg9/MdscgFeCrbCjGXYjA+nuE4XQ5dL6ThuDLMsdN/L?= =?us-ascii?Q?rWbst7ojexuqClgOO/QYd45jTwnIBYtGezPbRd1jyC7jE48HUG4NsCCxqSNw?= =?us-ascii?Q?FD60o1TTq3FEKoNWlCUCoIed2cAJnA7ZapcQwF8M8Dz0mLTqjcmG7ZK27WGY?= =?us-ascii?Q?wfQ0TXM6Nx3JMoAC9XmC0D7XW6hWlXEV9E/xay3qvozb+icEwGzE0Kt7sfOd?= =?us-ascii?Q?yXIN5lVig2jX3UjENmtfAwmN5OBLRi4K7iTHY9n0j1Di9OyUQKwU7MkyQ5m8?= =?us-ascii?Q?c182TXkYdvseIgJlr9OdQm22oiQ9ucR26ga9J6Jy2m+rBolaf0X9UMtuX/nF?= =?us-ascii?Q?Npje8r/e3ruAPH5C1E54FGX1gLp9ZAQ2KaXSRR+vKLDbmztzgUDbwYJzU6k1?= =?us-ascii?Q?Fca0f5dTAtse4aUYbfkq842hCwfjYKSB4Kmca4oGx62JDwapgeg9KHHyeb73?= =?us-ascii?Q?ykaCUd9ryqtSeDfRG6zrSJDJve7RETrs9NIW7g0u35RO0TY9oHMuf4tPQq7W?= =?us-ascii?Q?MZt0wIYAVwUz64Nes13KrhtYoWeJp/cr+uWWohtvavvKeBPNUC/Lw6zx9VWh?= =?us-ascii?Q?3lJmj23Shfg0Do/CkjFniAmnw656q9wKU8k7pX1/ClZ54SucdAMVj9zor6I7?= =?us-ascii?Q?i4914BQ8rHJ+Bhxat1SI+llHsoDtrZS9KWUWFyC+wZco6BvTI2YTelu/C9jw?= =?us-ascii?Q?g79QviOAxEoidz/dNc9YXBM1RI7GwkD5eCyPfYFW6aeIqEydDDejHDJMTtMD?= =?us-ascii?Q?hn/x/C1lyro4Qhp7KN7kF12BKqWAn9doNloedv6/+reX2W5XXmCksHUXgruG?= =?us-ascii?Q?mb2LNPcxXw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 78ae53ba-e0f6-486b-5fe8-08de8478187e X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:07.6748 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MvJbokAt65zmTnJV2PeycY//0Volwgg7cbAHTFBWUr9liLTu7odKDZFfq+Rnqfk/N5Ds9kVeeTuz77fncPe3pA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Up until now, only the GSP required parsing of its firmware headers. However, upcoming support for Hopper/Blackwell+ adds another firmware image (FMC), along with another format (ELF32). Therefore, the current ELF64 section parsing support needs to be moved up a level, so that both of the above can use it. There are no functional changes. This is pure code movement. Reviewed-by: Gary Guo Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 88 +++++++++++++++++++++++++ drivers/gpu/nova-core/firmware/gsp.rs | 93 ++------------------------- 2 files changed, 94 insertions(+), 87 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 2bb20081befd..177b8ede151c 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -457,3 +457,91 @@ pub(crate) const fn create( this.0 } } + +/// Ad-hoc and temporary module to extract sections from ELF images. +/// +/// Some firmware images are currently packaged as ELF files, where sectio= ns names are used as keys +/// to specific and related bits of data. Future firmware versions are sch= eduled to move away from +/// that scheme before nova-core becomes stable, which means this module w= ill eventually be +/// removed. +mod elf { + use core::mem::size_of; + + use kernel::{ + bindings, + str::CStr, + transmute::FromBytes, // + }; + + /// Newtype to provide a [`FromBytes`] implementation. + #[repr(transparent)] + struct Elf64Hdr(bindings::elf64_hdr); + // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. + unsafe impl FromBytes for Elf64Hdr {} + + #[repr(transparent)] + struct Elf64SHdr(bindings::elf64_shdr); + // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. + unsafe impl FromBytes for Elf64SHdr {} + + /// Tries to extract section with name `name` from the ELF64 image `el= f`, and returns it. + pub(super) fn elf64_section<'a, 'b>(elf: &'a [u8], name: &'b str) -> O= ption<&'a [u8]> { + let hdr =3D &elf + .get(0..size_of::()) + .and_then(Elf64Hdr::from_bytes)? + .0; + + // Get all the section headers. + let mut shdr =3D { + let shdr_num =3D usize::from(hdr.e_shnum); + let shdr_start =3D usize::try_from(hdr.e_shoff).ok()?; + let shdr_end =3D shdr_num + .checked_mul(size_of::()) + .and_then(|v| v.checked_add(shdr_start))?; + + elf.get(shdr_start..shdr_end) + .map(|slice| slice.chunks_exact(size_of::()))? + }; + + // Get the strings table. + let strhdr =3D shdr + .clone() + .nth(usize::from(hdr.e_shstrndx)) + .and_then(Elf64SHdr::from_bytes)?; + + // Find the section which name matches `name` and return it. + shdr.find(|&sh| { + let Some(hdr) =3D Elf64SHdr::from_bytes(sh) else { + return false; + }; + + let Some(name_idx) =3D strhdr + .0 + .sh_offset + .checked_add(u64::from(hdr.0.sh_name)) + .and_then(|idx| usize::try_from(idx).ok()) + else { + return false; + }; + + // Get the start of the name. + elf.get(name_idx..) + .and_then(|nstr| CStr::from_bytes_until_nul(nstr).ok()) + // Convert into str. + .and_then(|c_str| c_str.to_str().ok()) + // Check that the name matches. + .map(|str| str =3D=3D name) + .unwrap_or(false) + }) + // Return the slice containing the section. + .and_then(|sh| { + let hdr =3D Elf64SHdr::from_bytes(sh)?; + let start =3D usize::try_from(hdr.0.sh_offset).ok()?; + let end =3D usize::try_from(hdr.0.sh_size) + .ok() + .and_then(|sh_size| start.checked_add(sh_size))?; + + elf.get(start..end) + }) + } +} diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/= firmware/gsp.rs index 8bbc3809c640..c6e71339b28e 100644 --- a/drivers/gpu/nova-core/firmware/gsp.rs +++ b/drivers/gpu/nova-core/firmware/gsp.rs @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 +use core::mem::size_of_val; + use kernel::{ device, dma::{ @@ -16,7 +18,10 @@ =20 use crate::{ dma::DmaObject, - firmware::riscv::RiscvFirmware, + firmware::{ + elf, + riscv::RiscvFirmware, // + }, gpu::{ Architecture, Chipset, // @@ -25,92 +30,6 @@ num::FromSafeCast, }; =20 -/// Ad-hoc and temporary module to extract sections from ELF images. -/// -/// Some firmware images are currently packaged as ELF files, where sectio= ns names are used as keys -/// to specific and related bits of data. Future firmware versions are sch= eduled to move away from -/// that scheme before nova-core becomes stable, which means this module w= ill eventually be -/// removed. -mod elf { - use kernel::{ - bindings, - prelude::*, - transmute::FromBytes, // - }; - - /// Newtype to provide a [`FromBytes`] implementation. - #[repr(transparent)] - struct Elf64Hdr(bindings::elf64_hdr); - // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. - unsafe impl FromBytes for Elf64Hdr {} - - #[repr(transparent)] - struct Elf64SHdr(bindings::elf64_shdr); - // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. - unsafe impl FromBytes for Elf64SHdr {} - - /// Tries to extract section with name `name` from the ELF64 image `el= f`, and returns it. - pub(super) fn elf64_section<'a, 'b>(elf: &'a [u8], name: &'b str) -> O= ption<&'a [u8]> { - let hdr =3D &elf - .get(0..size_of::()) - .and_then(Elf64Hdr::from_bytes)? - .0; - - // Get all the section headers. - let mut shdr =3D { - let shdr_num =3D usize::from(hdr.e_shnum); - let shdr_start =3D usize::try_from(hdr.e_shoff).ok()?; - let shdr_end =3D shdr_num - .checked_mul(size_of::()) - .and_then(|v| v.checked_add(shdr_start))?; - - elf.get(shdr_start..shdr_end) - .map(|slice| slice.chunks_exact(size_of::()))? - }; - - // Get the strings table. - let strhdr =3D shdr - .clone() - .nth(usize::from(hdr.e_shstrndx)) - .and_then(Elf64SHdr::from_bytes)?; - - // Find the section which name matches `name` and return it. - shdr.find(|&sh| { - let Some(hdr) =3D Elf64SHdr::from_bytes(sh) else { - return false; - }; - - let Some(name_idx) =3D strhdr - .0 - .sh_offset - .checked_add(u64::from(hdr.0.sh_name)) - .and_then(|idx| usize::try_from(idx).ok()) - else { - return false; - }; - - // Get the start of the name. - elf.get(name_idx..) - .and_then(|nstr| CStr::from_bytes_until_nul(nstr).ok()) - // Convert into str. - .and_then(|c_str| c_str.to_str().ok()) - // Check that the name matches. - .map(|str| str =3D=3D name) - .unwrap_or(false) - }) - // Return the slice containing the section. - .and_then(|sh| { - let hdr =3D Elf64SHdr::from_bytes(sh)?; - let start =3D usize::try_from(hdr.0.sh_offset).ok()?; - let end =3D usize::try_from(hdr.0.sh_size) - .ok() - .and_then(|sh_size| start.checked_add(sh_size))?; - - elf.get(start..end) - }) - } -} - /// GSP firmware with 3-level radix page tables for the GSP bootloader. /// /// The bootloader expects firmware to be mapped starting at address 0 in = GSP's virtual address --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011050.outbound.protection.outlook.com [40.107.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 923823F8DE7; Tue, 17 Mar 2026 22:54:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788062; cv=fail; b=GY/b9tUFH04kxZBSod0+MMC9/iv4NELXdMBQvmX6fXp/2iOiklwkecauWIgdIRFkLWgNhrnVw5dBgamMfRDUAsCUgg8Bbw/vQZEV2djcuKK/q0Gf/Jv8Jh3kt0zRWqIwup5nzuAEflZqGsw+QGviDaS6Kdq+iAJFaaK1t/Cu2eQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788062; c=relaxed/simple; bh=j9HYYPamnsBLHV+bWvvpjIygUSQvYGIR1xEZXRPIHug=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=mGurOuwPU3dL3iDPhQnz42Nqkb4frGDBj0MXp5WssWEz9N8aP+a7+2IoKn6un7DZzOVbtC0SkNTTvrAKAcCZ3BRFmFQBnnk5vp97W4hIHxO+kwv36N+YgsG3Ao4/LtkFaddwaw25SK23RkOfJI2gIhdibTq9x76Wh8zRFk255C4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=dhmBKqZ9; arc=fail smtp.client-ip=40.107.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="dhmBKqZ9" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=n9T7pIPSIvgYYpH+qcKFVVKcsRLUGSI0v7R0P6DKaJVW3gCUs2SeMYD2d+O9SkkggoEhHMnYa9vXENbbiDto3SYxqWzPrBSZTiuWOv84Nn0D8zxhWY8n+kGheHFLVs3SLxJ5yDKm7bbH5pSBMkkRYXOefPD1kaEf5ugh/ZGAJymbzMpOWWuBPoGCn026PJa/UAmTMv1KxE5Bhu8ePlN9+11tn7y8Wt3ALu4DR7fyskoL5zPmbU6h3oeBpPr8A6utcXNsokD8I6wtpxzHs8q4BrBoeiqz4OvhRR3NBXYGMUKp4gnqMrSZD81TASuy17aB6K6noLFYJJLgZYSF90QtRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JqzMViUbcH4b1K0VFivK4pFi1Acp6jmWlFgRt9vyxjU=; b=zO89AoHrFrGe2C2dP0KM4n457OewVXBWJqcs5k1X3fPXTTR4CA69cZ7miDlfvx94oQUsQTm+Ul4n8sdubV29XlkD0/07T4tBby+FnVqm+Tj/w7PegQxlHf4JrvTdog2/7rquzTsHWVEBV34VHW1gyAG4eyLMTT3hWOBV3QiyObAW+jEVVkvALZdZVDJseygXCclrEAk/nk7eavPTPw/BSk1FFCOen2bjE1CmoIhDBHcxHpLaQ9EK5yAT1l2hP0vuv7WAb73KtNtO4kL0g33HgTEPvBkSyHaA5SLln25c/lby6YBaDCDSQNz2TRgqaMgrIHtmQ6kokq54XM0fn7HXiQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JqzMViUbcH4b1K0VFivK4pFi1Acp6jmWlFgRt9vyxjU=; b=dhmBKqZ9KTy/XOhckG+AL4Vd+rhDOWx/0QWXhKRC8Jd87KdBP54KHvD/ZN2FCjnGP/Sp5m9nSspsH9a8PFiA0GQSWVsdZgeevC87teHf4P5ZveEJAwRdByx/Gv+WADDGaxuTn3++85BwftBW5vzwUQBGsE+T74cRKsvqJr3ZCILmNjwZXOMH5kjyszKWohqAsMIJ1KOuSaPJd43+KqvGdbKYvXe8qhNEIMplZ0VRddtPiOp6UsVwLBe0XZHSxlRRFWjt9dzKmlpGsVOO5AwPIXbhDbSCaUX6MmHpgkEEE+agc3bSZ1U0a3xoTE7HSdUHljfNRwJh/ocgFuK7DY+5Yw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:09 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:08 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 08/31] gpu: nova-core: factor out an elf_str() function Date: Tue, 17 Mar 2026 15:53:32 -0700 Message-ID: <20260317225355.549853-9-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0223.namprd03.prod.outlook.com (2603:10b6:a03:39f::18) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 77e2c9f9-6005-4285-c098-08de84781930 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: P79pzJdutK/G/vUyOGUP696aLto7yOqagMtuBE0mV/WxiK+uNx4THsUMrEsz5Z4hSATMC14lWMmz7itLGjMPzVteyu99s32ZxMofMjRsy6zaTxkZfKlcJq70uwpTWsbp2vfar3eSpu0/bjT5j01M3n26STXydoA+YhjPfJ9IxDHmhXwpS2VuaxEb9PabSxe1iiSD3oA26wgh0XGWiotD/e/gDzBEcO54XFM/eNM0XoT0LHtDPUSy6GMCRt8omj2Crg/Fucj0gAI3sOwolLdn7hqBoBIY/2OCOdNQ3pWlAiDMCN7F4iEg8Odmozi2TSulTjtel0/ZEBJVXnKc3Jz5fku11WvgbOLxiJNVs2W3vHSqZ9h2nIyL8L2oEA3HJCUBrl1XnQO5xq/APX2NFO4ew6nPTeXQiiKQKs1VuPgllOI0gxRHKL30FTkERKHJu0shEupnEJxu28sB46TRCe9gWjfv3sOxgPqKm8OQ56hgqmLSEY+j0W5FKbM9aMWlItrTng1eL6PY/gvOdgUtWywkhKPPsXjyESfxmhGZ6Bcb2at0Ir2dUmoM3UgovHEzxixdGlB0ZFUAoU5JYKkSvzzmvqc5BaNgUB+YThi+XiBsudv91OEDmmUPGSgj5dDGrjH8cuiNN+e6pFAZxqFNqGTYWAHYltGm9HgaX/CmZFDY5eZy6bVhi8Dr5IQgXMNc8Zv5J3P97iWsbzjYaCKYmq7qneEq3HMCvAoAX+Zww/pcSLU= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?J4rv40LWS9lhIqVJakTlNw27AW1ZXjP/LH5oxdMrrageB7uh34k3T7RVYnNU?= =?us-ascii?Q?hjUpLc+6iBvBOYnR60FRGgRL77vF/Y1RfuFAkVeI5qM8h8wV4URwxmPA/sdb?= =?us-ascii?Q?/1Dy5x5olG9tPLJcCEDBqgjl+yanjhj7eVO1rP/I9/ptwvji9wYt39uotAM1?= =?us-ascii?Q?Qivsd6p7s7knz11iwrAxJkTBovBNOfVJOsluzzOhmsEBY64+w8qmGpc+EcKD?= =?us-ascii?Q?IOSaeQJk4/NX3HjLBBDvtUbhIw/xJRftCB3WUp3e9PrhTn/T1eENP2249Out?= =?us-ascii?Q?pamvaGRlg2tbSN/Lgf15REUsPXlelnP2HTS1h0P6E2nkkebKaivgbgZdgH9E?= =?us-ascii?Q?c2+ImkNzcRyssOlxIRo8cMm7zG0yg5B8zE9Nr6MHA4G9hHoOt++v9RmV7iaz?= =?us-ascii?Q?lo2x+xRVkRaFcBEVUuYpbm3YVz0AYiAsd1rTiafFL44dued59Cwae7Gy2tmk?= =?us-ascii?Q?ncZCf9JSpAbVnuB1/ezXmiNHVObWF3pNW+23S/kB/h18HVzWvM5N5b81Fu7+?= =?us-ascii?Q?hqMZsgwFtGpIWyCWj7if5Ic4x4KnnVlxa4Sm7Kfzked9b7nr/ebvT/kLYL4y?= =?us-ascii?Q?SPARMtNG/VOO9SMxjYvicPKHrlW6u1PhDepaQ7i1r0yyi9R2c+pgC6xSOJWe?= =?us-ascii?Q?UVI641/hRjruOujegoXMEWIAmqAKngVtMb3fyFVpeWSvwGKaSfCOLPBUWq8Q?= =?us-ascii?Q?alGGnAhaiOortep536p3dAeAafaLjr6foH+zaxLtfQyZgfj0z0WwK3/jlCYX?= =?us-ascii?Q?3WSYrIb67IVuDi8irZuJbByBRaYuyG/HEjJmXwkYaWkQgFSEVap3NmbUEUP+?= =?us-ascii?Q?DxJB3ipWq+OdiAX13BiaIpQLR2N7KbvIRV5qBHI0u0qrFQYbejqthYOgZc3v?= =?us-ascii?Q?vdlb4OHqq6b7IhQBi7hm695QS25LFPwE4rBP8JEzyaQB1gzf3AbHBz2GpTW7?= =?us-ascii?Q?X26VJ3WN6z0ZKY6XxG5OLii4/5YSTZebZVKdmMC6WILznzRvaQhTG9b4Kxty?= =?us-ascii?Q?IQpgUrVCYnFjGMx9e4HHAh539Vs0uJuTYT99IFw3Bst7r3zVC70jtOEZvKJj?= =?us-ascii?Q?zAk6XY/EvUoG4+rnufI3PUNVPh7/BI4as0UJOIEOnJcm004qucByRpuiOJfh?= =?us-ascii?Q?+JaY4f5Fqk6CZSHB1rZItQQHV8zqq8s65n3Ww0XWS2H0mAeqxr9JQ/sPe75r?= =?us-ascii?Q?haM2uUD1zKu3DEjI/akhd5CsBx3J+d864UXp0gFPHb71j+xWujBxjr0L/1bd?= =?us-ascii?Q?/SA/6QLVlQwBnaaK9HyWlhzB+/eQBUtxj69zFdUfCI1blWBmK8L1qAkLw1n9?= =?us-ascii?Q?YuWKj0BS0DgE5YRKuNhiWV+pU90EoFj7pofC9dnreQBNx7We9c8YROLds80O?= =?us-ascii?Q?zsJanmosIlk6p4PKKwWh6OutJ6/3e/eliVMJJ18CfPDcDG3YSwddt9pPV2D0?= =?us-ascii?Q?jiM3kMS07OWMZXbyQAtj2CAP7pisnqg4AC2xyTH8Iuggnd2Odzxbn186oG1e?= =?us-ascii?Q?56xltECc/NikHiKQp0d71hIb6h7tBwcXkioOCg1wmMbaR9qeGrI7aj/1I8DT?= =?us-ascii?Q?JWXeFA5M2UugjUUSHBoQGxSaGH4dOdaNL7PQh2uRKnG5RxZkNqF1BvGjm2GU?= =?us-ascii?Q?JDYW2Pm1puta1CF/wst+PZfWGHN5R7WpD5U+JnlSa3NeHa5rHarh6RyaRVh1?= =?us-ascii?Q?yV8hF90sokYv3+XjXJqB5uM4I4A5WXrAUnT5spG7Bn9M0U/M6SPo03nM5tjc?= =?us-ascii?Q?8vW2IqJ3yA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 77e2c9f9-6005-4285-c098-08de84781930 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:08.8341 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VUrBB8QeLznF0xmpDmmZryq9rNj3111YHNR0/t+BadCSnMRCPi0cLFnrwbU4Qb3OrCKFaPMFK7x12qY6E6Z98A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Factor out a chunk of complexity into a new subroutine. This is an incremental step in adding ELF32 support to the existing ELF64 section support, for handling GPU firmware. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 40 ++++++++++++------------------- 1 file changed, 15 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 177b8ede151c..6c2ab69cb605 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -484,6 +484,13 @@ unsafe impl FromBytes for Elf64Hdr {} // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. unsafe impl FromBytes for Elf64SHdr {} =20 + /// Returns a NULL-terminated string from the ELF image at `offset`. + fn elf_str(elf: &[u8], offset: u64) -> Option<&str> { + let idx =3D usize::try_from(offset).ok()?; + let bytes =3D elf.get(idx..)?; + CStr::from_bytes_until_nul(bytes).ok()?.to_str().ok() + } + /// Tries to extract section with name `name` from the ELF64 image `el= f`, and returns it. pub(super) fn elf64_section<'a, 'b>(elf: &'a [u8], name: &'b str) -> O= ption<&'a [u8]> { let hdr =3D &elf @@ -510,32 +517,15 @@ pub(super) fn elf64_section<'a, 'b>(elf: &'a [u8], na= me: &'b str) -> Option<&'a .and_then(Elf64SHdr::from_bytes)?; =20 // Find the section which name matches `name` and return it. - shdr.find(|&sh| { - let Some(hdr) =3D Elf64SHdr::from_bytes(sh) else { - return false; - }; - - let Some(name_idx) =3D strhdr - .0 - .sh_offset - .checked_add(u64::from(hdr.0.sh_name)) - .and_then(|idx| usize::try_from(idx).ok()) - else { - return false; - }; - - // Get the start of the name. - elf.get(name_idx..) - .and_then(|nstr| CStr::from_bytes_until_nul(nstr).ok()) - // Convert into str. - .and_then(|c_str| c_str.to_str().ok()) - // Check that the name matches. - .map(|str| str =3D=3D name) - .unwrap_or(false) - }) - // Return the slice containing the section. - .and_then(|sh| { + shdr.find_map(|sh| { let hdr =3D Elf64SHdr::from_bytes(sh)?; + let name_offset =3D strhdr.0.sh_offset.checked_add(u64::from(h= dr.0.sh_name))?; + let section_name =3D elf_str(elf, name_offset)?; + + if section_name !=3D name { + return None; + } + let start =3D usize::try_from(hdr.0.sh_offset).ok()?; let end =3D usize::try_from(hdr.0.sh_size) .ok() --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012058.outbound.protection.outlook.com [52.101.43.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7A813F99C2; Tue, 17 Mar 2026 22:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788065; cv=fail; b=KO3gBg/I3O3Qi+Fy5N7T0vVzB8IZ4/9qszSTziV5O4YZqazlwSgtxi1CxrBAd8DPlEVqTfAX+reZbONMbmpp8KQZOoN7/+voob0eJeNTuZUbh4B7/V1lS48nE8fPSOBGmzBP3tb1+jvxE7TkMNBxWzzODVUX8kFHVLMPVoWzKkc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788065; c=relaxed/simple; bh=ngDJisWsseC9Dl4NS0VFZxUdyDU57OOiO1kmaTNruXk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=Yw4lA2qi38Amp9fM6pbMcABIevIVjfsOHTTDNj50QOQ7KJRm8ZCTWY/61XmExtO7sgkXbDtx6WbtCm+Y68Of6jZG5T5ywJFbPIhjldbxW4Jh6+zVd1IjY99DiJk31GEcmplMUrs+38MEW0zpOBD9TQBBmko1WQiIxl9OFgapzWo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=bC5iG71H; arc=fail smtp.client-ip=52.101.43.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="bC5iG71H" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ScIhMTL/pvXdNH0Kfs54RHxF33pjCTvCylQAzGKUsJbF0DwAC8yPxtI0lYuLGYSe0HmiUd4jwPtiz54BURUH1dlBJwq9uTXDbpX+K5ymsTW8XNZfDOQwKQRKsJ21R2FECXPNM+w6/Ithd8SAz+QLPIDgkPnF1sgpdodvpI0HMs5cKpDf1cVO2ND9G54+Po8V6Ufw3Zb0oXGfH/HJ0mfCndN3KEtYglfz9Ansm2WnOySyjbNTeNbBiEf6I7N6mwcedm1Ox1Iea6jWiAT4ntWXxJfOjz9Xw2d/4Xu3DzhKGKNQWVdf7rdhq5TvNmdmHAz+m6OZDFK9ZYmcfWcBBp7Ykw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=c7CYDng2/Jezmz4Ey26Fu4WS1kpmee3dqLivU4b+93M=; b=FEyNe7w1Voili2VsVLD5i6xO6yBYTbboxw0NsIVVoJJZ1cMWBVvg/+uYv2nHUZkb9WK8GxJRM2s00YYhwdEj+sVw8Cf9qh93jJ+CU0YJSiBxlHYG/FuUHwjNk31EroRXSmiRqOhZufRULsG5fcCcoMBVRynUBIxslR2KXNorFO0HKIcIu1JLWeaPMJ/s3xj4GWRvgXGMpckv9P98QRuQOo+C6zL7opu0rpHcfsfR0ZuW4xdkkKQMsfZI9SBsL0XjKV2AyYYLE4XBYed3Fee4qnt9oSfVKWkz9rJGvBS7sL8l17WG7wXm0f8AfS9O1eb5l/CdrGZVKkz+zpNLcVw4DQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=c7CYDng2/Jezmz4Ey26Fu4WS1kpmee3dqLivU4b+93M=; b=bC5iG71HrFx4DNsZXQ1huTxu91Xj4th2oejr7StB5naJXwoHsYVcxR1ffIngNn+ju0g3E6OlcRU/XgkllF2ysZfeytA4M3ybF2cbmah+ItlzFWMR20eIjkoH2J4TWJ9UDtbFZxiAKCdEkVDompCX39scjzaObum+/LqmdUMY/78vTEYz7wMsjheDQCjgq9nHXq8ega+pp8cFhITdp7DQ4LvTqKOFbxO/Nl56DKuD2+L7vsA+X2B+HiyqHIsTTlIycj5c3RZQub4gJn2qsebdd6OZtPQsgxDchQUAiPHaMueXP3dSQNpbvni7VxsaxicH+d+Qbck5HBCyAFR+4yxTGQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:10 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:10 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 09/31] gpu: nova-core: don't assume 64-bit firmware images Date: Tue, 17 Mar 2026 15:53:33 -0700 Message-ID: <20260317225355.549853-10-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR05CA0057.namprd05.prod.outlook.com (2603:10b6:a03:33f::32) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: ddff0044-2bb4-43db-db54-08de847819ff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: XpGigjrIvehTK0mTSv123eNJZtGLoIVYbJzXKzrSlX2egLhcmJaTWjbgGs8oUdwe9hS6/nCDMxafDJ4HKMUQmEsCDCcYuIN6FemjQF0SnYKa+2SyXpqtTsdkVz05GVTOYSab1cTLOGyy/Vv0NWn2MxvTyyPqQgfL5cMSBWe9+pB7sKgoe7eZ//mARBLSLFMlqya5t0R2qcfnpyMdzbVllNopX7tZtccH14ige1458A9ngK/roFNSBxC/2Sg06WYIWcq6oa4VcxelYxFCMaYKkm1xDYsQsF0J3pasb46zIWTvefwuSC9RGJLoSrBmF218l27S4lI7f+sYQNfkjSrL7OjkHo+3wKHKpeID9mm/JTuPGe+d7mfbyOtRBLjsmgrbcfT0h2xgy8AZzULwajBU4lnQEqCi4a0FqJnwciVcKE0H+iudKr+oRhEAr1pZJosYkp5a1Zb/nSXVF2AjzC8tcDNpMCHkthAaYmIOBixJ3v5wA228KWliZ2B8J/8N0oo0nI/yC5//MuYEV2P3HrDB2F3Hv1tzUxYia9EtRLAv3444AkAJ8Auc8eiuzn8RkzC60cdRzsQ+78Iccse7YuZw+9YkC4tr8jtCSXZaY6mVUo+/aR8KE+vkr+mEeVi7H68mpJ+bBAL+huiWT1r820xoT+slQiAsarc3Vy00IdsGUA9n/I2wsJfnBOdEJa97d5/RFqHVJ1ERqR2IsAchFmrdoTPRwNKcwQ1QN0tdpqUdQw4= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?0vsuyJ5s6XTs4tzMU7vr8shUc3jTcUr0cUD9MWqqdrcw4VAvg62zNNVZr5f4?= =?us-ascii?Q?ovmCkX09y9+4Gbrauz0a/mSKz4G5DoZmEKB6X62oXgOQmcvH6R1SkRcVHb9o?= =?us-ascii?Q?SqN5dyUg9AafZXVknOu87GwQbiw9A4GCXIXWcbP7ZkBaXxZwFib0l8zLTS2Z?= =?us-ascii?Q?u7vChbBrvqOaJXBt5a4oIZXOaX1lt/3eZVwrH2bNYrek/XXwnlPyvzQedFlw?= =?us-ascii?Q?4JQQznntnBjH/iaSl4dg6DXCcVzo/GzbmBxVsh51tkhPV1T+hNIrlzR/tN+N?= =?us-ascii?Q?cfx7EWABKe5SoSX6HeKmKvLl2sJ6faSG/AI4PMhQVcPNIeJpX2EA/6nL7M4n?= =?us-ascii?Q?GUaZoVb5ugLSvddIKKBoawFkVGUDohIevc+PzhsocjOFm9+feLYIIcUoCuCC?= =?us-ascii?Q?6vn488vGSOuyEpJJeGu+O1yvHqVSdy410C7wgrboHbmD1Z8ltCogt31xCIlh?= =?us-ascii?Q?y8ujDwnzbRifp7uXjdha8UoMnbhLkRdUx909sZGlXlHrDk1drpvLvRgeHAxt?= =?us-ascii?Q?E6f15oqSgki8Z7PZxCf8uhFQSlSHu2EdNek1xp/RfDxH6kGn1bSxPPQfQ44+?= =?us-ascii?Q?U/3y6kQf7GVtrxzB8qbZoT1fum3d5PgOVYtW8zkY1nK2zyfaqT02QO1jNHlA?= =?us-ascii?Q?bdEHOW8HlrbVEx99YRD4vQNsCV+HR6iz1ncnHidmjizGQsW4+Gg7YpXxh1hI?= =?us-ascii?Q?eFwmnsrt8INI4yde6FU1kf0+YQgUveXhkz3PT0XfbvSfGIWBow9gu9qpZYh2?= =?us-ascii?Q?FOleAc2lX1Bgqy3jOBqzN0cA1EI7QKvknS2Y0uxxiqJbtDTiA3ZFmF0N4OJd?= =?us-ascii?Q?jSFPrrD9TupMAiLlex4v0QljRoRqJtudfZA8LRXQ9BkOIyQqBX6I1OBtf1Af?= =?us-ascii?Q?jgYFVX/yDWRVQ0Rfw7OFICd38GkWWMRjBb5yPoQgIYMdmdnl3Hc+QQ2s0l/t?= =?us-ascii?Q?uPTTa6IBhMtoCcMebUSnvveqbqy1fI+NAn/L2Bv3kGGAhIvDWMCuXdH2ApBU?= =?us-ascii?Q?lFQrzglz279BGX+OmucsDK77mMI09aqgEk2cinJlRUOEptGoMvigDDZe2C5p?= =?us-ascii?Q?gd3aQzyaKMugFso2ph5pNUBwIKNFFm2wl3/8slKTr6BNGFg1W/OO36W6bBEQ?= =?us-ascii?Q?A/9yA13Ij0mJPf8q70QZe0UmpaPIQFl4IcA3pOPRqLqIEMCtW/3x3YFbpk1W?= =?us-ascii?Q?vqUNe21MxWD+7TFKMie4/Hd/AW3R/RtxpURDJsIabFa8ls7gOA4wN72V6WSJ?= =?us-ascii?Q?mVZuPDWYjlm5f82djoFjiShMcH3OQhPUBL+ECDHMk3RINCzX2/jmhP/wu/n0?= =?us-ascii?Q?GdxpqTPMV4OnJ2wzu4eq61QTk8+m7BiO16oX7aO9QAcjSXiqHvtpoi4z1Wgm?= =?us-ascii?Q?9bx3m/PcG0Vfe3OVYmuF3jjcd4NqNf9WdSiBkGkkNC1zyEGM9t7ejFYAfJhO?= =?us-ascii?Q?9qsAMhQeJ4Bp7ttw3urNi4vzMt87W0tMBV7bOuTq4rMfcIBpl7x/zoF8UB36?= =?us-ascii?Q?4POuYTw8IiirlqHlNV3kbyjcBsqmZI6/tF7UB0x3jZxpjrxA3JWMq/QntsIh?= =?us-ascii?Q?56o/8paHpgWj9Rro/w3y8+DkNOEAd6l8irfKXsqjqC40YuvTrmjwp43AR9JF?= =?us-ascii?Q?Sjsu7z9RnaXSMWDHtMFYCXAPna0umcDvDVy9Xk/Biz+8hPGUwVOIEJdcBb33?= =?us-ascii?Q?O4qGL0UwlywTtK3TpFzEch4K6us4pQmsiQ8bYS914bbLsiAIIvbAP5J63WdQ?= =?us-ascii?Q?OvjP85pS0Q=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ddff0044-2bb4-43db-db54-08de847819ff X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:10.1881 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vOYeGmZOFe86ph2o1VLra+4+ugPpNDMmRVagqrJoXNNLNXIdNs8ViuUpxnW6/cNn6to7x+8GPCqzKpC7d0+ZEQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Introduce a single ELF format abstraction that ties each ELF header type to its matching section-header type. This keeps the shared section parser ready for upcoming ELF32 support and avoids mixing 32-bit and 64-bit ELF layouts by mistake. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 111 ++++++++++++++++++++++-------- 1 file changed, 84 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 6c2ab69cb605..46c26d749a65 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -473,17 +473,72 @@ mod elf { transmute::FromBytes, // }; =20 + /// Trait to abstract over ELF header differences. + trait ElfHeader: FromBytes { + fn shnum(&self) -> u16; + fn shoff(&self) -> u64; + fn shstrndx(&self) -> u16; + } + + /// Trait to abstract over ELF section-header differences. + trait ElfSectionHeader: FromBytes { + fn name(&self) -> u32; + fn offset(&self) -> u64; + fn size(&self) -> u64; + } + + /// Trait describing a matching ELF header and section-header format. + trait ElfFormat { + type Header: ElfHeader; + type SectionHeader: ElfSectionHeader; + } + /// Newtype to provide a [`FromBytes`] implementation. #[repr(transparent)] struct Elf64Hdr(bindings::elf64_hdr); // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. unsafe impl FromBytes for Elf64Hdr {} =20 + impl ElfHeader for Elf64Hdr { + fn shnum(&self) -> u16 { + self.0.e_shnum + } + + fn shoff(&self) -> u64 { + self.0.e_shoff + } + + fn shstrndx(&self) -> u16 { + self.0.e_shstrndx + } + } + #[repr(transparent)] struct Elf64SHdr(bindings::elf64_shdr); // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. unsafe impl FromBytes for Elf64SHdr {} =20 + impl ElfSectionHeader for Elf64SHdr { + fn name(&self) -> u32 { + self.0.sh_name + } + + fn offset(&self) -> u64 { + self.0.sh_offset + } + + fn size(&self) -> u64 { + self.0.sh_size + } + } + + struct Elf64Format; + + impl ElfFormat for Elf64Format { + type Header =3D Elf64Hdr; + type SectionHeader =3D Elf64SHdr; + } + /// Returns a NULL-terminated string from the ELF image at `offset`. fn elf_str(elf: &[u8], offset: u64) -> Option<&str> { let idx =3D usize::try_from(offset).ok()?; @@ -491,47 +546,49 @@ fn elf_str(elf: &[u8], offset: u64) -> Option<&str> { CStr::from_bytes_until_nul(bytes).ok()?.to_str().ok() } =20 - /// Tries to extract section with name `name` from the ELF64 image `el= f`, and returns it. - pub(super) fn elf64_section<'a, 'b>(elf: &'a [u8], name: &'b str) -> O= ption<&'a [u8]> { - let hdr =3D &elf - .get(0..size_of::()) - .and_then(Elf64Hdr::from_bytes)? - .0; - - // Get all the section headers. - let mut shdr =3D { - let shdr_num =3D usize::from(hdr.e_shnum); - let shdr_start =3D usize::try_from(hdr.e_shoff).ok()?; - let shdr_end =3D shdr_num - .checked_mul(size_of::()) - .and_then(|v| v.checked_add(shdr_start))?; - - elf.get(shdr_start..shdr_end) - .map(|slice| slice.chunks_exact(size_of::()))? - }; + fn elf_section_generic<'a, F>(elf: &'a [u8], name: &str) -> Option<&'a= [u8]> + where + F: ElfFormat, + { + let hdr =3D F::Header::from_bytes(elf.get(0..size_of::(= ))?)?; + + let shdr_num =3D usize::from(hdr.shnum()); + let shdr_start =3D usize::try_from(hdr.shoff()).ok()?; + let shdr_end =3D shdr_num + .checked_mul(size_of::()) + .and_then(|v| v.checked_add(shdr_start))?; + + // Get all the section headers as an iterator over byte chunks. + let shdr_bytes =3D elf.get(shdr_start..shdr_end)?; + let mut shdr_iter =3D shdr_bytes.chunks_exact(size_of::()); =20 // Get the strings table. - let strhdr =3D shdr + let strhdr =3D shdr_iter .clone() - .nth(usize::from(hdr.e_shstrndx)) - .and_then(Elf64SHdr::from_bytes)?; + .nth(usize::from(hdr.shstrndx())) + .and_then(F::SectionHeader::from_bytes)?; =20 // Find the section which name matches `name` and return it. - shdr.find_map(|sh| { - let hdr =3D Elf64SHdr::from_bytes(sh)?; - let name_offset =3D strhdr.0.sh_offset.checked_add(u64::from(h= dr.0.sh_name))?; + shdr_iter.find_map(|sh_bytes| { + let sh =3D F::SectionHeader::from_bytes(sh_bytes)?; + let name_offset =3D strhdr.offset().checked_add(u64::from(sh.n= ame()))?; let section_name =3D elf_str(elf, name_offset)?; =20 if section_name !=3D name { return None; } =20 - let start =3D usize::try_from(hdr.0.sh_offset).ok()?; - let end =3D usize::try_from(hdr.0.sh_size) + let start =3D usize::try_from(sh.offset()).ok()?; + let end =3D usize::try_from(sh.size()) .ok() - .and_then(|sh_size| start.checked_add(sh_size))?; + .and_then(|sz| start.checked_add(sz))?; =20 elf.get(start..end) }) } + + /// Tries to extract section with name `name` from the ELF64 image `el= f`, and returns it. + pub(super) fn elf64_section<'a>(elf: &'a [u8], name: &str) -> Option<&= 'a [u8]> { + elf_section_generic::(elf, name) + } } --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011050.outbound.protection.outlook.com [40.107.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC02D3F99C9; Tue, 17 Mar 2026 22:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788065; cv=fail; b=sXWhC1qkYQ+uGHpdP6vkfZR0Y5K+pIH1xdE8NAmNVhhWrPYehnPhzw2/vB8KN44C7Af++gHdo8oTRz6QfY7hSz+FCWsSD+qtjdenh9b44qEwxOqmIYntOyX0oa4XjcHxRcV0JkB8wedFZ9z7Hi34Z2j4cptaz00nv+9T10ZDETw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788065; c=relaxed/simple; bh=Kh44LOzmjxfd9KNVo/eohOq9Gr9WpEJ405Um4bz2GWc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=XrUGkrlZP7oICrY7glTVjf/df43sYui5zwyy1634dzQ5sgw3cnMt0nQoTuPBKVSJQsRErlpGVpJi6Co/ZsGOv5FrPj4pyexGWXQ3hF0a1ZzVQUiagAzQ/gFrJFZ6pIynPI8qjwKQAM/pTCptn5JTzakqfiaMR2mbW00XgZHMc/Y= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=hHfyxB94; arc=fail smtp.client-ip=40.107.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="hHfyxB94" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=iyfAp2uZ89igeKYhYm1pBHW85PETn3ENH60z6sDpYN0hcz7hONj8anXsMhThJek88a1Hnei9lflyc90FiXoMFe43yxZKsGwUhNIUH1T1QBySZ59HUWmuph5Ve+6ek+9VXO9RbZEY9QkySA5QUNLYRtfl3Ai6Mt5WqGKYX953+cRJ54V7Ndsh4FtZhpWcNpbP5QfeLTHZBHeAhusimarIB7CPN6x6VE1NZg+LfQaMCbNhEB90jDKf0xWilu98r9XSy8B/l7tY3fr/wTAa9207roRg3eISt9LrLGzcmd/DoklPhjzI1rG/QC4noh1P/ixQ2LOotSegYqH52CLa4OdZCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dHWfLfJwS/dFHO7S12MWlQdBJL5sP8TIQoUDspv5VVU=; b=qjEk+EQl15hoMPTpaheWW6EnbdPSVTE5BdHgdA8yxBLV7CrknvMRyNFLD6NhBYPkD9m4dr1QA7ubo29T+yPaFWUyrIuji5Hv7vSl3N2LQdrJrTwwlzGCYb6djJQWSQp65KEmg1hzhEP3lkqpReGHwaLimyCod9OvBOfcfPrH0pt/B2x44/zy0t6RKdqySXy0/rcF1/oXKyFD+4x1U2mBE0nzjtntJ5x3xWYID2q9H0yHNWBS8y5Vi6aUErNbRMeR2v7JhOK3whjZcw9nZU8AIvAn3zJ1rNg7EHNVyWsu9c48u8e+Ta1Zsc5mlxULrsJLtuC8TrARPG78hHp+qwK/Rg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dHWfLfJwS/dFHO7S12MWlQdBJL5sP8TIQoUDspv5VVU=; b=hHfyxB94OrUBCVhNx7gqCl3oFmkpACVEYToujApw4h+tOCjRAuQqiEag73PhGN2b+nstMO0dxB05GO0oQpLWtH7A6IL7u5Szov5XGeKhCPbGA5oBKcolISG9xu/Jb7j+ItQQRBtbEAZHItYug/1HQUDzZ0/hIg+PygBn+MKC+5UIKedBUaSrm1QJbWMroVnkoAzL4FLufAPV+43lrA2jl2MTdnuOqEV/hGj01l9TTm3M8jB9ob+7XpdDn/bmeY11crAfcBeLke06mTn8QM2kshQ5XuIQ8e42GszA4pAAktYD0Jalx5ejn7DXRs70va85/nAXyr/Wa92Rd/+c6rD0NA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:11 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:11 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 10/31] gpu: nova-core: add support for 32-bit firmware images Date: Tue, 17 Mar 2026 15:53:34 -0700 Message-ID: <20260317225355.549853-11-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR05CA0046.namprd05.prod.outlook.com (2603:10b6:a03:33f::21) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d174d9a-c385-4d32-edee-08de84781ad7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: H+YT0SDLFUWqxzwB/yFeP7Gfjqe9xkJ926SBUjiGuJzw4OM0DWLnSFMUP9qoNnefT4Danh1537gqD7KJown+LejVgiwT8c5zH83jupa6Pw98qWz8i2ROJGTmlKT3ZPjWayT5LaKrUprrXEN+4OhLT0FAO9krYGnlec3FyK9QA+czBd7Ulrae0RMpzwML7Vf9QPsOzd0H6qA3eBcuXJBl68RH45a7E7CZC2E/QLRqc7AoIkkUsR2AH8Kx0ZhBYsGnZc3gz7JudvrbwJ7ve5MIVAn/k4Z4dkyubzB01h6sABXDQ7nb3BX/67fGJHC13HJCcjNAsOqrNufYUcA6v83Al6+PWt5Y8WB9V7BxdfW7bi4nMq8M5KzlV3n0v/Q7noSwSGKgAZXfEzzDm4R/GW4KNKiKOT2pOrOHauDlTDutzoeemza9NTJ9hz1hFGk/yb+lkQGNqO9K9S9tGcSOlaPdmOXt3xgownjziqT8/8T8sgzvaR0/qupBli1GQZWEOQG4VADIsMXunBsSaL/mmqCfad4/uUXmxxB/3Ht3gBxVRkdvNsbdjgSu1mRnpEHVPffB4mqiktPMLFgqbiIjPbqVFj2C096j9/ms9MN0ULkIdPgWnG2QyK6jKVOd3p2zJ5Eyo11247g4CKZf0kt95BhIYLTJ2FBYrckzss6w1dcz1rwrYEIkMgaM0BT0XXXSQxOsLbCLEiSx0ykU/jb4zHF79dfQR0nR5HiKDaxxhjKtSyU= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?nfaIm6duNFzMlzOMpFkrbaJ6dSCU1mhwtAL8QqHlNgMJcdRVc2knFq6n9Gu/?= =?us-ascii?Q?lwLybIepqzqtw9bTVg9Z4sxOmioWG5VuWuE/I33A0tjB2VjSJYS+Illut3Ag?= =?us-ascii?Q?Xe5I8tKtPAGxt+k80mNkaU6zOLApCgf79FCWnunGYeOw0nBBh6TGBnFXFI2S?= =?us-ascii?Q?/GcWNN2Bs6a4c8Zy2JG97p79VnvZkoZWseiJ2QmORoPmQj/JZWK3kEbkqvpq?= =?us-ascii?Q?FJ35nu8xPNpHvegADNoik1RzI0QuVofgODsfcw9lluL78jx1UfcaTXJxKbQk?= =?us-ascii?Q?+Hdj+goO474u/AgP1JiMcZH/2ih+K2762k5fZB2wqq1HFa7vJ0IACtjGYLly?= =?us-ascii?Q?ZTSVI47///XM5SB2SXWmnoec8hZfvrTmNe5oUQ77yZqm2A4TysMsFK7g3NmE?= =?us-ascii?Q?RYbdhYYHpMcKSd+SZuJuXPVGVasQ0XW9aEYV9xA8aYO78b1X/ulY/O8o/deY?= =?us-ascii?Q?QGJ59/VRih/NQyFWIJLOVkHWuMU5FeNqTcDHg8lEsiVn0XmE5zvyZGI3n/30?= =?us-ascii?Q?4M1dFPeDAEfOtgLWBTk34D5JO1O7kOfYNwO3IkWdsxJuRouQBhhkwrHHoTZU?= =?us-ascii?Q?qn8vdQykFM8c6E9t9IdSYE69w/QIq1IsWzjfVLQH8a/LvZNVVovlmCrO4EZr?= =?us-ascii?Q?JMYPOQoT2qnPghaMNNshvO6WnzKPvLReEV4xVbnjpXTvo7JGaSDWoGOvXZq8?= =?us-ascii?Q?Pu5Na62M3g2Iw9H8JCgrII4b1MJhvgJLEzjvOkIO/kH3ULt1JjzH2MK7YTRM?= =?us-ascii?Q?SnMSQZ7xDVm4NWxsjQmeCAzz/Kl4dUNTlZjQ/cJyC67sMnboZf66QkHeOgW0?= =?us-ascii?Q?+TxzpIN4yfX3NoIPkDePDJJ4blHznqLHCM8t5V+kO9t2iQZTpkMUaW4rx7c+?= =?us-ascii?Q?1zqaYxeB7ACevnmnk3lA161Mgdrr3DMvYlIJNdTSVHvlUFOPaT38wktGpydv?= =?us-ascii?Q?etjcYI0vG0RabZ0u98rOWWOCkI+hSj64pYCErczIrw1rLDIVozmdEG76NQbr?= =?us-ascii?Q?tfoZ2yvJ2oPHCy8BR9hdEvIdBMhFjYGyXZPOQA/AcgBResae6IznEE+QA1nZ?= =?us-ascii?Q?/Funj4I/nsyGf5lO+xvMbr0li9sKL9RKXcXZ4JlGkQ2Vnc+/ItX8fgfKxUrd?= =?us-ascii?Q?kwX69AXjo7z6lZ04TQkd5r9xeSuE3N5suMaHl9sJ5a51xydcbkt19dJ4g82q?= =?us-ascii?Q?6pCiwfakKyho0oEvmUaEsVZr3az1mWnzXZbW8JR0YXgg2TDT2o7GJ51Yjvu0?= =?us-ascii?Q?URvUfGtDP2ZObUz5zBpg4rc98B3Roa3sVl4S9ZjkmREkbjdiJG+IUrZS5jh4?= =?us-ascii?Q?NxEkAqsvp7UEiY0Ni9tRnLCnh4s6zw4rvL64ZAcyql3luthGYz2Vi48BfTIH?= =?us-ascii?Q?ozsPSjsG6rNqDgSLFxwVUxPXbx7ry8D7a4h5ujvO+91kQTg7TYa4BJijK6Fy?= =?us-ascii?Q?oMcgHvEUzJAfKqfXJOWNEzndeHO8PRCqC0aCMulj+rASxUykIlCL+m4J10Rs?= =?us-ascii?Q?zfR+jRvvio8xE1OIbw6BQX2QsNuQ/06kFqQyHxsSdYioU8jRWcQZQnpEtnmu?= =?us-ascii?Q?TTPfd6urmbqhW9IJ9lUqoY4QrgDC/A6MhrN81VROpZOobkEWhC4dN6UOo1b3?= =?us-ascii?Q?6Awu9rRuOlVwcRP5dX9oed/7OmJC3g326RmC28EPW7ReJJVSV9y4DqEUof9w?= =?us-ascii?Q?R3YEeKUv2vCBFF/X358habLXqa3hhXuBNVX2dAszn9UVFD22I9Qf3jvsd3Li?= =?us-ascii?Q?J37ADwJ5+w=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6d174d9a-c385-4d32-edee-08de84781ad7 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:11.5692 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JLC0dae+jpoFIBCKKML5pxnmG5pYEg0JoLLMcExgqVQmCoP+92IcTJ/Vig4D6jTx1TkGKa0xy7rn2RJCdTlyCg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Add ELF32 header and section header newtypes with ElfHeader and ElfSectionHeader trait implementations, mirroring the existing ELF64 support. Add elf32_section() for extracting sections from ELF32 images. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 53 +++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 46c26d749a65..a0745c332d4d 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -539,6 +539,53 @@ impl ElfFormat for Elf64Format { type SectionHeader =3D Elf64SHdr; } =20 + /// Newtype to provide [`FromBytes`] and [`ElfHeader`] implementations= for ELF32. + #[repr(transparent)] + struct Elf32Hdr(bindings::elf32_hdr); + // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. + unsafe impl FromBytes for Elf32Hdr {} + + impl ElfHeader for Elf32Hdr { + fn shnum(&self) -> u16 { + self.0.e_shnum + } + + fn shoff(&self) -> u64 { + u64::from(self.0.e_shoff) + } + + fn shstrndx(&self) -> u16 { + self.0.e_shstrndx + } + } + + /// Newtype to provide [`FromBytes`] and [`ElfSectionHeader`] implemen= tations for ELF32. + #[repr(transparent)] + struct Elf32SHdr(bindings::elf32_shdr); + // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. + unsafe impl FromBytes for Elf32SHdr {} + + impl ElfSectionHeader for Elf32SHdr { + fn name(&self) -> u32 { + self.0.sh_name + } + + fn offset(&self) -> u64 { + u64::from(self.0.sh_offset) + } + + fn size(&self) -> u64 { + u64::from(self.0.sh_size) + } + } + + struct Elf32Format; + + impl ElfFormat for Elf32Format { + type Header =3D Elf32Hdr; + type SectionHeader =3D Elf32SHdr; + } + /// Returns a NULL-terminated string from the ELF image at `offset`. fn elf_str(elf: &[u8], offset: u64) -> Option<&str> { let idx =3D usize::try_from(offset).ok()?; @@ -591,4 +638,10 @@ fn elf_section_generic<'a, F>(elf: &'a [u8], name: &st= r) -> Option<&'a [u8]> pub(super) fn elf64_section<'a>(elf: &'a [u8], name: &str) -> Option<&= 'a [u8]> { elf_section_generic::(elf, name) } + + /// Extract the section with name `name` from the ELF32 image `elf`. + #[expect(dead_code)] + pub(super) fn elf32_section<'a>(elf: &'a [u8], name: &str) -> Option<&= 'a [u8]> { + elf_section_generic::(elf, name) + } } --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012058.outbound.protection.outlook.com [52.101.43.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 708283F99EF; Tue, 17 Mar 2026 22:54:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788066; cv=fail; b=fsC1qQzyCp3Ob3MZ4PDZKcuKng8uo2gf6kmMKt3lkWS3bBjFRgJE6fPCG6Qs6LoPyiPxAjWoRlZ/XrOjRsXyJm3+KcO1KROb7Ip4ifjng7AXMm7bcCg1wh3JPcY3RU4v6xQEYv/CVVVOVZ1TL1/Wuda5Dj4/szsV4XYyZIRkpuA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788066; c=relaxed/simple; bh=Wp+6peDnWiPLjt9oJP7pnh0zSHeZGJOBGUv9TbqR7lc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=S3Id1iCFR+bZglD6tNVX3HQRS4VO402iKa5TXQz8e3s3DD1VOTRycoK6wkz/WMIxm7qwmCrnCq8u1+yIowMzXbm6pgoSABiOZy4EY20C5rO51dX8CZSFfKRtnXlSH86x3gxqQmE+4A4y02I9C//dh3SEMvMzRtCPh3WSrADjCIU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=TrCDZeVi; arc=fail smtp.client-ip=52.101.43.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="TrCDZeVi" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=yEmkT/95CL7S6RqFiUI8fwJQnlq6WecLzzXkJoexWC7IPpGvXJu6rxvKSRhclRAiGZJSJIU3JP2wLkS3Q/ay+KtV11CtPaAB+P9YUmB1/Ul5JzzGNM+gBvJA4OhfMjfapHN+BwSIbsrv3nv52VV6kKYXDBbIQhp8RHivqGWXg+7CFFhQOizrJvn3P0v3fLXALOvazLZ0yU/15kS6kBw340znTsaDN9bYytLEj728GSIHwsA8KCkERRrQ0617wB7gai5fmVgcwip6DCqn1GDszEwDuebKAfv4rrSqvO367LgzpAMr/uSgma83e4cvWk3L6Xqdulwy8zrpVkhynOXYFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xBEGvVEL1fl2sgzeCIZvbA/CLj0fkKSGpcJYf170uwg=; b=ey19S3bIuagPJ5etdLSJYggr6Tyv6VOMYFIXMBAlDRXeGX9kJiBhZVUp25pzpFWlyfIjsntVWffnlSq17KOPTBNVpSvtbu5motbhFOqI/huYZsMS9/BP5lNlMUcSU4T12gren1LxNMPQOznlnFMApTL8BWc3CU2H54V3inO2/ErP2TosjAIvnUul27UMSQr3JJunOEe9AtdCS9UXzJPoQcQMltO10q0PzfJlpQJgN8qVtzw68uSvpTKKbB9ua+bh/bL3rxjh9QHnC/GQK2usFgtjdnM+d7pF1VgvJbh0Sz246oWo2Y70d0kM1ap0lc3KyAndYfv+WBivV2X/vc7U2A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xBEGvVEL1fl2sgzeCIZvbA/CLj0fkKSGpcJYf170uwg=; b=TrCDZeViFKnmLJLkSMXutvP1gESAyR/ex4LaZ426KGzDGPz4D0NoUXCr11LvcQb/rsWrsDFLGg4UNUeTepEYBE6A6a29t8U7r0uYe9A/oM1lmmPtBPQ/HOkL0zlMDkLGIv05G1x4KJXQPMetsYkkdKRaUPQQkYr9Mj98YKitHItu54kaO889uGFTcGLctHHAZeEjKVq4Lm3wjEpB6S24VMc9R0hq7dV8QUHW/f+wgjjT488t3Jrfi57/fqtzbtUI6W0da9T9GTtlbfa76B7KXX4R6KwDTwmNQmCOOfjgZHyHBclT3eWj4kBs1f4XuNG1y/CqCveDh4UJ80hFt4/OjQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:13 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:12 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 11/31] gpu: nova-core: add auto-detection of 32-bit, 64-bit firmware images Date: Tue, 17 Mar 2026 15:53:35 -0700 Message-ID: <20260317225355.549853-12-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR07CA0066.namprd07.prod.outlook.com (2603:10b6:a03:60::43) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 4732375b-e92f-4f1a-c9cf-08de84781b95 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: YtFBtP671tXfRVQqDmHp1W/ouEhJfIywq7DhZZMMBxOI9jwEujUVMXWSajCjJBrwBBaGq0aXFej9DtC1ZyQMqMAGiRDkMaRWx8+sFz1V8AL+8N73SSpiBUI3py1lN3GBSmGga93WzK9eP5VIReKxvClngj6YQ+0llZs4oONCLLF7qwSBDeM1Vg+NbYFjjo1i+jAkyknDyTgaTgVQKXrjQ00dESM/9645KWf7170oZQTZIZg2HKQZEwLL+QBeD2NuEPF2wvB6+6EDYcIQNMJVVeZbA0P8YssZxWKWKI5VY5zg8GQvQKQyAOB+/PAsiypnXoJnyv8L80iF7OvnZPg0RuDyLyxfOj/iB2Iyn14hu/ykgyZYOEC7HfNRJ5HI6HEzCEHWC+VZTqLxdPinr9KkgnP0eLFkjKPvkyqGKrSIGOIfOwI/CFeNH4kO2OM2jowFYb0fT7Ae5F0MM4BGSqBKfojAUk7Or9FTsUUiqMesiTwMs8sXOZXrz9CjqsbXionoaz4cV/rHf3hT79UTBnjtw2YpTxiadHF86OlStv0lAPk1wl2rBnx18TJbL77yFyDNSb5ZgMGhSSdriOW8X15imEFlQAXCFGc6+cI2lwOpjz9asi1bhBd50XB3dN4QgrliIyw3bdKnDMzX2JCqsDnKBHOEiIfILSYZIM/4l9/3/Ay9JA1ekhNViZPrtpf/VYUoc8io3yrEOkdc1+KE7kfCs1OHkl1r+lzPSX10r27Un+c= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?+/hgXFd0NXtlasZiSKYyZJNP/mMzVCRJoRhaBtEsCtIBnBckObEGrhqoZCL+?= =?us-ascii?Q?e5go1g/i9LulMB5ZghD2qX46dx/HtcF0uvtyWAvbqz9s+Xrk7Jt7ukdA94p0?= =?us-ascii?Q?vpR98frOv1fsa1+BLpfr7yR0Ncv4j2D869Dz7AfbEdSnlLoolZhx11gPxyET?= =?us-ascii?Q?GAEGVTSdm0qYCGe5sSRJs63fhYDCbGWy3mvyMA++o6va6wu0m+WxF9HSo9ao?= =?us-ascii?Q?8ccCNbZtKquDqYiVSiOfqdezqUPBUJZWBpr/d1OxuX0rApaCEqlcURXTDsVi?= =?us-ascii?Q?ga9ZBTXFs33OvMOzSH6SE/dnsqG78Ask/xpDUCwMcI8R008MW6m5PGrKY6WE?= =?us-ascii?Q?ZP29deu8LJefL+URjIEBj61IacwmuiqKM6TvhbmTCZDTLRp7yai/Brnso7xS?= =?us-ascii?Q?MBjIq571YfnagIWqqhqzcP/+ID3IEmnUV8H8100bZ8fQ3vqlRwWKTq0N/MJc?= =?us-ascii?Q?bvfuTxRZaD6unNxUl1Jfr3sQVIoB+JohBcrTE+Cb00YLRVriFNY7E1qcvVBv?= =?us-ascii?Q?9drVNtu5A2+f2wzaA9VoE2vQjVut/ZBwJQtAKj6GZJtqVwra7BE8pMxr5o4v?= =?us-ascii?Q?kMlcOUpeEit0APFXGp8K1FUlSjFPS7Bl0xskM+PoTXT3zI4YJ8HM36hJFy04?= =?us-ascii?Q?pXL2E7Vis/QB60Rv060kSiQb9D8Vq9INnj7A7tW8hNNe1F6yVLR6u/qvxNsf?= =?us-ascii?Q?jPOi/SSl2pIYoo6RhJmL0w42ayXC2P8Lr0Mma1dv+tN9WMTS/zxH7zb5e5Kz?= =?us-ascii?Q?SDpaWGncst7ZjWh+tGaKhpXv1DjZbbdCDfG3wscxjbGZEFf48xtwvYzOnqcR?= =?us-ascii?Q?G1/c2Xiu+qPzzLtLipQg8r1maIEaBSHaV3uraMBdkBZDQ6zoOXK7FLkRwtG2?= =?us-ascii?Q?5Pa9eKELrX8IphDcO1G8sPE+xAEj4ch73+JGqbEixbTW8dYolLQEgHz4rPnq?= =?us-ascii?Q?wzneno6j6PB0i9VmChj87aR3vKAhjEq74qUQU7T1o5Ns2TKz0yQlmQMq/JLV?= =?us-ascii?Q?bthrN7WXhBu+cBJMKs0wYGM1KKiwP32lAEIwGSsCUx0jPxDw79i3zXRpM9wu?= =?us-ascii?Q?XBi92HbdroQrBRCIhawRKpGk0wBw7eHfJf/5J9pF8FjDpiAOSJsDAdrDd1UN?= =?us-ascii?Q?/4QnDbSaKftmIxqnst3c37+HlL9yr+E7sQHHaroYGyODXeLbSbmQ3yQ4Oir4?= =?us-ascii?Q?MSPvpNjESh/1dDsDs6vb8r+gPBtYnsjsWChv//JMTbLl3Xd3VVewbf0Gj5xQ?= =?us-ascii?Q?UYXtCTdv082wMoBwykHafkkqMxaAdBEeSo8I0xGZO5a7y6G1UTn90fgyw/Ch?= =?us-ascii?Q?/gBrXQPMaLNZAtK3P053EgLMMgpMAPqwz2uAwRX4LufTF/qOuwrByD7WeQuv?= =?us-ascii?Q?a5pJoFFNrSR21VURs/uxJedLV3sswb4Et2Dbeg9JTYsrLu2+pDzdcfuZIHu3?= =?us-ascii?Q?9ZzHIyVROh5j5bWmhOpZt/MIPzLjCEDl8/+PRs7avaARGPCBROEzcJ5y0Qnl?= =?us-ascii?Q?ELWE2mWctQRQxM4WggB+YHpi+n47rKhqbVFZTDmQPsnRg9XHUa0wJVLuC5A1?= =?us-ascii?Q?OyLi76wcuB18wCZ83EXnqZSQdpDKpgxv+uLyiBV3+8ympapJDX1SugKW35oJ?= =?us-ascii?Q?vnXAaYU8nyP08VslU7Pm/TDzeYbcLSRWyDRK2970/buGAercZS1C/V2XlRNe?= =?us-ascii?Q?TWvQOSXYOQ2mzimvVt+JkYVwzBEKwshyEPH0eLd9fHfPngRKM5ervlRGtIMB?= =?us-ascii?Q?XACQ6CpWyg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4732375b-e92f-4f1a-c9cf-08de84781b95 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:12.8304 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cl2roIJMneiKYDBuv+LUQlEJsimV1iBeDZLK2HBBMLsEy+O3wDqYQHw4r/C1/JRgEQHj8QaDgoT/E34pH+LFsQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Add elf_section() which automatically detects ELF32 vs ELF64 based on the ELF header's class byte, and dispatches to the appropriate parser. Switch gsp.rs callers from elf64_section() to elf_section(), making both elf32_section() and elf64_section() private. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 22 ++++++++++++++++++---- drivers/gpu/nova-core/firmware/gsp.rs | 4 ++-- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index a0745c332d4d..bc217bfc225f 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -634,14 +634,28 @@ fn elf_section_generic<'a, F>(elf: &'a [u8], name: &s= tr) -> Option<&'a [u8]> }) } =20 - /// Tries to extract section with name `name` from the ELF64 image `el= f`, and returns it. - pub(super) fn elf64_section<'a>(elf: &'a [u8], name: &str) -> Option<&= 'a [u8]> { + /// Extract the section with name `name` from the ELF64 image `elf`. + fn elf64_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a [u8]> { elf_section_generic::(elf, name) } =20 /// Extract the section with name `name` from the ELF32 image `elf`. - #[expect(dead_code)] - pub(super) fn elf32_section<'a>(elf: &'a [u8], name: &str) -> Option<&= 'a [u8]> { + fn elf32_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a [u8]> { elf_section_generic::(elf, name) } + + /// Automatically detects ELF32 vs ELF64 based on the ELF header. + pub(super) fn elf_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a= [u8]> { + // Check ELF magic. + if elf.len() < 5 || elf.get(0..4)? !=3D b"\x7fELF" { + return None; + } + + // Check ELF class: 1 =3D 32-bit, 2 =3D 64-bit. + match elf.get(4)? { + 1 =3D> elf32_section(elf, name), + 2 =3D> elf64_section(elf, name), + _ =3D> None, + } + } } diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/= firmware/gsp.rs index c6e71339b28e..360cb7014073 100644 --- a/drivers/gpu/nova-core/firmware/gsp.rs +++ b/drivers/gpu/nova-core/firmware/gsp.rs @@ -93,7 +93,7 @@ pub(crate) fn new<'a>( pin_init::pin_init_scope(move || { let firmware =3D super::request_firmware(dev, chipset, "gsp", = ver)?; =20 - let fw_section =3D elf::elf64_section(firmware.data(), ".fwima= ge").ok_or(EINVAL)?; + let fw_section =3D elf::elf_section(firmware.data(), ".fwimage= ").ok_or(EINVAL)?; =20 let size =3D fw_section.len(); =20 @@ -150,7 +150,7 @@ pub(crate) fn new<'a>( signatures: { let sigs_section =3D Self::find_gsp_sigs_section(chips= et).ok_or(ENOTSUPP)?; =20 - elf::elf64_section(firmware.data(), sigs_section) + elf::elf_section(firmware.data(), sigs_section) .ok_or(EINVAL) .and_then(|data| DmaObject::from_data(dev, data))? }, --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011050.outbound.protection.outlook.com [40.107.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C8D43F99F8; Tue, 17 Mar 2026 22:54:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788067; cv=fail; b=gLmDdb+E0vz/W2rDLdjXhdsF7mLnZFZa+gkhlrUH4MSxjnxTPKQKgzVqqA/N5zFmZHyRagiYlv/cPkYi779NC+Vji5AStEKL4Uh/eSZ4L/h1Mh9tKjF1FOjcoO2slVFvS2hyfyu3JzOdjqYogPABk+9HkHfjUqKAsN8y5D8GfOs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788067; c=relaxed/simple; bh=9mV5x2GnrJ7ORga2OIoIGcYUETCgOxP4brMI48nQXCU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=jorUzjOYzdptytAW8XGjeH3d7PQiGjJy3EON84xgFPs2O52obW9VbEH4pFCCCvBS0N1mPOQ0GKA09QeNTr/BowVGG9FCJwI7ouZAGIgECKXzNws+EPfVLwaBxMjOgECNRqI9dERuNySnO6/t39xUQC5wRgKZznS4IK0HTkETHtc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=RtRc7bo2; arc=fail smtp.client-ip=40.107.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="RtRc7bo2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=N5XJCghJN5gXi75mznltCUWS2vVIf/vD13lAoVuCKS16RjZui6ggrAjDxwqTVeHsPURInWPDyCVPfRd75hRYZAmzUjzz3Dm77pzQkF7xErwT/XqkgJYnXYCbJDic3r0+owOk8eTGIi+7Jpuy8k0rFiUpOvhtL0YkGFJ5CbeUg04qWMAvkQ6QVAuSxMeALDMLFLyAJfnnoqivPLN08uQkk9ZhOrrG4KNBl3NSTTC7ucgULfMfpIH/T7HpxyPjLIVSmTDwvsMFYsjUdxId7kq4vmylabp2pOdF4QUckYhveIoqgJDDCBrw/i4kqI9N8OKBTESigrFetkEoI+K6nGGqeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZJwlCCyjjYZDdMLvpds2OrxnnD+XMxN4RnwtN2pNyjs=; b=lQrtM3hngnujHsdayaIFaeIbEHCQofo2g0ZHmfNsAVwNfP0sKVCjN99K7wvKqKZ8rAMOTngWV5Q78MuZh8pqtN8lLwcJtwWPxECFpDDxJueocttCPB3tmuXR7QxG8sDRQX1+qxHhD8L9DVsnnnuLSbQNCOjrWFhj5oSAwmKlfu3i4Nube81JfSV27TRHu9B8JmH18k+F+K1fAWcRO0XitRXWX/Kwlt8ujPQ+3aGFvKh/tp2miR1KojPcJ5LIYpb98gdZAl7Kjd5JFD6DzS6eDmeuwjukyudvVzDy0oDrzAgzkchuUIcUIR1+j/dnbbC5Cc6oaGr3eRrQUxS9aCPfPw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZJwlCCyjjYZDdMLvpds2OrxnnD+XMxN4RnwtN2pNyjs=; b=RtRc7bo2pQSnMw+EPcKJHx9gRxZuUW30Z6xf5CLRWVwIjRqGG48Nodp22ZwfakmM+/sgVXha74sz24bgslNHmq+oYDsm4hb3j9IQS+81/zROZBYmUsV9uxO753D9hvzhsFvIr58UhjA/sroUT1dpVbB6fIy+z274Z6MK9cXBpgTXLQUBiADcM8SbyUDkSlYZrBY67h/jeKi+SvsquGyhJeioo0dYlpiuYHx9SIvvWBnPX1iSMSELXHFLjvQfwJR6IOZ7B8skddcRgJ5nJzIidrbuQXihQxvJt0AWOcBkIMyykZOWWzfCB7rodYmT1HT6o5Gre2vwl/tV8f5sRnJ9ZA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:14 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:14 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 12/31] gpu: nova-core: Hopper/Blackwell: add FMC firmware image, in support of FSP Date: Tue, 17 Mar 2026 15:53:36 -0700 Message-ID: <20260317225355.549853-13-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0289.namprd03.prod.outlook.com (2603:10b6:a03:39e::24) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 72b2ac89-b5f3-4d56-9947-08de84781c68 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: FdPvCJO9frw/LFUkYWg2MUPAUnwSwj3LFCbG0hybMEH4KOvOgXvS392RJYYAeNdTTcQJ48OYS5/4kJkwwqnoDkav2nr1BcEiN7p707b+K5m4DevBBz2P06/+r9RrMb/rd9xDv/sBeJPryFJSx6xkWSRYFoPAwkOBshiBwdTXadZhip0Nnb7r5R25q+W0cvOjSMoPvwyatWpgUEa/LbiT6hOGHXgVRjAFVpQ8ggjkwcZOnSGx+V9+wqXBNxbmam0x1a2w8NaOo7n5t1q7ILrKuXxEMiybyFv3wkbBVMAJD6FDRnrX301NDAPGqPz+19xUbSHJZ98KDikxRvhD0hfVWebNP8R/ew0QRWL2BRMrINoiOiUoXZMz8wdH1RrctAbabNUvpuwuiekN4y+hoIwXX9jcGj7vEJkvlLyTPNppdatyDic3dAKqhJWrqrkNZueUTApg6ciAjPHFJ9n+0aJcBj9Y7DKaPq0u5uRWCmNVPbBinw7TuH96wpHVdP/0y+P7uyxV2eqKjtZjQO1LOHoMNrpQepgtqhv8fH6LXc/YiM0WXoNELck416jOlNwp0ljMe6boLPMMqIBL/NgweN5QejxbvdHAsCcrqNOsmUl26tRNbgqhXN2T8CjZS3Q8zgoAsVmaCWd23kVUpU0GMwFDd2DFjYFZWXt8B60imuZ6SiMn+YlIrVFPLAYaickEp8EnazH8FsNWwPJlGrIlO9UpZTIoLkjS0TPrc5Jvzb2Zrgc= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?qfOitgzUnLBqALDp9wg6rLG7LqJu9X3Hzu/ZZ+S3+5NkveRslE3Db/1+UvkS?= =?us-ascii?Q?IdYK3acOBSBthN1XBunYG986aGUtw00Irvh4vyXVoYIfFnSYQb5mLg7fFq1M?= =?us-ascii?Q?wJtg6mobxAMCMdkLa8Lv3tQ56zvOJiP+JZ3lU+E6n2L0s/Hrn2AhRw60+gF5?= =?us-ascii?Q?mu6BMtrjWrbmRfsQoANoFMHC+LIVDPmjj0xsuMbKyGpzt4zSFGtFSJOGcEHz?= =?us-ascii?Q?shcpxfVvw0N5JdYVTQyQOuw/RSCpULCuDfSQCwGhNeP6TV9W8IzKrlWC+Ho1?= =?us-ascii?Q?ikRLmvXtabuJoXrnfez79SO2guGppoRm7XqgnaTb1PupJ+FF7cdrUaVAfJLp?= =?us-ascii?Q?AZWD8ImxY0fOOre9j7b6kKm3vv4tVw91GNRya6wgDOFL6vtMFUAWtJovWr08?= =?us-ascii?Q?oom+A456/sDndOnfg25Qf2pdCDgwEnB77F//1cvfQ2YqBmf2zXPi7T/SNHND?= =?us-ascii?Q?5PQcxhCK+rKOu/MyfxolVEDYocwGZX/28IqRmYwVBbcdPGwpvI9K7T/WVmXJ?= =?us-ascii?Q?F3IIhsnFAWs9yJA3zpUqO7lFuH0knjZcDC17YdCV6tarvrOPPdIafNB/DpF8?= =?us-ascii?Q?3TvsXxqF5sRu+kKtLXgowBnPLIUZJFgtm+kIZYO8c8WQncmzbM2ijwtxAd1C?= =?us-ascii?Q?+fQj2gPiZBNwQ0234lQRWqaTXGFc7YlYaCahqjyerr8t8ODzI2XDJnJOwCr6?= =?us-ascii?Q?0cvM6bguHsUU6suU0HimpTw0UGv1idVJWBrDBMmIV2Ive9Zh8ZCorgP4Ruxm?= =?us-ascii?Q?4z+eBFRgzXW+TW/GjgKSlQCK2MLEtSeUDAIQBowVNt8YYJqNP0ro1PFk1Uqo?= =?us-ascii?Q?cbXCU1WEwm72OY2kxiPLXXM/xoI3XdJ2M0gYU3Kk2Hq5yjPmCVTfapLAzh4N?= =?us-ascii?Q?fAfVb+X2IjaNkzchYvLXoX4KFOekt/JUq+LEA28L3GVWlOV6C0W1fgBxQa4b?= =?us-ascii?Q?IdCpWde+8177//Pkr1DvDWP4+pApA5ptJO2+hHg/c1kAup62XAiy5RaItWgL?= =?us-ascii?Q?N0ae1QZLN6/9pgMkmvPsOOkNjn33eVMbDX9KLa2aJxXsZlHWIFadDx6EXIlx?= =?us-ascii?Q?gQMJnZFB2ZYmKpUJgV/Pbu6TvBHDYPsXL8yYrhBJlVkOCzlSKxbn0xwtMLs6?= =?us-ascii?Q?BdG978rJGpQcNP53F8uMbUBpSFVC8S1R+6FCd85qzWZiDVzhoxxzwbbkbEAd?= =?us-ascii?Q?cz5obNDVBxsU7SuCVkuwaj9m3S6ojzkDW/abvI3pxXV+e7NZELbsacLYa2zL?= =?us-ascii?Q?rOlMnb4/uCnDUOmEBxoSr5fhwnUw52oE891zBHO+COurfl0/I6J4r2GbNU8V?= =?us-ascii?Q?tDcytQKc9h7E28L1zeLx/KM/tO6mSumWtrac3p+GaJLHWW7XpkWPvoro0U86?= =?us-ascii?Q?BIMuM4PPgP6BJhhOImocYDrL2c5kmXCv3Yh2A/RkSZSmhXL6Dr5eucMZe4Bf?= =?us-ascii?Q?qxSZhr82jmU+FLfF2Z/tn8sfxUYQJd5ZeJoeMpLok5ovuBQH3fDjA6Kdu/nq?= =?us-ascii?Q?QDQu9v32C+YTMlDbwf9g9X/k8krwQiBe6dpA9NfvyHB2vcXSqrCkAwB5vhhV?= =?us-ascii?Q?ns0fCklwX1jisDRAkVn6EFjaE7S+KVyRjZwdCqA7IFgABv4qLr2blfwEX1QQ?= =?us-ascii?Q?DPQ2vPlMP2/+ZDMSGQEhP6oPyAAj9j296QkryvlSU8T0a3lo4/n7rVdNEHxz?= =?us-ascii?Q?wFMbQgNeDRnT2jI4+D6XxMK1WPgZBcUWtMaA2dE+ApANxHQ+S3H5GOPOnush?= =?us-ascii?Q?AGCkSNRzeg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 72b2ac89-b5f3-4d56-9947-08de84781c68 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:14.2649 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WTodpjxtvXBFSKfrk7fyBOpwbTeeJ33XlNH4NrU17AApI1WoXOlhe+kogf9qqwP3lrJ9RQ+X0NgvMeu2LUZyVA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" FSP is the Falcon that runs FMC firmware on Hopper and Blackwell. Load the FMC ELF in two forms: the image section that FSP boots from, and a CPU-side copy of the full ELF for later signature extraction during Chain of Trust verification. Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 1 + drivers/gpu/nova-core/firmware/fsp.rs | 47 +++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 drivers/gpu/nova-core/firmware/fsp.rs diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index bc217bfc225f..bc26807116e4 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -27,6 +27,7 @@ }; =20 pub(crate) mod booter; +pub(crate) mod fsp; pub(crate) mod fwsec; pub(crate) mod gsp; pub(crate) mod riscv; diff --git a/drivers/gpu/nova-core/firmware/fsp.rs b/drivers/gpu/nova-core/= firmware/fsp.rs new file mode 100644 index 000000000000..5aedee8e6d41 --- /dev/null +++ b/drivers/gpu/nova-core/firmware/fsp.rs @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! FSP is a hardware unit that runs FMC firmware. + +use kernel::{ + alloc::KVec, + device, + prelude::*, // +}; + +use crate::{ + dma::DmaObject, + firmware::elf, + gpu::Chipset, // +}; + +#[expect(unused)] +pub(crate) struct FspFirmware { + /// FMC firmware image data (only the "image" ELF section). + fmc_image: DmaObject, + /// Full FMC ELF data (for signature extraction). + pub(crate) fmc_full: KVec, +} + +impl FspFirmware { + #[expect(unused)] + pub(crate) fn new( + dev: &device::Device, + chipset: Chipset, + ver: &str, + ) -> Result { + let fw =3D super::request_firmware(dev, chipset, "fmc", ver)?; + let mut fmc_full =3D KVec::with_capacity(fw.data().len(), GFP_KERN= EL)?; + fmc_full.extend_from_slice(fw.data(), GFP_KERNEL)?; + + // FSP expects only the "image" section, not the entire ELF file. + let fmc_image_data =3D elf::elf_section(fw.data(), "image").ok_or_= else(|| { + dev_err!(dev, "FMC ELF file missing 'image' section\n"); + EINVAL + })?; + + Ok(Self { + fmc_image: DmaObject::from_data(dev, fmc_image_data)?, + fmc_full, + }) + } +} --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012058.outbound.protection.outlook.com [52.101.43.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 135833F9F48; Tue, 17 Mar 2026 22:54:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788068; cv=fail; b=ZitB2xovSuMSJ+kXx2l2EtXdtUwF6wN4ITNbvuYg04NlRGsdeYrvolZKF0q3aPtIV9cs0L+jdHoSAXH/TEQDVyKip/9vZ26yYJhR3GezqdO41CwFHswfP/aDTaulSJAw5QnfEBUUjK93hx1LArLy7iJDiXVgouN/N78JrLfG0y8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788068; c=relaxed/simple; bh=9HVIv2Ob9jqkZQHCFAQKrSMNLt3aIvtUxN3u69tr2Ek=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=AQaRvHP2WdYCTkoZ1FHDeCHCzUyO7qSGXlphUB2SwgrynMuwDXXR2ret0nuxQgT0KoP07kkCLPUKAFf3DhVXXV2f0SzT0Q09q0RRgrTJzFd0WMDU2gToUnXd8yRgjI18/tWwzwfRxPsHyySIgAcjXnjCGq/DSEbmwuDzjKlk3DM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=OQQ0XW9t; arc=fail smtp.client-ip=52.101.43.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="OQQ0XW9t" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=TBna55hi3x/y3yCWCbIMFuFPTisKKnSqu8zoiYgHkYrF+nyBmg9J3O9pZkZvr0iBJlbi2/4TesXE2OcQ3OCWiMYcL/l/60NNCLT2fRHtApTILm9QPUA2tNNtlMyzSw574mEyOqK3VNPuP71QBJ0ckvE2nR2eqNCLPz5osBHGpvcm7drdwc7xLlm4O5CwZ7pvor6F1s/fp0dbQiRd1vm+W0a4UEmGTbywaiXP8ImYJnUYi1srjorrKcPlwdPi1BHnkeoWPFmR7qwiFddH+vUWI3IavVi/zTlhJjP0q8SgPC8vB8ghVdMyyYtTF7vbaXUZmIdtMTC6PBZLp4etHR1BsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TGT+JL+3eoZTa5OC0izGMCigslcKHghTNFlTCRuBHc4=; b=SJIZ13ZCBqZzGRleZ6pGSB/QcheMall8ANsNeiVKWeobDDRf5WcsnbqU1ZfCcDrYskICcCxknX0uqYATCwa4cgQ7p9vVyjJJH3Gk6/ZHb5B4AT0cRKZ8gIiMA94oQdNE0Loj7uihuNM4FVqpFPuGtC9AET31VJ72ZDMgUlpxa0hJNWLXrIAySctrt7BZcm8KuIt/lWRqlrsCPoyeBRZR0RjthJB6UH2muNCgWdun1QaxREqUkLbMTKlLNc9MTEpBC2st+dfPiJlWBgazIHvrIlCfua9sN+zzI5ENi2sznhecuEZvIh4HfEScnE6USSS4eoYJ4eimqFG2rJcoY6czEA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TGT+JL+3eoZTa5OC0izGMCigslcKHghTNFlTCRuBHc4=; b=OQQ0XW9treP84hNkUdukBjukN/gaX3k0ZRLl3ZJXUfVTytFolPS2cswTrETFDJc4DGQtBFPFPS5+eqsfmchiRkBJ1UB1lj1Q0hafk+28U9gn40o5dtPPPHL7wBXoh4DuiJki2BavopNp6XKwg1hdvjV7R+wachedVWMRWOLVhDcczAloRF5i86qjtO3BNyPLJV7e6e7CWiLFVBgWDxIjDqPHY2f0NLtoF0lPOP3BMSxG/MRgpHtgdh96KAjvVWeb964AI/ZURLQzbbcVJu/D1tBlAKDIdMtgA9EGN1YKY5vqsuaRc0PIjzPyi8OVJmhRALCZv9mzz9negc+FzwjSSQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:15 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:15 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 13/31] gpu: nova-core: Hopper/Blackwell: add FSP falcon engine stub Date: Tue, 17 Mar 2026 15:53:37 -0700 Message-ID: <20260317225355.549853-14-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR07CA0059.namprd07.prod.outlook.com (2603:10b6:a03:60::36) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 983df694-dc10-4c2a-86a5-08de84781d20 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: D2qb++EU6D0s5fgQ2hXPKe5uxcZAarwONgbEDi/GVJlGT9NzX5epy6mrDGk6hVMEeMq1ievaEDl52aPEaDDKNN8Q0smidYInHcGHHF2OWzV9QSjBuauBX+w/XGcYwVPJAWtz+alB7ZHqHTyxZqvWtT9fjidjdnf/ZYqIuLYGLs9SJB1KXHqg6eWrSerRT5Ho5hMXoslwAA/v0pOLlLvqu+Yhty3Nq9JRlsQNnGumgA76MyfFx9Nd3L2g3QHCd0V6AtySldVbt24ijWwFX9SCm/DgvJON+EvhzIiC7LJTjoO06EPzYGQ/Na1O4Ie97+zRzDPJvuCC/YgUAw95eOZAVNijkzV/p8pab48ksYmgm9x5KAL3hCLgjLWyoBekQz3vIlo7ePRG3OKxSNlyQY9ClI0XhBMhYBVbZMIF3Toc7qVXj4FdaAZOwaLsIDORYWXyWP1+vJ1EPRoWZhVDRoiiqxr0Nc2cYpgkO8PwxHXGbB4eUZo9+di8Sy3OMKGiHGJdc56MN4eVzj5RQxIq7mWkiMSovvn6i3Z3B5GgqJECVFhUac6o4lyIPrEb1D0G1rplHw/rPyRZKRFvyYPdtPh+TrQpj81evJrRk9a/nbCMcagvS8SKuBhQRluRELqqFf5NNLDx6fE8DxAYZaeSdu7cDNXwJ3CmJAzLvWmHYNY9o2SdyRHzx0a24Le28H5NKgC1hamiPRero4ix9oTqakbp5YVW4wRjbexS6yQOUw6yu2c= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?1+ybUvryp8AO65cMJdLxQRVsN8hYkxcu7FFcard8LJAHnqfqcplcUBWfbxQa?= =?us-ascii?Q?QkL7GlD6Hbw7Uv4SuYCkL8JkNGjHbczi1MlXywZvZHcurO8nL3POblZjvA6+?= =?us-ascii?Q?LXVy2Pp/1bIsjy3bTqzlHMOaTv7y+69D7t05MF5vendCoExdZ549vfNQSPup?= =?us-ascii?Q?Wm/26ckVMXco7IPEuZ+MSe1kmAJirNBp41YhJhR/4Th/yUzc4I1aNbRFTGPP?= =?us-ascii?Q?EtTR9oeKYC5vyeteI/wd6G7PE/xsTbPCgGigTDF+eVoyzmFWJDqy74P3zVSk?= =?us-ascii?Q?Th2D+VyQqt+XXoM+qczCxJ3NNULtreT6AAk2yezeMz7mKdN12BxoI96L59PI?= =?us-ascii?Q?PcA+8ogc3Ai/PkSljeQE32XXGTTASbqIwC3WfUY8wCM9S/rrweCPXyeF2Fwh?= =?us-ascii?Q?vIg5aNLIuaCWEocMzx1vhgnNVzT4Gq/R6Eq/AG4GERVwZK6Wq1wwodS2QSSJ?= =?us-ascii?Q?uoaGW0/12YYguW+6iOiiP0Mg8Z54CiNE+FqTHklyCVkh0kZVauMCGtNTMvSL?= =?us-ascii?Q?nNUuBrw99uejoDGQIfuHBHuXTMq5eEJkyxYEHRvjeBVYeE7teMdSLDiiSbq9?= =?us-ascii?Q?gcrgDAxISuYUhHQ1HBP2YUXkPCy83xvGd9xviHHqxNHbGQXp4wunOpc+Q2by?= =?us-ascii?Q?S6tUEqeSnonrHIppop2emLBR+s+W257Gz5buO+gOJnDr1/vAgmYEIOt49QKB?= =?us-ascii?Q?T9NVli3EDhfaPEmgPnfF04/OEdGe+rFz40wPRVUzYb7U4l53RW6kWMaIe4Qc?= =?us-ascii?Q?WKcUQKKRl7bMRJdTtAG8Ho7IeLSjFbqlFDelZT/NZxBWHBfzMHI3oeyd8Zyf?= =?us-ascii?Q?0Z12ypxLCr1W1iEG+5ndsL0lkRd5okDxf9BUqCBeq4HTy1IAjgF/c7PHIgL8?= =?us-ascii?Q?+nD4U9jsKTZ96fFOuW3DsGTjfRjqxPJa+VPW7gtujaZKQrFbEjqXBu8jIcEX?= =?us-ascii?Q?5hVIyCLHsgMmV190SQG6NjGC8KEfotU6g8A2+F91UOf6gvdgqYr5Egilip18?= =?us-ascii?Q?m6fDYP0H3Q62VrCJJdk2sniO9u7d1wFE4HSZaT18XDgOIwNg0aOctV4cQJXO?= =?us-ascii?Q?8HaQdgO0K/R/BPr+uo1I1dowMo95XfvIOmssmJFDqCdt3BLso6hVB044+owe?= =?us-ascii?Q?ZqGammUpibVj1F+8RimsOTlut6fpZSBv2r3cB9zPIyRdIRXvRAIqa/sFyM94?= =?us-ascii?Q?0yChvGzoCeluxzF5QSvTM1dU9JEQN7yOmWMdGuLeia3mMRxyyQH2dgoYcr+V?= =?us-ascii?Q?D321SFwyf2f59vUhle6D390p6c1mMOrtsJgWYMZyYgFjQ9fTihH4Xn/TboMl?= =?us-ascii?Q?ojxbhfdmqn+fevjHEFShIe6Hty6Fl0mkokFbGWZw/hdFamdAH/oHWDGV7QuS?= =?us-ascii?Q?eILEDytNxAZY234oNm+n02FXBie6/u60FaLk0x9yLdSv0qBO5gJJCu/B7dWi?= =?us-ascii?Q?kX58N5G7hfg2MfxisYolVPrDQGknYJCogFmzlTvCUwlynRmvDngdYAGOaBQz?= =?us-ascii?Q?auETvxdJgRpF0PkmYEaxq5eCHOOTgyOsB7qk0GMAT+uZn504pM1x6FA3DV6H?= =?us-ascii?Q?QQsS5AkDfEzJ5JdbMqPkbf9xxj6CmTApYfkRpl9tVelkqgq/NJ2shdOw7F4j?= =?us-ascii?Q?n7Zz6dgKWxfqp8JHXPUmFMWLQIBLHOCYxQvxkM3Wl9eb5E8e7iRClo7LowpB?= =?us-ascii?Q?/DnvzQNqNg72NPCOavzOG4oqYjoj5uTeojbGYYCqVf62Be5DCt0cRaRvKiYy?= =?us-ascii?Q?l2ITqW3AIg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 983df694-dc10-4c2a-86a5-08de84781d20 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:15.4251 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: St/A62ujR8Q5Np369JAhoUYqcz2sfcWzN4fibYxjfZPT/dS/B47/LYiZlxd/pitwRTYLc+6pmfrE1Dc+CguOyA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Add the FSP (Firmware System Processor) falcon engine type that will handle secure boot and Chain of Trust operations on Hopper and Blackwell architectures. The FSP falcon replaces SEC2's role in the boot sequence for these newer architectures. This initial stub just defines the falcon type and its base address. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon.rs | 1 + drivers/gpu/nova-core/falcon/fsp.rs | 30 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 drivers/gpu/nova-core/falcon/fsp.rs diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 7097a206ec3c..f515a4ff2f5f 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -33,6 +33,7 @@ regs::macros::RegisterBase, // }; =20 +pub(crate) mod fsp; pub(crate) mod gsp; mod hal; pub(crate) mod sec2; diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs new file mode 100644 index 000000000000..c5ba1c2412cd --- /dev/null +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! FSP (Firmware System Processor) falcon engine for Hopper/Blackwell GPU= s. +//! +//! The FSP falcon handles secure boot and Chain of Trust operations +//! on Hopper and Blackwell architectures, replacing SEC2's role. + +use crate::{ + falcon::{ + FalconEngine, + PFalcon2Base, + PFalconBase, // + }, + regs::macros::RegisterBase, +}; + +/// Type specifying the `Fsp` falcon engine. Cannot be instantiated. +pub(crate) struct Fsp(()); + +impl RegisterBase for Fsp { + const BASE: usize =3D 0x8f2000; +} + +impl RegisterBase for Fsp { + const BASE: usize =3D 0x8f3000; +} + +impl FalconEngine for Fsp { + const ID: Self =3D Fsp(()); +} --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011050.outbound.protection.outlook.com [40.107.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 788CA3F9F57; Tue, 17 Mar 2026 22:54:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788069; cv=fail; b=MAQ34Zirb4Un87I5PTd8VuuyJrOIjCqd6deQsB6swZAE9exvh54JhHZGHvP7xjjEMlSCB6UNkZjDuZzBqoRcrLD7J1gHlYGkvrvG8csPT4zD5knYtI7ywSI6seKjUo6tPZlhYoMchoPDh2KH7umCDJRNIudAOeblQJv1WkohsVo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788069; c=relaxed/simple; bh=DgxK2O+y65ATaa48kI4pKXj8U7y35Un9j6nPTbiqtHE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=JvQLCIyJ7MmaXNLKqI4ZuEVd5EPmOoZLqlhMWhJm7fWc4+kzPqKyVqOGJSLxElBrgX3mLjZpgZngWmJsCEA3LF+zMkgPZqICcPLUmgOo2Zoo00g2SMxB24NMBa8ivJXGj7xiX8JE0eQbhs2a69VEo9YXxcxLaxeP+Vxq6eGpEpY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=r9L1WesC; arc=fail smtp.client-ip=40.107.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="r9L1WesC" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=x227PBAL0r555ICw4qVwUAlwvfUjfM/EfAKgdcwGCmSJ4Td5/cviVk832Lhvf3d54Xos0m5dybMwCy0oM//hdsOsKi08WeVeAQ0bNhV4VhiYIGQdM0rPq4FHFxWOuF4laX/bCc/bmyvneuskSKq+ZU3ywoaMQlgnusgbAN8q+Nd7o6HviXc+XO3yekfwQivoqpVnQT/DVOXOqSDIMm1e1oGQd8Mot56mpXNQQKuPJKyskminFZV9/luu0GJhcMDgqoA2sD5pc8Ksn1DptUFR96rjpKcURebPtqqRwV3rtRTnuM7sY7jNpIJEmCRxMTEnM++HYbswU3jVaBbKTwKO/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QTsx70V0qdYFEfuvPC7b2bRXggX7lxrWj3DYMMvY2jY=; b=DfQKGR1o5lo68MBUYdPMIJva+PSSGc0T1FFrh016umeu+DByE3tWq1O/+8qtaonTe+myCJ2EPH7iTa9xTnWAJ4lW1KJ6HIWAHwoGyKME6wIeK4Dn3MT64ZYj6GRhiZcd367pTMMPMavGs3HwEXHuYKBoXgyvWOY8C9J/+QUamNbj1otGfaybvmrcdCxtChYVM1qJYn+lEczI5xde/beF0eb1x+SWVzKIOeYopZNo+VFHui9+sRVkuPTvjWxTxVKIXuAQmQrHZlOljX3CelS2DG6yQD8CsCqZrnuXk3KjOhqS0Dq05yKtvtSQazKnICTd9LPAsay5dvQ+2XdYXtgMTA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QTsx70V0qdYFEfuvPC7b2bRXggX7lxrWj3DYMMvY2jY=; b=r9L1WesCqqpLcQw1kVkkiXVe82HVSsuoT1OOSWHnNPeWIGS3Eh+uYK0cOx7GcwbZ278JMaXqWfwvjCyKxDhjWQuFWxpcgFcvt5IzHs7hjxJVBenx8S6MN22Z0WPK1EYcxPLLYt+S2b96ys7UPJcBu5tnYBn4Rcxk3NWyZuuIz/EMoTwu76P98Oew5H8+IoZOwxhMPJfLD4wxHvB1TAK+n7xQmLCjsPNjhJkq/c0tHjC5Wvf8d1OHeuU0DeWBuvKUpKCwfo8czgJ2DnSLHqq+cgikwNaoGPet6zhvpqyDUUw0B2+WUrQuqU+vGHGX52Ue+vyynC2F8foT6a+uck1V9g== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:19 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:19 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 14/31] gpu: nova-core: Hopper/Blackwell: add FSP falcon EMEM operations Date: Tue, 17 Mar 2026 15:53:38 -0700 Message-ID: <20260317225355.549853-15-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY5PR17CA0023.namprd17.prod.outlook.com (2603:10b6:a03:1b8::36) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b6249a8-6af6-4983-fe19-08de84781dce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: oqZAuyKXt1aauf02LNffPkxALQ2YI2plEJ1Bp24R4IGDTAJMikdu8IrLku0ZZt5RZZk46fSnyMoWjp4OP3aRWpcKnNcofsRFOEWPnh8Z5dZVaeJJOmaFK8HdimtZA+l8MlTjfaUTeh63OHQOwrfy/HGUBrErEbFJ0GjpAx+hXJMtQTZPEnc5bxznGm0OtRwCQ1TTWFFzQnGGyyzUyrYwvdYTjd8QonOOHTN21n8eB5D9ukqn7wXoBKimde4HG2YTCD09Rdd0VeklUiUVP59mcg3L0jkvUlBQTxIpik1S/wubN+B+bkcWDUkW4FFOujcijBn3xQFESKqGFUYtNcl8ihZFbXFIWZIVCCwGVNfbb8UdI3WqB2y6Sg/CJLEmmGRG2mmRLDwnSVOsjVHYw6MA0JrmZf1mrdoXUcUjW0EmWHDCBglO+6366Baf0Ou7ONzcpi72FXo/Gr2yaRh76q0cLR8TM0xBWI4LLB2EtZOson0nRO8RxsPXoZaKQfrzoW7eCa5Bd3mJPJwDJgAWBLVAiQfdgxlCquS42GLZyCY4WWCw0sV1PCqPQNVJeXFXIK8LvwvE8wGgqDkckpYCO2SRij8pShJ6JpL5IoHobVZutmvDCEp2MewMcC66rVVaJlkE568+XZPc43RObSCTGDKUvWqja1dwakX1a6T1e4JR0RNrtIdjJSebmD97ZqLUrpRuvl/VBx1NLaFpp9wnmCnQqPg5AGy2NlovtZIf1EA9l2c= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?+CvnNNj5p69oZW6fXqhgy1jk2Hvb0Wh3PywzN/Zz6u1k/+wHLr1BRaQtbtD3?= =?us-ascii?Q?T8zyoW69aUqNoLTEZ4YdnNFir+P7Ywf2+9MK5D8q8rOyxn13hkxP8nt8wi0F?= =?us-ascii?Q?TxR/nxbNy1RbtdzQFLuXo9VQeGkxMNw361LnAUmxSjodApUf6yqLgnWUITdn?= =?us-ascii?Q?gZ4O1ye4ZMjdfeqarDy60jljQuGbtyAXrvWEmoN2t8XCqk1uHia1uay4Bp5Y?= =?us-ascii?Q?RH0AUHZTYQKfRxunycSPqvVmMAbtcAjqiSSHOA4BkSte5UR+OgOYpJnsPv4Q?= =?us-ascii?Q?K+FV3IKd5p0QnzloSYBOWusX3TgTc6N+pDbLFkVwq7GTCkyUWkltEcjOMVT0?= =?us-ascii?Q?a/GykC31iesumX3Unq5ffAqSzWuUhkT/nIJqY8DjJwyR3FibSDXY8w7VY+Ev?= =?us-ascii?Q?4bv933nVJXJdc5zLOt+tbcw0iCeS/YfpFuh9seoJ3RV1/IPBUzFNveyncVI7?= =?us-ascii?Q?YILFZXa3g6yxd/zeAb4+7Lqq0pJ9pQv70F7F8znA+muQfKQlam/sHiZ/iTCr?= =?us-ascii?Q?uRWEFVJHfEvPWxF8MopbUddiP55EGnlbnxeyej5s4psqU1TeFVQ2Fa7ChSNX?= =?us-ascii?Q?92eWl1RZe07LvpsuLG7FuPVp9KGX2O8EREtyVnZ/v1mkna6e98F9Z+NfoXzw?= =?us-ascii?Q?ZW6RjXvFx9GVkazwSKewI6tFUtNioJXUhSxZNokIuFajW65BnKcC4wm6EyUa?= =?us-ascii?Q?DaPwtsw52bCE4zjdv/OvhxxJq8p8l5L3z1xduL1VLhWBvtiXTK4wf9zPFfzQ?= =?us-ascii?Q?alOiSWDX6wjKG4nykg4uisnWNqfJiydtZeHCZhPkZ51MOUcIMW8x1FsH73F+?= =?us-ascii?Q?b15TQxJXpgj938Kq+nurZMsm1OVpJw4DjUyEyBt76xUVbdt5jXIpnDmOhcw7?= =?us-ascii?Q?dURpu973WccL5qO6SHXY+2UUlbHbIcMqoA0aAbk2Xi0J4NcvfJgojCSy+1S1?= =?us-ascii?Q?f1NGNFCRTuyk6a1toFSEmRVV2CtpCef6l4qjsEdX/41O0SBlx7UXurOFRgn/?= =?us-ascii?Q?/lNDKU8dlmK908oTHS1YvLsvzsE17ILb/HjAc3nCWKMWS5mQXiHYHjv2MzrL?= =?us-ascii?Q?Ux0aoH2EsF2JYQbceVU5l5UPY6s+1m8IT82fbfA+HGJ3jfwJc5iPlB9cgc4G?= =?us-ascii?Q?k66xtHFE2k68WduvUslIy8BL3Pk2vICa2keHelgXYIqe6B9O9pUt3TPgPXLs?= =?us-ascii?Q?doOzKrZx3V5AIW9gxk6g+Ky856FhHt200AdNVkJfMuf7x8+u7DqF8AAV73af?= =?us-ascii?Q?QgQcXkiAAk2XJn1eaAwTLLa7zFyGDMEebtKGgbj+JZlQ03HLXQX2Myq+p7Df?= =?us-ascii?Q?lK3DaaVMTZMcsXX6BYHziStoxw0Gi4lP9FtkVo65sjx9oTswQ/mgXH+wnCgS?= =?us-ascii?Q?yJfI/rgCp2Hes9ukyAh4SjGDJCEsO7NpGf8HOTduBEV/+ycbZxjdenNpr9TR?= =?us-ascii?Q?hfSygq6LNWTLPso1rgUQzyt/Cc9mAX+8a68Y5zFv7hhkf3D57kTipRMfyu/O?= =?us-ascii?Q?1Dt1oDqlslqutS2mdUJoYRt7izQ9pAEQCajzYX1p01GFhZH6RA/FwZLin7Sr?= =?us-ascii?Q?TRxY3IAdSQlxbFJe0YIN2G/xe6AGXz81v3gesrMZ574wOiceIJQmEdYKVP0M?= =?us-ascii?Q?ZHMxLey7flDQjmXYugxDyZamTOha7Tv1sDLSuAW4J15I1KTIfnD+JFaNa+Ry?= =?us-ascii?Q?EHijrp8yJIaXd0ZAXL6D1E96yI6lzgxKe87jExaQycRw18tQZN3BE/u7sy7g?= =?us-ascii?Q?gABlmrFDmA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3b6249a8-6af6-4983-fe19-08de84781dce X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:16.5847 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Bsx362c+ZM91ErpWchymVzrxICdLTiLECo9nCGSbukTA+w4kbbdSlkQeefTcBMN/VtJcW7LDhNdmS26q9q7kRg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Add external memory (EMEM) read/write operations to the GPU's FSP falcon engine. These operations use Falcon PIO (Programmed I/O) to communicate with the FSP through indirect memory access. Cc: Gary Guo Cc: Timur Tabi Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/fsp.rs | 120 +++++++++++++++++++++++++++- drivers/gpu/nova-core/regs.rs | 12 +++ 2 files changed, 131 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index c5ba1c2412cd..29a68d6934a9 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -5,13 +5,26 @@ //! The FSP falcon handles secure boot and Chain of Trust operations //! on Hopper and Blackwell architectures, replacing SEC2's role. =20 +use kernel::{ + io::{ + Io, + IoCapable, // + }, + prelude::*, // +}; + use crate::{ + driver::Bar0, falcon::{ + Falcon, FalconEngine, PFalcon2Base, PFalconBase, // }, - regs::macros::RegisterBase, + regs::{ + self, + macros::RegisterBase, // + }, }; =20 /// Type specifying the `Fsp` falcon engine. Cannot be instantiated. @@ -28,3 +41,108 @@ impl RegisterBase for Fsp { impl FalconEngine for Fsp { const ID: Self =3D Fsp(()); } + +/// Maximum addressable EMEM size, derived from the 24-bit offset field +/// in NV_PFALCON_FALCON_EMEM_CTL. +const EMEM_MAX_SIZE: usize =3D 1 << 24; + +/// I/O backend for the FSP falcon's external memory (EMEM). +/// +/// Each 32-bit access programs a byte offset via the EMEM_CTL register, +/// then reads or writes through the EMEM_DATA register. +pub(crate) struct Emem<'a> { + bar: &'a Bar0, +} + +impl<'a> Emem<'a> { + fn new(bar: &'a Bar0) -> Self { + Self { bar } + } +} + +impl IoCapable for Emem<'_> { + unsafe fn io_read(&self, address: usize) -> u32 { + // The Io trait validates that EMEM accesses fit within the 24-bit= offset field. + let offset =3D address as u32; + + regs::NV_PFALCON_FALCON_EMEM_CTL::default() + .set_rd_mode(true) + .set_offset(offset) + .write(self.bar, &Fsp::ID); + + regs::NV_PFALCON_FALCON_EMEM_DATA::read(self.bar, &Fsp::ID).data() + } + + unsafe fn io_write(&self, value: u32, address: usize) { + // The Io trait validates that EMEM accesses fit within the 24-bit= offset field. + let offset =3D address as u32; + + regs::NV_PFALCON_FALCON_EMEM_CTL::default() + .set_wr_mode(true) + .set_offset(offset) + .write(self.bar, &Fsp::ID); + + regs::NV_PFALCON_FALCON_EMEM_DATA::default() + .set_data(value) + .write(self.bar, &Fsp::ID); + } +} + +impl Io for Emem<'_> { + fn addr(&self) -> usize { + 0 + } + + fn maxsize(&self) -> usize { + EMEM_MAX_SIZE + } +} + +impl Falcon { + /// Returns an EMEM I/O accessor for this FSP falcon. + pub(crate) fn emem<'a>(&self, bar: &'a Bar0) -> Emem<'a> { + Emem::new(bar) + } + + /// Writes `data` to FSP external memory at byte `offset`. + /// + /// Data is interpreted as little-endian 32-bit words. + /// Returns `EINVAL` if offset or data length is not 4-byte aligned. + #[expect(unused)] + pub(crate) fn write_emem(&self, bar: &Bar0, offset: u32, data: &[u8]) = -> Result { + if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { + return Err(EINVAL); + } + + let emem =3D self.emem(bar); + let mut off =3D offset as usize; + for chunk in data.chunks_exact(4) { + let word =3D u32::from_le_bytes([chunk[0], chunk[1], chunk[2],= chunk[3]]); + emem.try_write32(word, off)?; + off +=3D 4; + } + + Ok(()) + } + + /// Reads FSP external memory at byte `offset` into `data`. + /// + /// Data is stored as little-endian 32-bit words. + /// Returns `EINVAL` if offset or data length is not 4-byte aligned. + #[expect(unused)] + pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32, data: &mut [u8= ]) -> Result { + if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { + return Err(EINVAL); + } + + let emem =3D self.emem(bar); + let mut off =3D offset as usize; + for chunk in data.chunks_exact_mut(4) { + let word =3D emem.try_read32(off)?; + chunk.copy_from_slice(&word.to_le_bytes()); + off +=3D 4; + } + + Ok(()) + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 53f412f0ca32..f577800db3e3 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -461,6 +461,18 @@ pub(crate) fn reset_engine(bar: &Bar0= ) { 8:8 br_fetch as bool; }); =20 +// Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell). +// These provide the falcon external memory communication interface. +register!(NV_PFALCON_FALCON_EMEM_CTL @ PFalconBase[0x00000ac0] { + 23:0 offset as u32; // EMEM byte offset (must be 4-byte aligne= d) + 24:24 wr_mode as bool; // Write mode + 25:25 rd_mode as bool; // Read mode +}); + +register!(NV_PFALCON_FALCON_EMEM_DATA @ PFalconBase[0x00000ac4] { + 31:0 data as u32; // EMEM data register +}); + // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012058.outbound.protection.outlook.com [52.101.43.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D42573FA5DD; Tue, 17 Mar 2026 22:54:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788070; cv=fail; b=lp2s+PrWCAlKHOtN3oQO1/bYZaVnsQv+Mh5nPYkwOUMW1QoWqgHBCsEpa2tOe/2+J5Qy/Je0d55EbfdR5cUEUZNRd3RWqFiGZr0jXi8b8U1G6zL3lyJ8pwMEQGyrUup2iiaLvL6G5Q/Y1Y9y95QUyCEk1mPHAbL6yaFhs1CEPp4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788070; c=relaxed/simple; bh=dXR3t0LZJm+jakgskbQFTU1Ve7A/1CgOThuNNlU+C/s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=LArklFeJNQXDbO7m309zUEAaiUzH1TGzcUpCwnZrH7NxuKz2d80+mM1j1MO/MnV3R8GD5IPIYjL1nMqgbB4w9K7fs71r4tLfU6xfzFYrrjFYa3IE5XVexf9J09tqGIif6XFEOIwZMk1b5ParJrrBBDpSFMqzOVq+UsXX25HalXU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=JvZLnslb; arc=fail smtp.client-ip=52.101.43.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="JvZLnslb" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Jnu50D0PrdVB3ZPd0kv0Y4A01mCI0bR4sxklOqfpWiHiKbgOb4jPcU5QcV+yCYktjV4kkKSxMbQ/UqCUEGFIijuZWLY97I8wAKJKsEi0Pk3FQvsHlbWeTDm/eOyBTcixeRSNUTdkN1FZE7HdL3JzrULSeaNcTDh9tYRegzPAwdWGhJcjIRnwvPe5vqmEt2qYQbFbBXwyLszr0YneVNFt+wGU5gB0s4bdKfiCxQwSzPX6IVyuQ+ZHfYB0F9Sj9Jn4bC1qZ5TREe2TOvSZ4kqwJDxQ5UICvvZqGfu028EzRVwH7HBEOPHUyUdXJHQ2oBTnfW7oKRd5q9Ke3jBlGsWk5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Mtt/OKkiOahKRBvb4nHmvsF2sNBRQikoj7/lkRETgBA=; b=fX2z5iztjdvMr6eYa+TXvZyLKaBZunxpM4ANx4CdF9M0kimuK/BBN/J2n4cqiAp6h7ejjP7tzLHfIuGIvLhfNoCaHCC7y1Z941or17lNgAbVWelLmmeRcKn+h8URxW+c1+JM0PoxzWSfNw4DlEFAQuWaBiG8YKel9hucviiaZ+Sp+cNLDX3//3udAOHQ84Bdam9Lp/PAzqOFO2yY7L6zUr4cSqhHDU4XleqC8AualjP2mFazzcTZYxJvrobtQL/ce+xKwuP5Na4kXnw1iJvP8pXpjI2Lc2/e4pnBTQjx/vA+cfvHV8pZxao55xwpvTg8lMPpIjuoWmkQM37oCBApUQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Mtt/OKkiOahKRBvb4nHmvsF2sNBRQikoj7/lkRETgBA=; b=JvZLnslbkWx811iyIJsbveWZrYM207y6EyfGLWUuthBeWAUzRajYrCtgEXziWmff1D8koBAh5I9eVaBeIRf0rfANj4cHWur2a9HC0D7/2FTZnTNVjfN3Au6IePJ7fI+JsPazBt+mzZm4O4pAaaUYUrMEdn3whIZLmJ9x31If1BDEpk3OvY3khkiJVyvnzAVYtgERYCDahGnlT4MhogMIEkaNZ9sG7xWWxtusIQ3YL7sflOaJmCR7nesFYStTJQObMTOr2aZvRqDEZZtoCZjeS+oCNr4Vzy4gbCIC19NyerUx9r4SGq4CyAHAf07TVyR6r6zX8Y+j3shRvCxRXGccyA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:20 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:19 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 15/31] gpu: nova-core: Hopper/Blackwell: add FSP message infrastructure Date: Tue, 17 Mar 2026 15:53:39 -0700 Message-ID: <20260317225355.549853-16-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR07CA0061.namprd07.prod.outlook.com (2603:10b6:a03:60::38) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ddb7cc8-c4fc-451a-ef44-08de84781e9a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: Sg9VguOk3cahjq1wXmEKNUJsNnnkvul0g0cN06+qZ+iP0FaO5AjoyXeTdEDC8gRmAc0LnT10M2LAbAlJ/sFcI2gFuumZ/XW/bBS+orchXuZpAmAycPRvBGCBYCluOaMyyz62AOXr6r7/D18WRasAXTDWZnyW7JAF69BrjhXpVv3uzH/uTqtnAqtkZ1PxzZ2XfOKihTDkPjWkKVycYzHutpGaloUSmtqYMJ01S1PESmv7s6v3PlSS9OD/1+Satbmdgnw6ScjzwPuOmFLfJ+Z3ZWNHMI+eUT57kmU9PWlEOfZUX93Jvw41ir4SiHyK8UMui4u22og4pYheqVFHanRKd+7yqU6i+fdHMxuV2oxXkl+PBqqNtOtnSGp6Y3ibRSbzHyq8WDw7o7zsrzfsA/UCtb1MIU8zi94KH019wuz17/yGzJNH9AyNX0vH7ZjNDqqdxrP0c14G+ZsxNXBWkI279qse7bukKdoURzXRR5ttmUjrCVofU+e4o4wiY9Y7G16HfI1XPkPdDEKguAaVMeWMnX8yaE8H/NXMW0FL1A9K8uXn+Hqb5OtvzmMaSphRlV7tz7WlkKvm2faHrlgtfs3HYpIGgnXkSl9s99CgaQZS5tITt+lUx0wo1WKIMhmF3fcDeN5HC1GGyOkdumySHA+lx+wudxufH8pYprdbUuKNhibgXEE7WrA/ZbNsiKN9ErPv4hTxRuZLRLjo+PbJh4RivV2jVh4EdLZ04cy94ivCwEI= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?so9aP1inJ19WcZkvtsXutB6PPf2qcwe2mEt/A70Qp4F8yl4jljzg4hrTFkGL?= =?us-ascii?Q?ttGzN0bfrei8sE3uk7WYcu6pzp870bh9ZCl/zcvdH8jSmXDLJAzI+bbyXTbC?= =?us-ascii?Q?2mrCcoVgkMBvGWeTO3XAdwJQsLkkkIRN4OdzmBcUD1GTBSMnLIzdUdPfAN77?= =?us-ascii?Q?7ODXGu25QCEdG+BzQGNQoGb3oW60Nz6k1Cqf88rHwrKS6brdNtMq5WSWGFrW?= =?us-ascii?Q?8c249JZjhjEGgObt4p56RFIF7gqy0tR+mDnAHlBEF3Q58B0CpM1diw6+acXI?= =?us-ascii?Q?lPNHoydMST4NecXrmNL0y3bcEXuZGa9SuDFyJnDT1F5p/QbZypJO0w2JA15c?= =?us-ascii?Q?9dIefHezAMEbiziK+5gIICZ3U5hBbUR0GPR4ZwHAf/5U3JBjpwe4hosQYtnv?= =?us-ascii?Q?IAWSY/0LbwbBPf+fm5SKFQe4m0ck8ijv5P7rhuqyzryTWZUgkzpUlQmyudHd?= =?us-ascii?Q?EFsNZrZcn74l+N8QS3Yld8eNDfOywHMcA+EQFg9xTr1auzde8GS3zW0wZIE3?= =?us-ascii?Q?2g30xEO1x0CEx4zlmYFI1YOb3BtupANvF19fGDotJli+mXkExJ/uedFDNS+s?= =?us-ascii?Q?sHa6qNb0t+pFforswdIpJ+iLzsOmw0O9gmQ7YV8XjGV8pAmME9nTRZ6tGKO9?= =?us-ascii?Q?p+rXwhaJFdvzsAnHDpmCY3F2r+ZAIN/FAjk4Rna7MBe87rHRF4LeprcGL6V2?= =?us-ascii?Q?Irdga+T4SmKmocxiv1lCxluRaJt+0baQxzTUwN/G0iQywcV/kjMP0rGzyPWt?= =?us-ascii?Q?qy76JgDwnZKUD2U5jS0TZC3F7cWLuBeB5JhNpW+5ftvsTpBmdBMqEPpBaEcZ?= =?us-ascii?Q?vPw8bBSQhJ/CRmhOrFrgwjE17qHR5Ynh17f6mC8swE1RCB37ti0Xoyvj7q+K?= =?us-ascii?Q?Wj/D/zKI1wC0G86oFPzckT5y18aDhWoWKo+4h+mXIoWb365DhCYJgpIavVaW?= =?us-ascii?Q?E2M5rqkSXtmKhWjkZ5tCwpJgvFyUlq7Mly3vsNLtXXMMZm/z+kzPDha6EimJ?= =?us-ascii?Q?OW27qvUBfcNbwiu4NGtpI3iCjcPPW20nhliV4MgjIzSe5LWeK8mZWDUtLNup?= =?us-ascii?Q?90RRBmoONnteTJHQHvgtKGS8OKT5CFls4CO3waN3LILT2B1wlSiu1S/CDfxW?= =?us-ascii?Q?Yu7yRICzTSQOO2M2wYUgZrICHQjxTYNbm9plVYAnxj4awEVnH/PwcX0hArXJ?= =?us-ascii?Q?7Hyc5fye147VUDtmeWSsoDUsF+bgDmB3vekLZNz19eib6ADw3Ex9IxAJHzjo?= =?us-ascii?Q?26N/dCL6P+K9BygCTOe1cEqMfnKgsf7FcD/LdK6i0HHSbX/Y38jqDW1s+7wo?= =?us-ascii?Q?fcszPFfa+ub84OyMzdSLk9GIFu+fjH7CQNxzAiWKuffZ82oF433aYCbfFsJl?= =?us-ascii?Q?pkpOAEoDnvXgnyqI8tkORGRhAJgVG94tQWQffrQTXhdcjZCxiePK2B9Zw7zx?= =?us-ascii?Q?gyD8YLKA8pSGXdBzScfVjFkO33xt9lzPrCmIZWMmhSHGLKCZiwN7ccRXOywa?= =?us-ascii?Q?UqHslMDd/2yP9b/FNaBV4L4J2Otj3EFU6NL8VuEULmwTx2Hve6JSuHauca+l?= =?us-ascii?Q?Sz6gq1eYq0Rv5fZA9JdFkEiPrUH6JfIG1dODFNww+FBBtlkXM+ruLJ7EiwgX?= =?us-ascii?Q?xfgP3BTJzg1qyydIroh3U7B6koGFF4Bpkm3J2yxIbXrRjhBdlr4s51o5w/r8?= =?us-ascii?Q?nuSjaCaEttRaCdIR+AXE4tKeHojYEWA9fimIb0ATnMhBcKdDnUqLdpka+3pT?= =?us-ascii?Q?NpdfsT6ROA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1ddb7cc8-c4fc-451a-ef44-08de84781e9a X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:17.9512 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: neRf+tGTlK2kawsn+XASeEN1mxqY4a7TyABF7xhPfbCv7rP8w+azYM6K4qiLM3+GsdFaQXFWNTDfBYUTmCfvGA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Add the FSP messaging infrastructure needed for Chain of Trust communication on Hopper/Blackwell GPUs. Reviewed-by: Joel Fernandes Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/fsp.rs | 79 ++++++++++++++++++++++++++++- drivers/gpu/nova-core/regs.rs | 18 +++++++ 2 files changed, 95 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index 29a68d6934a9..faf923246ae9 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -108,7 +108,6 @@ pub(crate) fn emem<'a>(&self, bar: &'a Bar0) -> Emem<'a= > { /// /// Data is interpreted as little-endian 32-bit words. /// Returns `EINVAL` if offset or data length is not 4-byte aligned. - #[expect(unused)] pub(crate) fn write_emem(&self, bar: &Bar0, offset: u32, data: &[u8]) = -> Result { if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { return Err(EINVAL); @@ -129,7 +128,6 @@ pub(crate) fn write_emem(&self, bar: &Bar0, offset: u32= , data: &[u8]) -> Result /// /// Data is stored as little-endian 32-bit words. /// Returns `EINVAL` if offset or data length is not 4-byte aligned. - #[expect(unused)] pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32, data: &mut [u8= ]) -> Result { if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { return Err(EINVAL); @@ -145,4 +143,81 @@ pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32= , data: &mut [u8]) -> Resu =20 Ok(()) } + + /// Poll FSP for incoming data. + /// + /// Returns the size of available data in bytes, or 0 if no data is av= ailable. + /// + /// The FSP message queue is not circular - pointers are reset to 0 af= ter each + /// message exchange, so `tail >=3D head` is always true when data is = present. + #[expect(unused)] + pub(crate) fn poll_msgq(&self, bar: &Bar0) -> u32 { + let head =3D regs::NV_PFSP_MSGQ_HEAD::read(bar).address(); + let tail =3D regs::NV_PFSP_MSGQ_TAIL::read(bar).address(); + + if head =3D=3D tail { + return 0; + } + + // TAIL points at last DWORD written, so add 4 to get total size + tail.saturating_sub(head) + 4 + } + + /// Send message to FSP. + /// + /// Writes a message to FSP EMEM and updates queue pointers to notify = FSP. + /// + /// # Arguments + /// * `bar` - BAR0 memory mapping + /// * `packet` - Message data (must be 4-byte aligned in length) + /// + /// # Returns + /// `Ok(())` on success, `Err(EINVAL)` if packet is empty or not 4-byt= e aligned + #[expect(unused)] + pub(crate) fn send_msg(&self, bar: &Bar0, packet: &[u8]) -> Result { + if packet.is_empty() { + return Err(EINVAL); + } + + // Write message to EMEM at offset 0 (validates 4-byte alignment) + self.write_emem(bar, 0, packet)?; + + // Update queue pointers - TAIL points at last DWORD written + let tail_offset =3D u32::try_from(packet.len() - 4).map_err(|_| EI= NVAL)?; + regs::NV_PFSP_QUEUE_TAIL::default() + .set_address(tail_offset) + .write(bar); + regs::NV_PFSP_QUEUE_HEAD::default() + .set_address(0) + .write(bar); + + Ok(()) + } + + /// Receive message from FSP. + /// + /// Reads a message from FSP EMEM and resets queue pointers. + /// + /// # Arguments + /// * `bar` - BAR0 memory mapping + /// * `buffer` - Buffer to receive message data + /// * `size` - Size of message to read in bytes (from `poll_msgq`) + /// + /// # Returns + /// `Ok(bytes_read)` on success, `Err(EINVAL)` if size is 0, exceeds b= uffer, or not aligned + #[expect(unused)] + pub(crate) fn recv_msg(&self, bar: &Bar0, buffer: &mut [u8], size: usi= ze) -> Result { + if size =3D=3D 0 || size > buffer.len() { + return Err(EINVAL); + } + + // Read response from EMEM at offset 0 (validates 4-byte alignment) + self.read_emem(bar, 0, &mut buffer[..size])?; + + // Reset message queue pointers after reading + regs::NV_PFSP_MSGQ_TAIL::default().set_address(0).write(bar); + regs::NV_PFSP_MSGQ_HEAD::default().set_address(0).write(bar); + + Ok(size) + } } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index f577800db3e3..686556bb9f38 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -473,6 +473,24 @@ pub(crate) fn reset_engine(bar: &Bar0= ) { 31:0 data as u32; // EMEM data register }); =20 +// FSP (Firmware System Processor) queue registers for Hopper/Blackwell Ch= ain of Trust +// These registers manage falcon EMEM communication queues +register!(NV_PFSP_QUEUE_HEAD @ 0x008f2c00 { + 31:0 address as u32; +}); + +register!(NV_PFSP_QUEUE_TAIL @ 0x008f2c04 { + 31:0 address as u32; +}); + +register!(NV_PFSP_MSGQ_HEAD @ 0x008f2c80 { + 31:0 address as u32; +}); + +register!(NV_PFSP_MSGQ_TAIL @ 0x008f2c84 { + 31:0 address as u32; +}); + // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011050.outbound.protection.outlook.com [40.107.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8972D3FA5F7; Tue, 17 Mar 2026 22:54:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788071; cv=fail; b=a8KMMy4w6ieyS4oRFNA/AaOFZQzbIuV5z8K1mrO1FwbrOOXDQUr8Sg7209n73DrG8qcPkEA2ZeBkMMtsqFf0iSOXOrxU+aN7uxn1ULdLI/C7ut+zeGlPjydhPVvbVS99aQzSaFEiDLDjtGOd+dNdsbh2PV23iM4a3bzs6Lz2Z9k= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788071; c=relaxed/simple; bh=UT+l2O4Q5nskWQRnfadZNUIf8Fqy48VF+XSZOk43zuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=JYFLSgGBK+bVYXJSvOxq4lg6gZVt5uOqBtPAtjISyL9e+e615KASkSDFhjaCw03ZMlAR1hOqxOXbcZfmPCS66YZ8wt1zp8Jdzh93CVTEosf/Dk0bc4FC+aE3+FighdyV0ahmUTekVriyHVaBXvEl3iyZSeeKXqOrDajaf+6yWdw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=NAu5wiZe; arc=fail smtp.client-ip=40.107.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="NAu5wiZe" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=j//fvtOsJZ4weD9xYNQI1poUAHYB1JxiqnPSD7zTOXy99Us299pEgFu6pnjj1HAY+DvTWf54ePEu4ZwHzvYYAEm7C4rvxMsycY9Lz5dt6JkzH6eQld0DUvP8qJVg29FjWS6CmO81Ux9SA7TNaboP2FFr0NES7URxFLTwD40HbQSHsRaIn1aY0gR/r5fMZCvF4Rt+M6zgZ8rm/0uV8SAxLxFXkMpDNlVabxnn/WNXEcII21z5mYO8b/EXClyUYmvO0rRZtLaFGJnXwUpAAiMd5jQA5Nj3g7QOkCiNeXMkulxq4eR+TlZg5Kxo4T+Hw9I31G4N+HJrJgrj1WMTxBSh4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5rcbpF2FxePTPZU5vap7/SdGKdnppb+lRZq7qpbG6WA=; b=DHwp5tCmUOBUddtIDr+JuTDdDqy0G1yLNJBfQb9qnc3+W9OEcV7C9F7/egwleEnq6Agb4y1Q2KF853x5GzVA+7HwyUoTm327clPxJxgdZ2lqDrtm3MPvJRU6xOskq4CdtYYRhSidvi9nq83uMVLkmL70g7RdgzPTGgBIGVaZpk4H67lu+hrPMAMI3fIbYtHm3AUh/UY2tWFI9yazV5bP3kEvJ3VWRsjQgZF5RP7zcvOhnE/Yflw/2iky5lM3C9XQBRjsqnQ8cCIGAXusrnxPZiFV/Ei9iJqqqkmHrJoHCe+huLFgDx/K+BGcK/mnEDR1I8uSaLh0NYICgc+yT131hA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5rcbpF2FxePTPZU5vap7/SdGKdnppb+lRZq7qpbG6WA=; b=NAu5wiZewf2umVr4doirW59alsjdNKjyBwlW8Rra6ahmipe4DwaPdzTTG3zN2MK/Fq7os9cZYdm8bp2AjfOXVbwsyfx/V8FyvyHtfO+OBpRN9kyyrw9w+p0v29nQpG6YmMQruCxCXw1sW3EsrX7DmS0cePoz7juCVWGWp4aJTqRD/ibdN3dsWDTmqB7L1q6Krk/jovPadlNNsVJ6pr/88eFgYBq2IgKrUYlK+8vV4dUMoggy18IxRw5no8FbWbStXcURjIClx9HyuhMhz9H9yJnCte0XtPXKJkZBRhWlASamVZAJmAb6Z6fV8jOFTWxPCJdve6hApnpbYdOJQguung== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:20 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:20 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 16/31] rust: ptr: add const_align_up() Date: Tue, 17 Mar 2026 15:53:40 -0700 Message-ID: <20260317225355.549853-17-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0278.namprd03.prod.outlook.com (2603:10b6:a03:39e::13) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: caa1e073-2273-4849-9d59-08de84781f74 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|7053199007|56012099003; X-Microsoft-Antispam-Message-Info: +COORZy+f3fgsYDrQCs3zxLcC1T5MvdS8sQVfKFDjNtgBWslP518cLaYnqwZOfANWHByNOV+HNkpZYKwhTpsTFLANIlx0nMAeBvn92yhGw/dyZHjtHv22XGrJhgCccKW1hQAEXN6nbSf3pfjA0CmcEAuIVOHmMAfK1g21+zFqgJVKqkk6AiwLaWyCq9YB0BhZI+QuhpbuKypbjwNw7DxhPixqCRqPtgFSl3LSPO+m4iuuMYAbNoRJgKJYcZZXM8Op4bAo15drzswVS0eQVU0n44jvhC/RrVB2c4jKnxYWBcfyxQmjHunOyybhQ7cTAXuht4VclxvGCLeVYrmbhEksv7Zox/u3CmWKjcvwPI3n8Zo0Iw39DbjVkxo8OTaoTvEHV8cWlsRIniq1XM1GIdtKSKnN9a5SVPeN9im8hKTug8Hi+7koYfDQcqBrDIOVsGHrSUMUvRAxop9UqrTjOT/bySDRHVxEmrsxtXPz/BWOjjGwIKBbIv3TQAWB9jgvus+bszjfE3fuRxmIxGKHCI8yqKTAgbQdirmPOUPp9p/hx6x0hVyPj8aYx7vQnJ1Frgof3p24HojtuaZ6WULpwZq72VL4CvjZEKxvmY8eflOKCif3kUfmTfx+MTTpQ7huLVpKfKlGoAHPAk3B84Y8d8uhbBR5fzNgF5qesyuZfk5Vu9hzOIYyn8RfMnviyKbqe9Q09s66xKpX/iFpqCHV6URcJLrwKmDjdaMF1A6LzmWlz4= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(7053199007)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?7AKqI3jYGHPsnOOgkIJCblslWYwpCS1ygYa/LO+biKJNtFvp48LjYD8MYcNy?= =?us-ascii?Q?QrKtdHAaRNYJ3ItbvjOIHIABnrWRWtXuJsH+Zl31zygmnuG9JQThFD0ISP1y?= =?us-ascii?Q?uqCbBWoMaoJ8BGO8/7rzVo39WnfYaaMQbN7bTuwXGBl4RfniHVPc+RZ/3PK4?= =?us-ascii?Q?O0KlvJ2x4hrQ7wmpF9oGoRIvMBduo/RP//0eNIrBLXgd4BwtCpKM1Z3V4kJ7?= =?us-ascii?Q?Md6Ly2OoXmifgmoR7/GYgZqF5fNPrtQg7u4v+cpkwGKZrr4PIvADgv6Mk0Gy?= =?us-ascii?Q?OLycw8cTBwutYtTDAo14uxSUfVPumxEX9KxWyV2/9t7RuDA3r/GGMjjC4YhO?= =?us-ascii?Q?WGHM9q2lR9ID1hRa/W1VLKk3nJBspL4LI/oSyQcjahlL+qBhG2Rb2aocH+bZ?= =?us-ascii?Q?jgj0pmm0IT16lS/FxEoXphV7tdxAn+msY5ThSM2HfqDIKGZdOLJWoAi9l3bI?= =?us-ascii?Q?mWlcaT5fPEbH01UwBZAzi+c2sVyRQYjXQKtHwHxvorfqeOu+uo1XQ1X3ijBy?= =?us-ascii?Q?ROk5ztwktItyRSjAB0/V5m6xyoTvAsojSZ039V9YqX1wBt8+gPfOSrvFGP2q?= =?us-ascii?Q?cftG8YM4VOaCNzEN3uVMlXohZ18u2kEsdeG21WNBTAm77TyI9PMAuVObrZ5R?= =?us-ascii?Q?TIv1A0IgcEMf7qaFAuXwSaTx/wa5REczWCxra2VwyDKFxRubE4YKRzHZdIc4?= =?us-ascii?Q?VkXaf418nnJeAz72+xgQnaVZIUyl/8IBjtK2yl8AZQi2hYzuxd2aeT3drBbu?= =?us-ascii?Q?GTiAsZfydiFWJBhOyPiXrnXfTBLKKaItQ4EfRFDWpBT1ThfiMT8cOnLi2bHQ?= =?us-ascii?Q?8+U4bh2FH+4dYawCQvvvhR8RBVnF9LeqvX1PssWozzcrPdGflzONGuy2XQh8?= =?us-ascii?Q?5mCI8xKBt/cAXno3n1eRfFSDELlHFlSLkPi85OlWKhXbOpeiHiqlbkTGl9SY?= =?us-ascii?Q?+3esyYwOmxbvt0ZJf9MUX9puZLcLhXS3xNIYI3v4wX8qdbqy7f2egggw4LTS?= =?us-ascii?Q?Xt6NMuNjCunLLmCM9CdxBgxd1SKm6YWen/jF6TsdieLvMYxqg4uxJZKA2XGe?= =?us-ascii?Q?GoeCcNif7P9O7grnzxY4nJsf1iKBtzqpKnvoGWwCt5o7oRWKLLBIBJSSSGQA?= =?us-ascii?Q?UIGpgYKh51f5UtsqYq6BO3E3H4gRi8BC6sl2HeNf5aqsTD7EA4CaghhfKHtb?= =?us-ascii?Q?kSF6zItDMrz96OCt9HAV8yZ8uX0NbU1N0YzR08wdpA60aQA1ASIkNbRHHxBO?= =?us-ascii?Q?fdoHktv3XibAlvjMPY3QZUtEtjiuwekxeYA/tMnk7C12Hp5oVkWNVzYNG2+i?= =?us-ascii?Q?kGaK9U9a8wlQlZLP/gXry7iNDl//qI9LV6il3KbuKwOhKMBCqrAYY34LFmf/?= =?us-ascii?Q?uNMqc989JTCcKIV01uF0Ev1OwIz+qbzQCdEiQGFkiC2DlTonswdLwkpk5iGD?= =?us-ascii?Q?4rbVVsL5dJ4LSctw5GVnPZnxsQdNJA7d4hcmOCw2rtLFhcmUh/KQDdEX93tm?= =?us-ascii?Q?elfswQgg+0UB5CC62tZens5f27nybfo1dcw1iVs2eNGNhchb4LwDCl+8FV9D?= =?us-ascii?Q?pGeEtz2+6/1jXOeRUs3mKpD72pO484sFmSJCHstvrKXm4DMCPPWqvR9UEhtD?= =?us-ascii?Q?Jp1mtuP2W+xifDTWdgzETANGpXakGWumaDW/D0gp1kM7PUWwT8oavLI+FeTZ?= =?us-ascii?Q?37A+4gG0rPa7dvL8yxiJurIOk2kdcUDdYUKdoFlmMudXp6Ew7J8OSYt+HZgL?= =?us-ascii?Q?X5kYKoMFVw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: caa1e073-2273-4849-9d59-08de84781f74 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:19.4424 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3mdgZNYoDr5sVsTEaa6y25z3g88MzQa2AJO0O3sf8KTP4SBlHIlL8XaFih0XhyFSZQfSU95JVaNeUj67rNG57w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Add const_align_up() to kernel::ptr as the const-compatible equivalent of Alignable::align_up(). Suggested-by: Danilo Krummrich Suggested-by: Gary Guo Suggested-by: Miguel Ojeda Signed-off-by: John Hubbard --- rust/kernel/ptr.rs | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/rust/kernel/ptr.rs b/rust/kernel/ptr.rs index bdc2d79ff669..7e99f129543b 100644 --- a/rust/kernel/ptr.rs +++ b/rust/kernel/ptr.rs @@ -253,3 +253,27 @@ fn size(p: *const Self) -> usize { p.len() * size_of::() } } + +/// Aligns `value` up to `align`. +/// +/// This is the const-compatible equivalent of [`Alignable::align_up`]. +/// +/// Returns [`None`] on overflow. +/// +/// # Examples +/// +/// ``` +/// use kernel::ptr::{const_align_up, Alignment}; +/// use kernel::sizes::SZ_4K; +/// +/// assert_eq!(const_align_up(0x4f, Alignment::new::<16>()), Some(0x50)); +/// assert_eq!(const_align_up(0x40, Alignment::new::<16>()), Some(0x40)); +/// assert_eq!(const_align_up(1, Alignment::new::()), Some(SZ_4K)); +/// ``` +#[inline(always)] +pub const fn const_align_up(value: usize, align: Alignment) -> Option { + match value.checked_add(align.as_usize() - 1) { + Some(v) =3D> Some(v & align.mask()), + None =3D> None, + } +} --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012058.outbound.protection.outlook.com [52.101.43.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C15303FADFD; Tue, 17 Mar 2026 22:54:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788072; cv=fail; b=YlLd9W2uaCN/guO/62I/tjdoK84DRKtbiGS+GwmVrZVuZVMKIgq8Fe3YfkDwq5kR2D4BdpNLQeMBSpJ1XHLodYIwgRbKODi1nUf5mJBLaKvnjVTSc+jXUlF9MD6Dpbg/xcc3I3N6kl61YBCOjL+uBMhxDzNnlqFpe8H7lQvYKZU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788072; c=relaxed/simple; bh=vL9HN7MusoVWBLbqmQwTxH/pKiP0j46BQiaAletpib4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=HEKuM6rcgJdOX1DHJCj4VduxZJljeteezK/1kymHFWt/aBtypK3rdCjsfeUAyxkL8wEYXGUurxZHhBSrIsFNPhGlhpzRtDapzJ2N16GpeiO1GrY+ecPsGf8hnRmczx/EmN7S1/Zn9f9WTn4vQRYG7Mz2bIN0EwrkFI8Q74Fdids= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=RAA3fny5; arc=fail smtp.client-ip=52.101.43.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="RAA3fny5" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=RlRiHdosRC2JQcntwMLO7BHoq28wyaHiqOkytGQQ1zgk45mLGIMan9X4+5vZ+D0wEd/XdGhPPk0fT6i41/urMsg9yQIQFollrjnmWSzmkdTdr8eMehfufI3JREhWakh2tz0cO/zpTL7Y8Z/4Bbkoi85olGfZe+3gNMj8ImGdaE+uS/jlExA+svJp1QyTa4Tt1fGfVpQtBzKlaJBuWuwGmDAibYceV6L3dcR5nC0oFlVuij6B6BHM4UCas/I/w7pZ35/9XE82E3Jer2waVKlTwTjAovxvaPDelJteBfIauhb0vQnfiEZyD9NnrHDl9Kid9QFjoCb3wDe7hSM3BVlMMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sJbrdlRXmMxHiM1B8iOy9zGroCqW0VN7hNJtzr9a3hw=; b=EloG94YYWP0gBh7H3LjM/IcNzWWYgGx4oCUOQ0ynpp4+NjQMunCFvodEQ33Zzu4O1UwajgoMj+5h8tGpTf5GthL1cMO2H2Z7mjnoLlEGa3h65fPxtlM2pyros9RSMC73woubIkfpTEX33cZqhw7Yucx3+BNyZtuB9d6zJhzdllU87x5b5VC6MuVF5lQ7Zo+hK58JAYdLsEBMyxHR+js5DZQ8tzwjqnr+4YGKRKCyGLSJ84x65pa/stXub2Mpudzyx798A3KptobAxdwyk2HLgVIfcQvIL9+tV2a+rlow6HHKfql3kXlGnYHOLwLlt4tsUu34k1JznhLbPSursr7grQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sJbrdlRXmMxHiM1B8iOy9zGroCqW0VN7hNJtzr9a3hw=; b=RAA3fny5tnqigVbhgkR9Kj0noGVHVsNlWcP4EOM1TCT7S4B8JTA2QKCPMCv3Crm3qlIfZQT7sEhRy/Zs9OdN+H76klWVjbrDzrBOEWVtpWea/3/piivTlTBXU1T5o1K8v96fPzjI8IPV8DQnT3XvznK+f3VGqxUGpChaKaQ1TkoYbB07uG7dsayzOTwkRSE94BOHfD+ND6i29kLm7QCyFTfDUHIHZmeRDDNalze4Et8owfKEe6TmeK3YJCxJ4twnrEiLu/0S+jZgCO70NngbSspM4WLmtSJm9eKmvOQL92sIR35axtX7R1oY9xSy5T5w20C3yumqRZFdaS/QCBxSGw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:20 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:20 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 17/31] gpu: nova-core: Hopper/Blackwell: calculate reserved FB heap size Date: Tue, 17 Mar 2026 15:53:41 -0700 Message-ID: <20260317225355.549853-18-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0298.namprd03.prod.outlook.com (2603:10b6:a03:39e::33) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: d0688f6a-9ef0-43bd-997e-08de84782029 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: /vtQvMy3BHj8L4qhe6snzV5yiMpV00/cywGTrw4UpQ2nqggP1f4D/+z8Iw8OCUmlnOsgOPPaAmWS2IoEeAyvSjBrViWICPmYuPYOlyQOVWb+doPhFGsUfyIAobVfJ1ZN64HC1QbrBA5FV/8qRAsE0WR8auSIcSsVRljHVOiS9AF36rF2Fzuo02t7GJceap/VuFiVuxwgvgDGvwIREuwFpYEBSZgtmVwfCWSXW5uiclKweuTwiY6crILSdrhTvXC5QI81ZkEEoM11A3qbeJStV4zFJUOn/yQiIBCv3iPa+IwFCH/MDk2bbeYs0hEEMbByffby0JOdQLMNFJ5a+EHrt3W720eahDAZo/mhM0WmHucwdSrTk09x3Lt/kzjd0rM9pqnvIn56rcvuqJ6rgaMEJnD9uB2kiKl4SpOiNfH5EtttV5B6mkNZJamV7IP+z6UKU+zeKoKtMC9tYR8PhLhUxe8C2PW2XJ/dut9Ad0SLtDPI8rF134uHbf2iTxuY0+iYAwOTbPTrMtWaydMSiveDTu2W1cPz8R57YcFDaT4Xd6bX6NFCRLoLy3B1MbzFplFIa4xKIt2iTRFAir6Dy+kHgeDB3KyYwTDlYMWu5C+UFCijIlHfO5DsrxMe60mB3nI6ttXlxyIC64sF9QqzwkJb3vpT0JJlIa0E06N1B4w8H3fIBm+lHZNpyZBHMO+vmpJrxwMQHFs5HoltDKrdTplRoecjktyAy9LQqnVZwUuviIk= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?i7gVB9i9NUemf2yKMUtkI7XNvMzgNvQUXUybZLpyyJhtCW32HoDNfDYamz3x?= =?us-ascii?Q?ep5vr2Cj76ThY5kGqZOKdQoS/uVeGFjklTBY9HEAJQzEakDmrYQYO5Od2LVY?= =?us-ascii?Q?pvosxA5fw1wp6wkVamiAWT99XH0EpDAT7NQECCMgGFBPjMdUv+FyX5TRAvsF?= =?us-ascii?Q?M2p/EC5dOL+LDR3JaXC5KFqEWyq45ld0+p0sJ5u06BXtPi/YVK+tMKQO9sFn?= =?us-ascii?Q?81sebcNjglt9QcsktwydQbv5PmMEKHtzYchptDfMUh6/RaLK559ldVrCqE/3?= =?us-ascii?Q?x0zN1yyk+uo8bNaIeKg8gIjVhM8SD6wDjN6Q61B9DVEIv1ftmKicphoT5n2w?= =?us-ascii?Q?gduQv2dik8fsKAeUQ42ytB+R2Ky/CNqeimhcvlv2QBZ9TS9+o5p4w6drtldO?= =?us-ascii?Q?r9htsYfVLufXrkpNhwA43/KR60Hvz+tlSkhFQw9SB7lXscxchNLl2evScOSh?= =?us-ascii?Q?FNkkkbT6vN3gqJCJz5OUnNNRSiF7vQpc5kHJQ9gxkuZrmRPpWndRObYMF5Ce?= =?us-ascii?Q?h3t4ULe2+E/blNvrGgd/n8LKlb2rjAtrE2VjSscAB5jLqOXBAOKux/NvmE7D?= =?us-ascii?Q?MEujTK3S8wHua+6OFFJcQ+Kef+rqXEnp+CQ8xkArG8MlUf1K9Qklc+BKEVNK?= =?us-ascii?Q?K6qZqzPAShq6rJCmOhwQPIdJ/N1xslPbFmOTlnXUs6SJ640Rh7/snkIE8zLI?= =?us-ascii?Q?VAdw9jrkwDCeQs0j65njE34fXzo4s631rvg6Bh7DNyzouGZN1LfXoamkiXEW?= =?us-ascii?Q?PZ6XR6jgmUWGlTOBvrVZo/JQvSbvFjrdoRnLHPHW3sCqAu6WfeLsM1H7MwzL?= =?us-ascii?Q?3bGLXcynRWMhiPBGIz7BF9FLN2EcM1aiH9NBcDnjz6VhUUZmR8Pr8pL6VtMl?= =?us-ascii?Q?Yy/3G9clAFJ/K9N2wMDQOY811bfX7EJx34VbpZO8qYqU0cXKojD1AwL3A+gv?= =?us-ascii?Q?tB0BGATuucIHYpCPlp59WmqdzFbYl7rxe7Uv96fTH8RLyUkJRp0E6lN+xBmK?= =?us-ascii?Q?enQ0WX6cSzbN7GqS7E6MNVkQh7E1iyLY84SG6FNspnG4fZugdK5bv5/RrpcT?= =?us-ascii?Q?A6r4K5RPaPWIfYS2IvtMQ7ecuZPLwf4dK6I2Bjav49XV89ScAC9lgUs2lm4b?= =?us-ascii?Q?z/Np9twHBOkZeH0nf+x4O/nJRNtEitqG0jNMXINTeT/utD+Aaae56dfn23wD?= =?us-ascii?Q?Qfu8nJJ3WzOZ8BYHYJD1gNYHv9ZtaS3n25mz2k1s1eYdeCBdioSaK1kkLTA0?= =?us-ascii?Q?3lKOzVvwPmHWdiEty4IJ8l6XQqc+9y4RFDEQoVJeTbFgFUd5kJfH8DRnLTrd?= =?us-ascii?Q?ZZDQYrqe5LQJDvYJdh7iTnTlyC75JypkVUm0opUxkvbBsjgR/fTsf14jhliv?= =?us-ascii?Q?sIJKl6zQVvJJq9troAXVlGY+lrOVnh+48iQZDLJyHCAiCSMFiaYIFUW45jHk?= =?us-ascii?Q?+Cf+KT+LEPBlJK6l6Ge0ihcN9wQlowizz/mQpzC6OIj9ySsPBz/rlsb75DDU?= =?us-ascii?Q?joqeFFa53ITucEW+x36SsYt37tUKN3FvQ3aCOoL6PVHeEzwOoQTvBDlRdSNq?= =?us-ascii?Q?TqozXMZcSpzDETK6ld0FcwziYckFnhKN0SYLMOgsiYL7d6+VtrQ+hB7bWRJF?= =?us-ascii?Q?XtJ2NTEVVx1l3s+1m25+0hU/htTXtueM7dnzm6KR2V1Y6nWw4yU7SGhatcT7?= =?us-ascii?Q?QDAx/OR1dD9wLvgYkwoxZYNT+LGp/bvDAQK4+JcHw8OyN6dc6tphSdA3Agmm?= =?us-ascii?Q?7pvUxPKehA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0688f6a-9ef0-43bd-997e-08de84782029 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:20.5445 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: QKzZuQN5RFty/Hy8J7RydIGHcfTikDUOHA7vW3o2pQCTfsnO2bxFNSeT8N+cBeq2Jlb2fiW46nPV6T6NwIQEMg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Various "reserved" areas of FB (frame buffer: vidmem) have to be calculated, because the GSP booting process needs this information. PMU_RESERVED_SIZE is computed at compile time using const_align_up(). The total reserved size is computed at runtime using Alignable::align_up because it depends on the heap layout. Cc: Timur Tabi Cc: Gary Guo Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fb.rs | 8 ++++++++ drivers/gpu/nova-core/gsp/fw.rs | 6 +++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 6536d0035cb1..ffb996b918f8 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -10,6 +10,7 @@ fmt, prelude::*, ptr::{ + const_align_up, Alignable, Alignment, // }, @@ -270,3 +271,10 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw= : &GspFirmware) -> Result< }) } } + +/// PMU reserved size, aligned to 128KB. +pub(crate) const PMU_RESERVED_SIZE: u32 =3D + match const_align_up(SZ_8M + SZ_16M + SZ_4K, Alignment::new::= ()) { + Some(v) =3D> v as u32, + None =3D> panic!("PMU_RESERVED_SIZE: alignment overflow"), + }; diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index a061131b5412..92335e7fc34a 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -26,7 +26,10 @@ }; =20 use crate::{ - fb::FbLayout, + fb::{ + FbLayout, + PMU_RESERVED_SIZE, // + }, firmware::gsp::GspFirmware, gpu::Chipset, gsp::{ @@ -255,6 +258,7 @@ pub(crate) fn new(gsp_firmware: &GspFirmware, fb_layout= : &FbLayout) -> Self { fbSize: fb_layout.fb.end - fb_layout.fb.start, vgaWorkspaceOffset: fb_layout.vga_workspace.start, vgaWorkspaceSize: fb_layout.vga_workspace.end - fb_layout.vga_= workspace.start, + pmuReservedSize: PMU_RESERVED_SIZE, ..Default::default() }) } --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011050.outbound.protection.outlook.com [40.107.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 548773FAE0C; Tue, 17 Mar 2026 22:54:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788072; cv=fail; b=FZqUwlLNGmv0VNMg23KLCaNvKOlgZ6mZXI3+l9b3W/88vXeBgH9H+ebav8UA689u5Re3e+XnBHWDKanvX3kLaZ60ezyRJdT5w26MPMZ35l1Em4LNIQmcOC/u+nEOaMzg3Spz0KNfTKl1IFbfQPVbdE8SgZG1rXRJZg4zusVocTs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788072; c=relaxed/simple; bh=Pn6SR0jN3mAxFJgBBxyv5jD0/twOcH94gh0hP/gaLRA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=HvDPyp0QQXkmLKXL01GWh/A6olRrVpLmPF+imCpmC00eN+LxLyrAQNukQe/c0NkBRDRMRgtixeGXVn2UFZae5tYKlJquMlgIQQlqDQl5iImOPjjjc2AdXVSMt1uADgmtfYz5UvUPBPf8hq0iuJhHDQjfepXEOrb2weKKZwxq+gU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=gvi2vbGq; arc=fail smtp.client-ip=40.107.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="gvi2vbGq" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=El07C/2LGUImSUoZ9x2kQU2tJlRWBKRmGmL778DXk4LWnrf06ikej0NyItDmEmkGp2R6XIF+zMD4MWj9wgTL2rFW+7C0xAutxeRCBpF5zYtPxP3NjoVRIzb8optBArcIIVHLy6ZCwrLHK1HY9Kn5t5xFDQYWIMNpel/JvBxe6M2KCYJ/PJ8nyp2xCzXEb84CE3OAD0Bgo93/ZZhRD/yi/Cp5i3g8q6eyWQ7rEblfYnb2PqWORnVp5U6hYPxtE9fBsM0kkU/80b4AxVYUvWjrwsBRpXXrFH1UsfxmFKPv3OpbhUJyRyMDTH3MumZLmAcatERd/7pSmfnNMMgdHbLi2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qTR7KifvWWq0naxwp1/whdR4T+68lY3H98BeBhsCQmY=; b=VD4asaqOSNz2NiU9/4RaJwGvJo6aqU0rxBCCH52TK2MgsgUmc037tb1bmyvBm0dSdamVwsRBzdQzlK3Y8A5+Nk1mW9URNOMobQzFmslNSmpgWsE3TBJCapkBxOTMCopkzV3AMrncpLVUanVPik+OuWToucJjn20PqtLdRd5L+AQU98efa9rBhAP1+Zh92X2ihPtdRWyV0gVtX44rTA7PVScdvCtKUE/36wTP3NHGGp7Kjsv24T7r2Xv98z5FW9hXiyL7wUpyToDSyx7MN9elSrwpgQOOu6bl0UMXFnTPRq973cihxD0+VIYziUv1tdT4FwrjjQMPCAHGrnZPrtk5hA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qTR7KifvWWq0naxwp1/whdR4T+68lY3H98BeBhsCQmY=; b=gvi2vbGqxvUVxwpFGUI5fgTjtcxqhN4cJuTAuH/auAMOZ86h2C46TwTthS0hgh4AWpMLT26O34yacf+aQW8taEt1TK1BX9fVVw3IaX3ACa0OcZR107diSAjvdoucY7oAz+kSR+dBvE6yyXY4H7OE9x0lyu0Ow+oSorTCB/zg6MD5TLmEbuUT55oKE7NTuPyQ0Pmr2AMftsDABszdJ7/cDnyaUjHspvWZrQsP7R/ar2BpJdJ5Lcr4ddU759qV76T47COZo+DHePBjcTtBupm3GhrIjo3Grbo3exVGxyTREab5TSVMC+f7sVZIP/hhPY5gCs3LJoa/x+B8eV2JMkyL3g== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:22 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:21 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 18/31] gpu: nova-core: add MCTP/NVDM protocol types for firmware communication Date: Tue, 17 Mar 2026 15:53:42 -0700 Message-ID: <20260317225355.549853-19-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY3PR03CA0021.namprd03.prod.outlook.com (2603:10b6:a03:39a::26) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 7edafd4c-44b6-4a31-dc44-08de847820e9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: awcnd0Jkhl+QNrAHzlDY2A7kqLCFr7ihGA2auUtl8ycODIxJCCO41fiFX33FRWbIxs7cU8exDz679hDrVEb0O7k57v/Gmmt+ouoks0bFW9TtBZavedB8VwiISTisoDzqo4tehnD7N7MFNiDqUHd7AgS/b8STT3XZuBkU03Ca5oqBYAALtf6QCnsAW3bCsRJOwWjlle0PwFUVKtzMubbiz/FyG4b4YSUs3ZumS1cMYlgnijle0hZcc/TIUIrgWFmSUb1KX9Pu8+vDD2hllLOhkOWrl9LcmY7EMwA+2PHaUO0uObXgWmxvqexiILQ0q5iYI24P8loQ8i+xnDlWFWJwevvsVPpZ0gj/dU3HNNmCpf1rkYor5DhrwwxnA7iLsmnM4OhHirq9NxgjJVvVGcTnnzOI1v0HrNPRaF6RFutBrv2put+P9FALRLw1C3QeP0PI2xk+nIhXAcxhIFW+RQRSOgm5gEk9iwMjr7m9OC2i910j93HMHcwbxlxK4uidnvZt6vGFsSmiDcmG2HdwmZ7iDFsfud8CIdo+UYs/NnghoxR/iRZAd6RgEu7bha/wp/5pW0YBMFibRXZqOFicHE303UjptNWjlIGtDGEUN6M1urMDgk71DzV9hpsxqIVQ1ccH6X70YPSTHRz9DDF1Qv8FaUf1/16dp2plTciu03zGjA1WEEzElS5g32arTZEorvMBe9VgthNCVaGod0KxD+lLvD+LIEaEAlBujtKPtlLbuEM= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?tnNPHk893MfgVhGUSKUAAATCgC/iv4LCmwjA136PJawFbAKW0AmnV5yn1IUV?= =?us-ascii?Q?QkHzGe5ZzBg48xTNLB+gCl7irbj0d5gikkovqklx910UbBSui86UcJuCbwx5?= =?us-ascii?Q?E+0Bc9Lq/7gqmveVs9NX60t0S19pirjfepBSU0ZzihVyrQVaNd2r7niM5qC9?= =?us-ascii?Q?0lnd3e6kYHeVblkJ2d7D8doROWSLvXmzQc9Qbnnpha/nwcluQ3aqaYqGZrUN?= =?us-ascii?Q?FCDA/GkSyY3n0/eByL9G5sKIc+mvf3LP9CGauKG9e33d0obN4V84mjgerNPc?= =?us-ascii?Q?9sUsx45QrEHoSN+1WJIrOfm9+VKrJN/yX1tvNWscHGxP2IZMlDedq7sRFwWC?= =?us-ascii?Q?gA0x3ut/1Lv13Mxzy/IfzhfoY5Rc20eh/uv4J8PRBZfv+QF6tgjkN6CovMKL?= =?us-ascii?Q?/PPNYqpqoePodLenh/jmYLLCKLB46gszGNiPk2pwRQ5uzfKFRbbhj9fzOsbd?= =?us-ascii?Q?CTEQ5ZXwFh3me1w/XaskJoSgRXhqN9tkwOKFmwvzXrBf0YFtv7HMc4ZOvMdH?= =?us-ascii?Q?dbpURDks4XPjqM8WlWtQG7KDSLkSZjI5i0CkmJ68qkPgAsOl74MpsRDwtAGX?= =?us-ascii?Q?knslz8GKyVx1TvutHzlSPRFqZDWATiJLDRaJbUb3d9FyIdsXV6R8AaO9wmYP?= =?us-ascii?Q?i6VG5UmwUHUDZoSZdHsSFZk3NpwAfjJwlFpvRf8z+RLW7yLDjAUUDrmuu6tb?= =?us-ascii?Q?ycwJeN+ioY+L1QuMIOI7WJP2CsaAf/oiGyQt/PrhSpUko0IesPFfv4XOC7zb?= =?us-ascii?Q?ifawZThzuuvfVjPk5vrhN8Mekq4PZ7qBVVCzY/pJxyC5br4oUfDbXBhKcZ2M?= =?us-ascii?Q?MVAOO4ZRnsbx8EPQUXAZGSBbAoXttCVVq0dLh183iDz/1F51hwbdd9iLrbdh?= =?us-ascii?Q?Qt6cty5RjcOP6oIEOLbTDdLijC4c+8roFjwA2grUWPNn3FF0vHuYjKKMXFet?= =?us-ascii?Q?NILgFTpNuQFJXqzJMbZjK42xr+89Ew8qRjZVVrUzwePxU+mtNRLouFMBOexx?= =?us-ascii?Q?LYwEx6nzFsPfZ27yasX0GHqqDy0BaXGq4xXdDMafLGTu4/n2Eskj8RqOj/Dg?= =?us-ascii?Q?FNF5s+i8TsTXiQM4iBXEoYcvNKjFcW21A87bdxUl+KzTz2wTvIL+0S05uFrC?= =?us-ascii?Q?0ZYSW4IDiFJ7N8M/k2V2coOsttorGYky0dFKoZaUz5RRQyyQmTlvckI5F3ij?= =?us-ascii?Q?XntI7/V1Rt+/dgcEU2Rvx9bBRAGBQYfruwQNzjt43pDmzqxcTKdfpUO+MjRX?= =?us-ascii?Q?C0zhisLmBKSytccCFR6uMvT9m5BflpMHcq67C5sAoEEP9iSEhFiCfciiOS7W?= =?us-ascii?Q?7QXdBncySOTtnhawQoeHIHLqC+g3JYVwWZVnB7pt9BCXeXFpIK4/fsbR5+Hn?= =?us-ascii?Q?Wwqjt1ljNIYX1IKwCaxA94b5ZbyuQlS1IsmolkAkOozt5rbxz2c3xaxU5d0l?= =?us-ascii?Q?bxQGLd8FOkYPutjNZdyuvEbh1is0p071u/qX9Ah160ZNPfX0kzpr1toPKxEF?= =?us-ascii?Q?gBSBAVJ6rSOhGCMWy7eLC+DFGjP/I7lsxUjSCNGV8HyFRBD/OvQdZqSnYL+p?= =?us-ascii?Q?PFv9PbU8loV3oI4o//N0TEpsQUorgSQaXoTfGl96xdfP/zw0Uy1cIQvxtS9t?= =?us-ascii?Q?zXbu2c8sBMM1a1YhluFznQS76qap1xF/fajAY68xyih9wMwGVi94vwpF6p4A?= =?us-ascii?Q?B7jDEvWNpqd4GLIR0iXtCzMVjhf8kdGW6yUjINbdLyUfOzjFHyQy2QsW0LLg?= =?us-ascii?Q?qve5QOI+1w=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7edafd4c-44b6-4a31-dc44-08de847820e9 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:21.7921 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 63o21Q+mfMqbwOp7X6TTeifAuICfcXJCEoP7bi2apZ+qln8v9ctx+yuZfhVBWShgivSFPGWxa/SrTsVE4BBrRQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Add the MCTP (Management Component Transport Protocol) and NVDM (NVIDIA Device Management) wire-format types used for communication between the kernel driver and GPU firmware processors. This includes typed MCTP transport headers, NVDM message headers, and NVDM message type identifiers. Both the FSP boot path and the upcoming GSP RPC message queue share this protocol layer. Cc: Joel Fernandes Signed-off-by: John Hubbard --- drivers/gpu/nova-core/mctp.rs | 126 +++++++++++++++++++++++++++++ drivers/gpu/nova-core/nova_core.rs | 1 + 2 files changed, 127 insertions(+) create mode 100644 drivers/gpu/nova-core/mctp.rs diff --git a/drivers/gpu/nova-core/mctp.rs b/drivers/gpu/nova-core/mctp.rs new file mode 100644 index 000000000000..9e052d916e79 --- /dev/null +++ b/drivers/gpu/nova-core/mctp.rs @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! MCTP/NVDM protocol types for NVIDIA GPU firmware communication. +//! +//! MCTP (Management Component Transport Protocol) carries NVDM (NVIDIA +//! Device Management) messages between the kernel driver and GPU firmware +//! processors such as FSP and GSP. + +#![expect(dead_code)] + +/// NVDM message type identifiers carried over MCTP. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[repr(u8)] +pub(crate) enum NvdmType { + /// Chain of Trust boot message. + Cot =3D 0x14, + /// FSP command response. + FspResponse =3D 0x15, +} + +impl TryFrom for NvdmType { + type Error =3D u8; + + fn try_from(value: u8) -> Result { + match value { + x if x =3D=3D Self::Cot as u8 =3D> Ok(Self::Cot), + x if x =3D=3D Self::FspResponse as u8 =3D> Ok(Self::FspRespons= e), + _ =3D> Err(value), + } + } +} + +impl From for u8 { + fn from(value: NvdmType) -> Self { + value as u8 + } +} + +bitfield! { + pub(crate) struct MctpHeader(u32), "MCTP transport header for NVIDIA f= irmware messages." { + 31:31 som as bool, "Start-of-message bit."; + 30:30 eom as bool, "End-of-message bit."; + 29:28 seq as u8, "Packet sequence number."; + 23:16 seid as u8, "Source endpoint ID."; + } +} + +impl MctpHeader { + /// Build a single-packet MCTP header (SOM=3D1, EOM=3D1, SEQ=3D0, SEID= =3D0). + pub(crate) fn single_packet() -> Self { + Self::default().set_som(true).set_eom(true) + } + + /// Return the raw packed u32. + pub(crate) const fn raw(self) -> u32 { + self.0 + } + + /// Check if this is a complete single-packet message (SOM=3D1 and EOM= =3D1). + pub(crate) fn is_single_packet(self) -> bool { + self.som() && self.eom() + } +} + +impl From for MctpHeader { + fn from(raw: u32) -> Self { + Self(raw) + } +} + +/// MCTP message type for PCI vendor-defined messages. +const MSG_TYPE_VENDOR_PCI: u8 =3D 0x7e; + +/// NVIDIA PCI vendor ID. +const VENDOR_ID_NV: u16 =3D 0x10de; + +bitfield! { + pub(crate) struct NvdmHeader(u32), "NVIDIA Vendor-Defined Message head= er over MCTP." { + 31:24 raw_nvdm_type as u8, "Raw NVDM message type."; + 23:8 vendor_id as u16, "PCI vendor ID."; + 6:0 msg_type as u8, "MCTP vendor-defined message type."; + } +} + +impl NvdmHeader { + /// Build an NVDM header for the given message type. + pub(crate) fn new(nvdm_type: NvdmType) -> Self { + Self::default() + .set_msg_type(MSG_TYPE_VENDOR_PCI) + .set_vendor_id(VENDOR_ID_NV) + .set_nvdm_type(nvdm_type) + } + + /// Return the raw packed u32. + pub(crate) const fn raw(self) -> u32 { + self.0 + } + + /// Extract the NVDM type field as a typed value. + pub(crate) fn nvdm_type(self) -> core::result::Result { + NvdmType::try_from(self.raw_nvdm_type()) + } + + /// Extract the NVDM type field as a raw value. + pub(crate) fn nvdm_type_raw(self) -> u32 { + u32::from(self.raw_nvdm_type()) + } + + /// Set the NVDM type field from a typed value. + pub(crate) fn set_nvdm_type(self, nvdm_type: NvdmType) -> Self { + self.set_raw_nvdm_type(u8::from(nvdm_type)) + } + + /// Validate this header against the expected NVIDIA NVDM format and t= ype. + pub(crate) fn validate(self, expected_type: NvdmType) -> bool { + self.msg_type() =3D=3D MSG_TYPE_VENDOR_PCI + && self.vendor_id() =3D=3D VENDOR_ID_NV + && matches!(self.nvdm_type(), Ok(nvdm_type) if nvdm_type =3D= =3D expected_type) + } +} + +impl From for NvdmHeader { + fn from(raw: u32) -> Self { + Self(raw) + } +} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index b5caf1044697..3bd9b1dd0264 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -13,6 +13,7 @@ mod gfw; mod gpu; mod gsp; +mod mctp; mod num; mod regs; mod sbuffer; --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012058.outbound.protection.outlook.com [52.101.43.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0B203FB050; Tue, 17 Mar 2026 22:54:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788074; cv=fail; b=nNWVAkjh4ZumVpN73A95Fh3gGK2780fvFadHv/9nAGLui8QHKmTIu/XkFbOqqTLOPI15gNOcyigSofgwj9aNoFbyokOx/NLGKkqfFEac8QLGxuOi1u8drWV3gQG6e8tQOycuKTgoTTVmIvo58ByhRaLoS5tj5kiWIZ9e4LJagdw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788074; c=relaxed/simple; bh=tZRZXPzK09hUuMKljfrFU6NkOLw9n7A5rnyQDFgd6ec=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=fVF7G4kRJ1AV7uhYYKqkv+pIQjexUg6/HABwAjG4G8ARNvNeriR/LyyMlqRTPjQi18Apnk3KEbNymsQQSD2Ffy5jmANPo82R87lwQ7bNoGzaO8rAOnIkoEA46uoB5iI2NQNupcZarVEDRwBur2hVyYtOzX0blNfuIY94hksyvPk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=mfi1TzIx; arc=fail smtp.client-ip=52.101.43.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="mfi1TzIx" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fndXKBYBNrWp4k4IYep9zfAGRKz3UlMp2QopdF48GSXmDGZsy4UrjNhQ6JwcdpwcYZ7AkcdAtQNj0BJvJ4oXFqEJ8TTpfdjDGPOYc6fTXrO0HALHNUZR51viNiAf5shAWBTrD/lRW5uVTlIVkdhxpGacUInGvhkT+niUEtj+FysWDtVJLhLQj/x+a4ReRKnQP/gY0+B/7EnpENvnRGOi/uxf/S4MZgd9C7OjbF2dQQTrZDJlP36nrqmZhAq+6K0VNFvJ6ohfahc26pYrUPJJbQzCVhv/GGqUO7Ck6tl/ecV1jcEQV2Yz2YbXL7C0ol4aZGS1RBq44A4y9hucwycgpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6nEoOdd8HVZSqOMuMkQGsMKUm77Wr5CSTcWJO/q+f0Y=; b=XClXVB/nhu4fwvVlasneoSXin8Vx96Ubr8/XI2MAj9L68PbHt/Fvs806Jhcw3J4R0i5nV9wE+qs5R52x0N6BpEpJpMABZEcw07QNN9s7Sx7sBndSQaE79ODAb20BPiOSt+X0XuoiCFIngy1tYPOwPRO0VymlHQxzpEsBem9+FTap/7GwCcNo9PfThA1q+IX+eE9mPKj8OfTDDYhb/3LicEiM1fQF5mrE8eMwNyk3fw/2S1nSXxjHzRRXBGEmKqYF6UHLjWH/keVLg0rHoBFUpVoSfvsASRrSNiA7GjvlIYJxwjssPDQhwBaXQ+Nbg3Vz8CGGhFg7bpAjHrSR21Buwg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6nEoOdd8HVZSqOMuMkQGsMKUm77Wr5CSTcWJO/q+f0Y=; b=mfi1TzIxrENja5cCWVNHLiRBhTw51U1ycJYUGcn48UVjoylj/6htpHoNx3hpDPQMYEEpp3wnLbKntdZx7g5aALRkVPSIb83yN9697iBnc3kojCbfAelYqWSmqRjbY0KZ2TWWVg+jsXJWYt/W/SpdM2b3ftLgIqZFn7vhiOx42O/HzrEdYjpspCBi073b3CWWBAyzacXghhVQ3GxPV2oSczfFOJ1iI8ni1aAxqPta/OJKxUB5Bihq90axzbWHomaIUjh/ecyvSoGGboNioibR5ORaujlcYiiOY49iFfz+DHf4MEB0TlJrEvvuD5HM+MO3H8ykil8AzBs4ZZd6SBTROg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by PH7PR12MB6489.namprd12.prod.outlook.com (2603:10b6:510:1f7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 22:54:23 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:23 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 19/31] gpu: nova-core: Hopper/Blackwell: add FSP secure boot completion waiting Date: Tue, 17 Mar 2026 15:53:43 -0700 Message-ID: <20260317225355.549853-20-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY3PR03CA0003.namprd03.prod.outlook.com (2603:10b6:a03:39a::8) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 82ef009f-cd85-4d29-1b30-08de847821ae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: yIRPGnOsLPXKMkyMFAmt9QJZRvTsojgKGv6G8IHGpscSk8cKorMBQS0Dqthn2bXl5T697TfnblTDKnFLUIlFCZJvhS618MvwNovUR3/GyNqeVjTBxoqhxwGRMqmRnB6BLrGO926aDaW2ANG8pUkGhHYepvdQ/El5D45824B4SFy30kGQxJOnbC6uuothbtm9nHTUbFd4t/g/wNDm8C7HEq/DOheGIkqjhPHZsj4ZVxI2gMRNI3BdevrgfeKyrfAY6Lx6QEOHSRjWCWxHSkaMPWaXh25g2LDxlHdmmKXqVX0Q0McFTutaQ9VNYre2PsaF3WA5mZxLgpJYKERSz9MEwdYZLhbB35AyTwMNc7Z39DcTEPIQ+WbAMxDIyYoquyIoF0aeA3jZtySKpSxBw1CNiALJlqxxiAmg+ov8mFQtn0TNWU4mO1BQtnD9t9V0/EFTJY51YoJcB/+A0r46X6ZITMme3+dS2TM41AtrIim+V2yHev9sBec9lu5WAgTiqW6cKEkJXFfQr/3nbZVvhfu6YR/0qkfWHbbXIfFrFFaKlAw0JsbJHtNKYJUbtHOicGwVYPRlyBSaF5UJNoDDCunYZlFMAO25r3eeT7H3daIAJzG1I5RBcADl1rNvJCojjXf6NBoMwkLeeMznJ4eVrhLYHc7kMdQ9602WOk6UM/3OvPy7WRX9WkUHwwuN66xebSn33QBrh7Cmpz2CThrSX6B6eB077KSjj0as+7CmHfiORAg= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?xIPDBTd7d3PrPIa+KpsJ23Tl0c1qNRXSi0+JRkZAkIEwCPTe2CHO+7qkUwFT?= =?us-ascii?Q?hLZ7C7upx6aeq4kz8JhNOHYyrkB/F/tF3nxhot7hnaH69oSTC3NPQd0kHyfR?= =?us-ascii?Q?ocpvHynbcHh946dBfmCUek0AgDwmfvajJDLFfilCi3oUffw0lcwc45/1HTzW?= =?us-ascii?Q?K4SiOITVeeXfpcfGTwF0ifjcFQPd4Kq0ZR7N3HLCCxkYoVmPxc7B8AB8FNAF?= =?us-ascii?Q?9X3UtEY0v+4xwHVUWkS8k6UBntpuGXdzksTIXrHz619Nfs2wtET4f7oqakr7?= =?us-ascii?Q?IQw6YWyrDb9npndYrVNDzXza7qJA7frMIXqULEue6Ex2yjApj0/Ohr4KbK6o?= =?us-ascii?Q?dU7+RWWV1IS2NVt/VNEdnimhmhY7ygadaMdWt8Zlx9U+mOl3hwGEh1PCgw8C?= =?us-ascii?Q?XXfZlEeTCtvH1xNwTh23iTDi58MvRGiLnEtF1i1wf8iKkGxYNh/9luy8rUFQ?= =?us-ascii?Q?fghmQ3SZgRhPR53kPdou6f3uDHWTiLf1n8Naml8/menSkjj73/oG5e/OL1BH?= =?us-ascii?Q?wdTBUffdm1v9ufQfTeQjkVbit8dSQlmXlQanvq8ZNkBQymeL/HuTue2lFnaQ?= =?us-ascii?Q?nSkWFdiT9sZVGOFGIbzSR1bxbman83kFQ7oC2ceFS1YwEyo6ar0V5pAdzvjZ?= =?us-ascii?Q?4Z91RZbmpyfA0h2xCkA9FvPgOCVIBMR4RZG0xV4htCunTP+XdkNvDmLUVJb2?= =?us-ascii?Q?740QPRNXbLKWpOh/1BbvoL8CfwcklFLRds78FoNAJPFuF5ezTGaurv4q4YED?= =?us-ascii?Q?Jqh7mEYNNkl+i57nG3XMD5NWSU6e+xBBFID9kRpUDP/Nr/OmxHeBqoTQ1Z43?= =?us-ascii?Q?KmTCfChe4518dA9Qj0ZGGP9wJzBgiODc2TSnD5yk7W8ZM29mst9DKBMrUTx7?= =?us-ascii?Q?BIaKcvSEvx7mu7v80jt9/6nt/ceFfMAzV1VpEZdFcQa6QKJqzZYhXmDw8Kvg?= =?us-ascii?Q?Is8ABcGzgtv8BnvFJDDRyCR7w+bqZiVyPTcO6v/IVcdSphl/BW4HLnfUCSQS?= =?us-ascii?Q?446gKY7ugALU70w9f6r3jXJs9lra30QeSyeCb1KZbfHX1oz4CCVNNOQbvTs3?= =?us-ascii?Q?Cev9IT+hGV7fltbxNsqCtj2H0VXG66q80jCD0j9de4yVfiRk3DXCaCLzSqj2?= =?us-ascii?Q?1m6E2kXnWfsJHm38kPtAxVelB6VCDtywLqf+fH80u1sYKAfgtTt28FMLbxgB?= =?us-ascii?Q?ZBEMXnJUSEo1Xsl1KSAtl8GrDHbTc8q+4yNjAv8G+x19Z2NU2vcaOAgoC/KM?= =?us-ascii?Q?lJG5S1FZiSXTUV2hbKNj5rl2FtIrtHn8eIKLHK2kB0fLpe5+SjhMY2wUsEFR?= =?us-ascii?Q?WVbVJm/34S2LNPqjyH+klcLJp3zFRVfgwLyLuK/66nHoq9ek814o9UV1y24Q?= =?us-ascii?Q?C9fd4tS4OcYP1/qZzhIKxgf8CIfM9zu8wCVrbSlH1LGOw3Uahpa4EInbYnr8?= =?us-ascii?Q?ARi0isgTKile1L9OQKqGk5bgenLCNaOEogsWmGNijeTLfkkdoVzUDZcObRy6?= =?us-ascii?Q?IjUPKHrspsLcMWoL2SnHutNCNRi8C11VUIQfLqevaLhZ7uIEszNIZzmPvLrI?= =?us-ascii?Q?OF1VRwgE8XK7OsgaJeKbFjx/JAPXo2cSJtTBcroF5wREZxHwTERrkx1Kocmw?= =?us-ascii?Q?qUX6XqD++q1RDoU58wg1ueVMICqnOa79SFENoHEGiYFgX39QMYQaPOVISJbn?= =?us-ascii?Q?2HQlT+S92QAVE2/bXret1SCaZ3GfcS157La7MN/pwietno3Egc9gfZnnCf+M?= =?us-ascii?Q?Sc0gjE4hzw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 82ef009f-cd85-4d29-1b30-08de847821ae X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:23.0869 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XDAE6ZNRHkGrLHkbnbZluSRrS/L8yiHoUtl3cJDJ/bZj4iysbUUqsrB1cEmR1lr1p0lhbajmQLssoX9Fgt02+Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 Content-Type: text/plain; charset="utf-8" Add the FSP (Firmware System Processor) module for Hopper/Blackwell GPUs. These architectures use a simplified firmware boot sequence: FMC --> FSP --> GSP, with no SEC2 involvement. This commit adds the ability to wait for FSP secure boot completion by polling the I2CS thermal scratch register until FSP signals success. Cc: Joel Fernandes Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fsp.rs | 141 +++++++++++++++++++++++++++++ drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 29 ++++++ 3 files changed, 171 insertions(+) create mode 100644 drivers/gpu/nova-core/fsp.rs diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs new file mode 100644 index 000000000000..d464ad325881 --- /dev/null +++ b/drivers/gpu/nova-core/fsp.rs @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! FSP (Firmware System Processor) interface for Hopper/Blackwell GPUs. +//! +//! Hopper/Blackwell use a simplified firmware boot sequence: FMC --> FSP = --> GSP. +//! Unlike Turing/Ampere/Ada, there is NO SEC2 (Security Engine 2) usage. +//! FSP handles secure boot directly using FMC firmware + Chain of Trust. + +use kernel::{ + device, + io::poll::read_poll_timeout, + prelude::*, + time::Delta, + transmute::{ + AsBytes, + FromBytes, // + }, +}; + +use crate::regs; + +/// FSP secure boot completion timeout in milliseconds. +const FSP_SECURE_BOOT_TIMEOUT_MS: i64 =3D 4000; + +/// GSP FMC initialization parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspFmcInitParams { + /// CC initialization "registry keys". + regkeys: u32, +} + +// SAFETY: GspFmcInitParams is a simple C struct with only primitive types. +unsafe impl AsBytes for GspFmcInitParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspFmcInitParams {} + +/// GSP ACR (Authenticated Code RAM) boot parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspAcrBootGspRmParams { + /// Physical memory aperture through which gspRmDescPa is accessed. + target: u32, + /// Size in bytes of the GSP-RM descriptor structure. + gsp_rm_desc_size: u32, + /// Physical offset in the target aperture of the GSP-RM descriptor st= ructure. + gsp_rm_desc_offset: u64, + /// Physical offset in FB to set the start of the WPR containing GSP-R= M. + wpr_carveout_offset: u64, + /// Size in bytes of the WPR containing GSP-RM. + wpr_carveout_size: u32, + /// Whether to boot GSP-RM or GSP-Proxy through ACR. + b_is_gsp_rm_boot: u32, +} + +// SAFETY: GspAcrBootGspRmParams is a simple C struct with only primitive = types. +unsafe impl AsBytes for GspAcrBootGspRmParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspAcrBootGspRmParams {} + +/// GSP RM boot parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspRmParams { + /// Physical memory aperture through which bootArgsOffset is accessed. + target: u32, + /// Physical offset in the memory aperture that will be passed to GSP-= RM. + boot_args_offset: u64, +} + +// SAFETY: GspRmParams is a simple C struct with only primitive types. +unsafe impl AsBytes for GspRmParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspRmParams {} + +/// GSP SPDM (Security Protocol and Data Model) parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspSpdmParams { + /// Physical memory aperture through which all addresses are accessed. + target: u32, + /// Physical offset in the memory aperture where SPDM payload buffer i= s stored. + payload_buffer_offset: u64, + /// Size of the above payload buffer. + payload_buffer_size: u32, +} + +// SAFETY: GspSpdmParams is a simple C struct with only primitive types. +unsafe impl AsBytes for GspSpdmParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspSpdmParams {} + +/// Complete GSP FMC boot parameters passed to FSP. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +pub(crate) struct GspFmcBootParams { + init_params: GspFmcInitParams, + boot_gsp_rm_params: GspAcrBootGspRmParams, + gsp_rm_params: GspRmParams, + gsp_spdm_params: GspSpdmParams, +} + +// SAFETY: GspFmcBootParams is composed of C structs with only primitive t= ypes. +unsafe impl AsBytes for GspFmcBootParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspFmcBootParams {} + +/// FSP interface for Hopper/Blackwell GPUs. +pub(crate) struct Fsp; + +impl Fsp { + /// Wait for FSP secure boot completion. + /// + /// Polls the thermal scratch register until FSP signals boot completi= on + /// or timeout occurs. + #[expect(dead_code)] + pub(crate) fn wait_secure_boot( + dev: &device::Device, + bar: &crate::driver::Bar0, + arch: crate::gpu::Architecture, + ) -> Result { + debug_assert!( + regs::read_fsp_boot_complete_status(bar, arch).is_some(), + "wait_secure_boot called on non-FSP architecture" + ); + + let timeout =3D Delta::from_millis(FSP_SECURE_BOOT_TIMEOUT_MS); + + read_poll_timeout( + || regs::read_fsp_boot_complete_status(bar, arch).ok_or(ENOTSU= PP), + |&status| status =3D=3D regs::FSP_BOOT_COMPLETE_SUCCESS, + Delta::from_millis(10), + timeout, + ) + .map_err(|_| { + dev_err!(dev, "FSP secure boot completion timeout\n"); + ETIMEDOUT + }) + .map(|_| ()) + } +} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 3bd9b1dd0264..bdbe7136f873 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -10,6 +10,7 @@ mod falcon; mod fb; mod firmware; +mod fsp; mod gfw; mod gpu; mod gsp; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 686556bb9f38..183915a3bb31 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -8,6 +8,7 @@ pub(crate) mod macros; =20 use kernel::{ + io::Io, prelude::*, time, // }; @@ -491,6 +492,34 @@ pub(crate) fn reset_engine(bar: &Bar0= ) { 31:0 address as u32; }); =20 +// PTHERM registers + +// FSP secure boot completion status register used by FSP to signal boot c= ompletion. +// This is the NV_THERM_I2CS_SCRATCH register. +// Different architectures use different addresses: +// - Hopper (GH100): 0x000200bc +// - Blackwell (GB202): 0x00ad00bc +pub(crate) fn fsp_thermal_scratch_reg_addr(arch: Architecture) -> Result { + match arch { + Architecture::Hopper =3D> Ok(0x000200bc), + Architecture::Blackwell =3D> Ok(0x00ad00bc), + _ =3D> Err(kernel::error::code::ENOTSUPP), + } +} + +/// FSP writes this value to indicate successful boot completion. +pub(crate) const FSP_BOOT_COMPLETE_SUCCESS: u32 =3D 0xff; + +/// Read FSP boot completion status from the architecture-specific thermal= scratch register. +/// +/// Returns `None` if the architecture does not have an FSP. +pub(crate) fn read_fsp_boot_complete_status( + bar: &crate::driver::Bar0, + arch: Architecture, +) -> Option { + let addr =3D fsp_thermal_scratch_reg_addr(arch).ok()?; + Some(bar.read32(addr)) +} // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011013.outbound.protection.outlook.com [52.101.62.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BCF03FB062; Tue, 17 Mar 2026 22:54:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788074; cv=fail; b=Cm+Ma3zHXUVMLIzz4mfWrjbGy2CjMoYgGk4BRnJH+Swlc0pZzJBU7hKWeL+jsHalDlqAC0l02KHbai/jb3AYnbY9CUTcOkTsdQsHB/6TyqvFJd3eVr8c2FJPP/e1NZl8g/Rub91lCcPbW/fiSVlXMydCsyxh0P+eXTOPAudFL1A= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788074; c=relaxed/simple; bh=EhJj+JSv+mlUBOk3rkKeIF/qCGhVcegVU5eGpjfOghk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=eTea7GFOB+uQR3p/taTsN0PGL4kMbLqrwXCM6o/P3Inhqk9Ybxf6qFoYmvc7TJOsYmbM3Vp3KZqz584s5lyDrod061n82vScVCMem0YVK0BDY3cQPayxA71O7ES+o4FS+toq4HbBzAc8oNF+tAiEQeivkVawFjPvTSqH4mmxZ58= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=QhmxH3UI; arc=fail smtp.client-ip=52.101.62.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="QhmxH3UI" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Sw4rzeZQbRpBuxeqieVcFudk6udOZli/1tzPZa2R4IUeAHwW3Jm0S0wRjGRQ4lexPDxvU4zExesxOQkdc9/1MvZq5622htHiH1nBnRQLiAz4qTwSftLNIsO7TlUkRL7Jjspvyiq084Fq9IisevKZCqFgBkPB3tRZuIYYIm6evCra7PHbXj8Z73eWdBM8TsZVnR/dsGT56yccMhQC/i0KYZI4MoEtKeFseQSeOafoUkukx2OB5Ooe2Gy71v/3rRLPUjzKM+kwsRU5nlLBXO1e2jBbqpN77vLdk90V/Eaneb6pfynyvPKIhj7BHvuADqR+Ky3GHjUa2m9+oDyCoaFSFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=gf+jsGbR77cE9ouw9SuS8Zz66UqUUpOFeErOxlCcmUE=; b=AgFffXmLfsfkMBJlLLPjYH4EDRwINd4JLxi7s3ZmvGnWve4mHv3J2wPzGBkJqCpofcUn1Vws4w36StHjMXgSlESNDjrpQI71+xpLNy4FxN+jT87DRcDn9X9tL9eWK9pbsGrQBZQRj1nvuLxgV+qO2Q8Ank/nClHPT5h5/cQpEZy2km+EqH12UzSPhVPuRAAnWEC6/mykXYaJYagQk/aeBYCxrD4LGYkOojgwnYcxQNRQRCUQ+BFcBpYBlSGTVL0QhzAlj7xTipnbe6fpGifL62uDm9qGJhz7FcE1u5pGakh8h6n1pm1LiKHoxRdDDQSYIkuX5N73UZTAZ8xleNp2Pg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gf+jsGbR77cE9ouw9SuS8Zz66UqUUpOFeErOxlCcmUE=; b=QhmxH3UIgDV+E9RhJ/GdeAWRsUzL+EPoQIAvmXwxQbZlObwuwCwWofbkH8T1eNHA3XTIUkCE9xc4u1gTSJScGyZWJqj0fQm2C+tI2FyQKLvxwO5px2zIbho5tIZms0ihUzWN9+7YPs7R7Qq3HG8c6pFUFUF17XYccbnb6mV2RmlhTZpnbOP1wlMUJxbSlj2oz9CfhXNmnKsZXtH4zTen85A8Y4OueDKFe963NVRSTsmDEduGuOkb0mNJgd0xmT9m32fazVSHVoijFITU8u2w4iGHV7LDwl3k4gZ2lK+NtYfkTLWWPOto43xmcXWvBjnpgbSDr4qC/62WJmg0wVo/Dg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:54:24 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:24 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 20/31] gpu: nova-core: Hopper/Blackwell: add FMC signature extraction Date: Tue, 17 Mar 2026 15:53:44 -0700 Message-ID: <20260317225355.549853-21-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0294.namprd03.prod.outlook.com (2603:10b6:a03:39e::29) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: d2fb9e15-984e-4374-9ff1-08de8478227e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: 1hXTVqwhvcbvAepipyemlz8Q1pOi/uxAy933e17DNV942ScqWl0p7RBDQan2mwUXICthziNsI1eOrep+TViOX+6C+2uHCjXkssLYbKZMp5EnVj2+O+kwDdgyT2jWgJ9vVz0Q0poWfXpcYz0xmVVgeGO+lM6qC0oQFNWtPyhoraC/PBUkOW0AespA8MnB9p8mGUsyN8FMn4qghP4nNlssR5T8vE0JActHaM8mhqESc++lM+pnnS+MnJWKCHf1xdSIwl5OBHlyPCzzV6extxCO6IrDAhHNoMlU4nQfIr+7EcwsSJQCYZRneRWXuCF2UotqBv4N0PeYBxY7BXaHVaX82wehJYdYKF9FlFGlgRMjdkZFRDRSeUAygt4eCZXU9JU6+j2g+MqAkfI1iJcbVWC8aJfVC2sEom6ou/QB/6muMZtC1tL2nbX9ALLMi0Up4sNLgddxiJXjLF+FZRCHRX+Jn19qT9aAQkFYoDlEV/iYaD/b7/QSWjJY4XngRy5mBsBYYujDzhFKmz+SrEByRER9ohB+3d4Uon1yutiyHscKCZr0G6dWQMVnbTE8fIyF2Hoi+qS04L5a1czsIP17ti9eIemCkxHx0BMXfuBtl30gQKxeHzIKvhFrMDH44Pu+jfXjpx5fiJPtF3QjVdJyMsds/V66Sllz8UVjA39cAaJK7nqniyHTSQ1MrBRM0rw2tIqAgN99XyG8hEVfeLF2dwOhQQzY6iPYvDwoK3xTXGS05v4= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?SjVHz9H77KQTj9SuyT3WszFdOZFqrfb1sRn9wyfG5aYebwxxnOchn7cw2Wl0?= =?us-ascii?Q?o4vkz+z7w64Blnjlr9kF5BiCEoojoQ03CaB0b4WVI+dgK/mFr1NUXMO0jpGe?= =?us-ascii?Q?VXplGKmiq4QLS0muTP9hYcY70G1qFcG6+2Wjt0Bas76DQ4gmjIy0/nF/W4Iv?= =?us-ascii?Q?uxcfhQ7L9/UooOzP+VABLIDZJn5f7XBfWta7VdDgzrFIIAhgXPGIwAnoK/Pg?= =?us-ascii?Q?+qLHKYNZo/ZvNj+Z53O1Y8i6HPX9jYjL4YFIdwaLgLDJh4Q81y4y0fK+ZytT?= =?us-ascii?Q?cPhdqTku8kiaYKsY/L8eWZJltY7P0smyJhWpNTZcjVzqQ8tfmKDUdPSymApM?= =?us-ascii?Q?7871pQMV74UeAvO4rPgUWGvRkXJpSmSsjyVNjoeEH+8r1nS5TQgQu+x0KSd+?= =?us-ascii?Q?pzudin5YW78iYW2S1r9h1jow02ogxDglftl7dSFMGKMDBQg5V8wy61DUFB8M?= =?us-ascii?Q?hccnHfGHex8RvM87BO1+JYj4cExh1HGBWYKcZqUVKW2XrVdwGUrrU9oZTA8G?= =?us-ascii?Q?n/ElSVWtcD5g0uGAW7XP9umd2FxMSqTlAmTUkcxv4Hr6o3FF8uOmq0pdTRv9?= =?us-ascii?Q?ysGW5+RdUq4Y23H3ON848s1+CaoQdR3T1JxmHYXPXpSCNDyadeREtX9sFOEO?= =?us-ascii?Q?7aRJTXgtkkRV/U8mcyBHq+gWDTl39OS7paSdYDEMrQXJkA7/BOeWV5UnpYmC?= =?us-ascii?Q?KLImjqUvmXASHbKZQ/u+u+PmSD7zLNk1c2EBGVNp7vvaYqDkghh0nELOniCP?= =?us-ascii?Q?qPfsAYfe5s1bvuUypyMWs0iMooLwsX61kLct1mE1OInYqmW9faTamfECNaCj?= =?us-ascii?Q?nqBA8l8SdsMbmJUJr9CHN7/4U9/XetkBCT1Ll9MDoUrXrXXQQqwb4KTQcOf9?= =?us-ascii?Q?kCMwJu3s0eqv6YF8eA3mgm/9ZxAS53OZnAQ0RI/lfvJGLtfsUk6nPWJFdsMD?= =?us-ascii?Q?uTeKOsvYLuXT8p9FORSdqxPS9eRgXAUwVuWU4C0JJoB6wq1dYZVAhNCAQ4CW?= =?us-ascii?Q?BqNa4FcGX+qJbpJNVTlP8znzQYfpBeQDTvtSJKqFI6Z7tzq/omgLFxNF4tPh?= =?us-ascii?Q?B5I+iHwrfxPQUMntNlyLrDia8/B2nSMADpADU+m43B0EgfoRuigQfJvEEKuQ?= =?us-ascii?Q?n3QDp0+7omVB9/ZnFm9y7EnvaOZrld8u28wGtldjdzSAlTztf5IQKL4PpDBk?= =?us-ascii?Q?Fy9swkVPh5CgtzsLQ35A8AOsae55l8SPmE60PneGC131Z6jvBaTXzCxZVY1w?= =?us-ascii?Q?v8L8CZeYec5dmGAASM8IX7KPJHQZIlmaeKfjQgIGEk2T7KbWbIE8iTh8xrC6?= =?us-ascii?Q?0FXLpxav5e8fS6THu91dEwB7hKCOqMrMnzlAvt5ZMDHH7QIKal7WeOqtftIG?= =?us-ascii?Q?ACdx3cZgOxPGuh9bJyzUDKEdspmF2rWL/NhF4DsrOkbnfnLpdXh5cLNyk+Fm?= =?us-ascii?Q?i9kp6OcloGKF1HEffx/xto6U1wvu8RkWbIwa/aHXbt0uZENEvYwSk2EC3dne?= =?us-ascii?Q?yXbBCW/UBbEiHYJZsNdU0VHZAaHIM1YZJYoy5mpCMKlG3/EP7Wo1xWZs8rqC?= =?us-ascii?Q?/Jl0SXVYcRuog+XocA3tN+xgGmCd7aWCvqGC6fRKX0pHZAirQCWGvIqOICuE?= =?us-ascii?Q?AnmsfUo8vkY+IMa7vE0285NpaBlipmFxzC87MmzygPzu+UmYtfAFHz9KsoVD?= =?us-ascii?Q?PahQLzRhnl2yN0bp5FSwAWQBCb4SlgCDnFoAq3MAjjezS9+xYnx3P38pvXD9?= =?us-ascii?Q?QHHwhNMQUA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: d2fb9e15-984e-4374-9ff1-08de8478227e X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:24.4358 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LYHb3mJhM7Z5S/7Xm9KfuYRgr0fxO8h5BbBYEEl+58/AjIinur7u96SRQSFnB3b3XmayEtDoyxKjdOigTip+Ig== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Add extract_fmc_signatures() which extracts SHA-384 hash, RSA public key, and RSA signature from FMC ELF32 firmware sections. These are needed for FSP Chain of Trust verification. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 3 +- drivers/gpu/nova-core/fsp.rs | 79 +++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index bc26807116e4..6d07715b3a49 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -26,6 +26,7 @@ }, }; =20 +pub(crate) use elf::elf_section; pub(crate) mod booter; pub(crate) mod fsp; pub(crate) mod fwsec; @@ -646,7 +647,7 @@ fn elf32_section<'a>(elf: &'a [u8], name: &str) -> Opti= on<&'a [u8]> { } =20 /// Automatically detects ELF32 vs ELF64 based on the ELF header. - pub(super) fn elf_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a= [u8]> { + pub(crate) fn elf_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a= [u8]> { // Check ELF magic. if elf.len() < 5 || elf.get(0..4)? !=3D b"\x7fELF" { return None; diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index d464ad325881..a13d883373f0 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -105,6 +105,18 @@ unsafe impl AsBytes for GspFmcBootParams {} // SAFETY: All bit patterns are valid for the primitive fields. unsafe impl FromBytes for GspFmcBootParams {} =20 +/// Size constraints for FSP security signatures (Hopper/Blackwell). +const FSP_HASH_SIZE: usize =3D 48; // SHA-384 hash +const FSP_PKEY_SIZE: usize =3D 384; // RSA-3072 public key +const FSP_SIG_SIZE: usize =3D 384; // RSA-3072 signature + +/// Structure to hold FMC signatures. +#[derive(Debug, Clone, Copy)] +pub(crate) struct FmcSignatures { + hash384: [u8; FSP_HASH_SIZE], + public_key: [u8; FSP_PKEY_SIZE], + signature: [u8; FSP_SIG_SIZE], +} /// FSP interface for Hopper/Blackwell GPUs. pub(crate) struct Fsp; =20 @@ -138,4 +150,71 @@ pub(crate) fn wait_secure_boot( }) .map(|_| ()) } + + /// Extract FMC firmware signatures for Chain of Trust verification. + /// + /// Extracts real cryptographic signatures from FMC ELF32 firmware sec= tions. + /// Returns signatures in a heap-allocated structure to prevent stack = overflow. + #[expect(dead_code)] + pub(crate) fn extract_fmc_signatures( + dev: &device::Device, + fmc_fw_data: &[u8], + ) -> Result> { + let hash_section =3D crate::firmware::elf_section(fmc_fw_data, "ha= sh") + .ok_or(EINVAL) + .inspect_err(|_| dev_err!(dev, "FMC firmware missing 'hash' se= ction\n"))?; + + let pkey_section =3D crate::firmware::elf_section(fmc_fw_data, "pu= blickey") + .ok_or(EINVAL) + .inspect_err(|_| dev_err!(dev, "FMC firmware missing 'publicke= y' section\n"))?; + + let sig_section =3D crate::firmware::elf_section(fmc_fw_data, "sig= nature") + .ok_or(EINVAL) + .inspect_err(|_| dev_err!(dev, "FMC firmware missing 'signatur= e' section\n"))?; + + if hash_section.len() !=3D FSP_HASH_SIZE { + dev_err!( + dev, + "FMC hash section size {} !=3D expected {}\n", + hash_section.len(), + FSP_HASH_SIZE + ); + return Err(EINVAL); + } + + if pkey_section.len() > FSP_PKEY_SIZE { + dev_err!( + dev, + "FMC publickey section size {} > maximum {}\n", + pkey_section.len(), + FSP_PKEY_SIZE + ); + return Err(EINVAL); + } + + if sig_section.len() > FSP_SIG_SIZE { + dev_err!( + dev, + "FMC signature section size {} > maximum {}\n", + sig_section.len(), + FSP_SIG_SIZE + ); + return Err(EINVAL); + } + + let mut signatures =3D KBox::new( + FmcSignatures { + hash384: [0u8; FSP_HASH_SIZE], + public_key: [0u8; FSP_PKEY_SIZE], + signature: [0u8; FSP_SIG_SIZE], + }, + GFP_KERNEL, + )?; + + signatures.hash384.copy_from_slice(hash_section); + signatures.public_key[..pkey_section.len()].copy_from_slice(pkey_s= ection); + signatures.signature[..sig_section.len()].copy_from_slice(sig_sect= ion); + + Ok(signatures) + } } --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011013.outbound.protection.outlook.com [52.101.62.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 162F83FB7DB; Tue, 17 Mar 2026 22:54:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788076; cv=fail; b=FTUfbtLM/cbIzn/YFOX8Ty9nZrabmmdAZC2LFQDY94bk+GmkbEMZfrYr8OsZv/qQ0NYI/hH25AnLdbuhPtaUSX+551x1zOAFBL7Ivzc82RQYqyf/6zmgk/6xhM3Zm1A53AB1ZKOpnDOqPWBiLt5AEKrL0RHkHsEroNjLUFqWG14= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788076; c=relaxed/simple; bh=cG+MwTSXUTE5EFNUQX3Bw0e5sEbHn37oTZHKDcbgDjY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=lZBIH+o4CD1aXtD+btNwWkB24xO4uH9H3EacWOR8o/VxF01yMhXPWmlcv+R8fu4VPrp0os5SPvQXvfDlGzPylGm5GijB/A12u7MOjCfAG8gOSN+k7iOnxipbTg7OZ8DIzELm0H+COJfvGEncDRwBB5R6YXIvE4kz7PJ97xj1gaI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=NVPdtFDW; arc=fail smtp.client-ip=52.101.62.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="NVPdtFDW" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Bf6LJzbEZeXXZ/qTp1f2kh0YLEB+gUt/RDP+nYB2sqWyNzAAoTUjMhgvuPi5AgFQNIqQ2gGwaO3LXHCCUzvDCoMT0eELjxle/qLCMjfyYnyfDjNPKoEb7Gt35JNHka967OtUTYsXo3tDE4K+lphvCoFPsglr+R79cvZVFpi+7oPx+mps+lxrsCNOziicE4vKfKiZG2J/Be4sWh1NeXJIbPIIH40NhL/CpOc6n5meE8OxxvTqIwmmTvfHKL0578eYadne5X0loChCQkMCf2rSSaVc6bOhV3d+cdGdv85YU/NEtI4oyu4EOZ4DKA3hvfVovcYXdvzdYLqZ14Jq9OJnsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vBBGJfGGO3Nd4L3+N9os+nmnO/nuhVK9onsPf4NxzFw=; b=d2ODjIBNVtrFx8wE/SVufiyA7Sh9Xg94MKdynGblh0+UYrsY8Hr/J2UwxMU5HT7iH81ZuzAw6eGCiSdtWgwx8UpYpFSe9LD+XHobhfuQMBMEwIlW/Bbl+fKKMOgN3mdD7JAtMHtiN6x+yLyc1lEhp65SjHX18ahaFjiFhVV02LNScaEIA9jBkFAO/3OKjeU/YCxcQrfprzhRk1278LYy2omEDt66cpYIWSS8InsvWkMI4XXwYQx36HAR/lR/BYSjPZWH31Gwhdgv3kjjADV/rP9SE+nyNpc60f2fpWtbrJoAQunSyQjEbG8exz6FZQa2i/tHrnRA4Mcw40CRXUQe+A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vBBGJfGGO3Nd4L3+N9os+nmnO/nuhVK9onsPf4NxzFw=; b=NVPdtFDW9rI3I1PYG7PedtQakUDcfhwkt6JgLcmqJDJQO0rjI+0xXTji+I58ffMHGrfSv/avDVMf9BHTfb6HaB2Tw8o3FEvsVychDu6yLTdcFHuOdn5aAKNOcZ57olf0ahjUzX57g/jJvf0IKeNtQfviNiu02ukHGPmBR6jb1FbNxGkrsW2piIvFLVtnYCeWWdlypR7pDdpMins07Vr5Knkt+TV5hm3cjXG9PoPwxh+sN2dlBvbJPnzqaCXjPZS17u3go0QN9xwnZSeyupn8R2Rup7H0mYEzfiZG+6WrG2N5HuCuRimtT2GW6BlQvPDApYjjMEqmX6wOom9AbXHXdA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:54:25 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:25 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 21/31] gpu: nova-core: Hopper/Blackwell: add FSP send/receive messaging Date: Tue, 17 Mar 2026 15:53:45 -0700 Message-ID: <20260317225355.549853-22-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY5PR17CA0031.namprd17.prod.outlook.com (2603:10b6:a03:1b8::44) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: f4dd305f-0c7e-4957-638b-08de8478233e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: t3saKsF+sV+SObrPCqywNlQx0WlF/KPE8HgKmYQsZwHNeI965uQNMtohuRT7dM+xl0X9YvLh/dgEIBHCpHYO8nm1Ax+wCZgylruOKxwrXw985jqOMIRtzmHv5e3F3Q6anrHwrhWkWXkkHtyV8VnxLBnXZpWc9abv6rpwjb4yTGrbCQTN3xgiqkWmLFkpwDo4iEqFHph4OTN+31l7tXg8dv7XeawgOfLDIyTNCUUkQFGZ6YhiqSVS+CZJtPxn8v+9MHSE0NFcOQgX+LNcOcAmEqfwKMz9dP040/XCnWvUha8LSOVe98BmMpvl/p5xNJ3A65BePmONjVjAJrtsGz9i3xMEzqjxbgYDKyfcFa2dQDaKyROyixevnvIJZshJeT+iroj7X1tdV9oAkT9oZWNKBNBJeGRz4Z356Ui0nmBnWl8hKdaTAcLPHqNZlJuKBkcm0Cojfvi55aLZMg3rnGxbSdiSDxS08sH7KVfBeOLxxRVNgFBKjaR+hvYWFO+xHZcGJSOQpHBUtzkATSI3OCIJU1Pc34CA6wtBCtQaQjKvfN2EVRm10H43NSMFf948906WtX6gwHlGMlNqV50G2cNCqVmaoR7Z0FkNKydUeyI4E8rRw/6U52hlq22fZRrKmqav+zgHPqiDTMTAibjbjr+RAUyUfNANkkzQYBBXw2YV5z+CYikJyKCc0dW7mpor8/lK2vV55jXW9ooDrGen0OseIZBfdJU9Y0lDLsHVRcH64vA= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?jhMRFyb3Hdvj0NBYst58Hv3NbPZ8S5g2AOhm2AM3x8tAdCq9Zk2sJ7d1h42B?= =?us-ascii?Q?wdunxwNhU1zQ5A1X3BVku6KR55Xs+wk5G/Q7T8nKYkXHAB7PmNwttq3Y+oUv?= =?us-ascii?Q?wCQdQcgOODFbvGZv9hIi+1+mSjBEdmox4vmnOmIbRfb580ZwQBjmetpeHN/S?= =?us-ascii?Q?bm60d24oIUKo9qwwQHzjg8icrDGkMeIKagv3sEdLVdFzmo37Pi2gSpa4mDSc?= =?us-ascii?Q?1ECgfi+sUMMrx9QgPVx6f7OrCP8Z8haeSAbqr7bLvOsWAT2p6w5yfq9UIJOe?= =?us-ascii?Q?yoHs11FFm+qfeXP8Z2YYtlrl9mohKhqrFNgPFjJaNxrUkLCWiVnTujFNHLwY?= =?us-ascii?Q?PbvVumijxR0hw7bG8Px+CAR6g75friNJ/o800NQhnYp2VkUzpwuUdJ44dlI4?= =?us-ascii?Q?HiiS/yRIzhJygwvwSEUkQvUT2geQxnKgd25VwFYd0QUl6aT/EYdxyBCOdxMi?= =?us-ascii?Q?Be4ew4cyGeyEwlakEeiV6E4ZUHGEXnvgUsJMhTm3lbBpdCQ6QFVUYmjnErv+?= =?us-ascii?Q?lQHKWb3C8qg50tq6niEUqys805eLOSuOLvx0NwVGPonHvYfS4FGtb8ST1PAw?= =?us-ascii?Q?XeBYpcGCPe2vPVbdE5LfxBT99PAE1eVVZHZvdgqkITLy/sWQMjUR8rDkJiG2?= =?us-ascii?Q?VJJ93IJZDa22DXoTn8t9lXV1Go/UZOP5Y8ymn1qJ0QEnbI3u1Ok2y/NFjExZ?= =?us-ascii?Q?aT3ml57P9C8Tjc4fWw7S9FcKZsWrnfitfN15pqiznEZBD8U4lwqwUsqHspWC?= =?us-ascii?Q?UP5HmP0lEUU5qvbUH350EhDuKNL8NFAiRlEGn4ycqL3U7aE97Enxt4cyolk4?= =?us-ascii?Q?IglXZmLdWK7JMsRGEPjjQlB1AEE8hQLU2WdLcN6spWBs6KMvjUklQSPdnePL?= =?us-ascii?Q?6qPxdKoRp4XzeyQ+7xIW6EYvd1dPhaScGgq/vAcAREx1BeT0sASDQ726/rL6?= =?us-ascii?Q?u/VcupCoZgfcsdkRV8u3DOo+SgWC5CzlkWSJKt+4JCK05pbxlK4HnnxfRWF7?= =?us-ascii?Q?Ga7mHw70+bb+ujBHhmPtfLbOip7OTNDMbJr/fJoS4tuFiswXz9UkoXBOkuJp?= =?us-ascii?Q?YC0ZunhqqR3OosKDLvBeFjBf+2Zszig9bTEYWoFh+x1AFOcJQwHibuygu4kR?= =?us-ascii?Q?7WpF+Ehz5U7tisWqIYUagLG5VeSendwCibYvOSSRr8H7InmyDxdNrr0+bmz4?= =?us-ascii?Q?TpUs/+IOUo1UR94BQLUleKxdIrt8rb3UGxIPdP1QHYVafJwoqnFE8AGrzRCR?= =?us-ascii?Q?G/cd1S9d/x2A74w8+hamSiFViHxZjjdQywx98gRJkOkGfh8RRfYrF/WNLgU9?= =?us-ascii?Q?WfYQQ5dFuy4qgo2POkYyY0hW9zJ51i+4L2JS6uELFEw/8qDZG2sYFJUCb/Xq?= =?us-ascii?Q?nk96SHenim+nBTigaZY1TY+FUvW2MWr+/BN4ttDOWXcEaEnWfij1TRP8TJUT?= =?us-ascii?Q?HJUQZZqRD/1gDTgCNmUqSCjSI0Nsx5wwhv7jzkmBjhhFRrEr34PGT4/YdWDL?= =?us-ascii?Q?dA51so/VuVXat3zQ2bSC9Ifl4+io8cuMal0vS4WZHRBuF5tDgaWKclET+2Zs?= =?us-ascii?Q?xVajgtTBbgK/s66JckVGgZ60DWAxsGuIjul1lwsEUkhuF5xXIu+XaItWEYgZ?= =?us-ascii?Q?StEbwcwB2b+0HGayyGkxb91boiNbMcbP0L4Y3AVipX5gyXCEsgO7IieCY/9F?= =?us-ascii?Q?zrUSa271WiWGMhnQoObUMCM1SEkSgIfhbUZ+TFvryvHvOlTydqcmRvJo5rto?= =?us-ascii?Q?2nyVV+8pYw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f4dd305f-0c7e-4957-638b-08de8478233e X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:25.7054 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: T0MKgY6TM0cmHN9qDtJcIWbNSlqxY9+35Yzuvp7eGcGuRAXvo9tmrOrRKy8uzVNKilW9rd5JFubOomQBo6+U9A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Add send_sync_fsp() which sends an MCTP/NVDM message to FSP and waits for the response. Response validation uses the typed MctpHeader and NvdmHeader wrappers from the previous commit. A MessageToFsp trait provides the NVDM type constant for each message struct, so send_sync_fsp() can verify that the response matches the request. Cc: Timur Tabi Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/fsp.rs | 3 - drivers/gpu/nova-core/fsp.rs | 123 ++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index faf923246ae9..1dcfd155b99c 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -150,7 +150,6 @@ pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32,= data: &mut [u8]) -> Resu /// /// The FSP message queue is not circular - pointers are reset to 0 af= ter each /// message exchange, so `tail >=3D head` is always true when data is = present. - #[expect(unused)] pub(crate) fn poll_msgq(&self, bar: &Bar0) -> u32 { let head =3D regs::NV_PFSP_MSGQ_HEAD::read(bar).address(); let tail =3D regs::NV_PFSP_MSGQ_TAIL::read(bar).address(); @@ -173,7 +172,6 @@ pub(crate) fn poll_msgq(&self, bar: &Bar0) -> u32 { /// /// # Returns /// `Ok(())` on success, `Err(EINVAL)` if packet is empty or not 4-byt= e aligned - #[expect(unused)] pub(crate) fn send_msg(&self, bar: &Bar0, packet: &[u8]) -> Result { if packet.is_empty() { return Err(EINVAL); @@ -205,7 +203,6 @@ pub(crate) fn send_msg(&self, bar: &Bar0, packet: &[u8]= ) -> Result { /// /// # Returns /// `Ok(bytes_read)` on success, `Err(EINVAL)` if size is 0, exceeds b= uffer, or not aligned - #[expect(unused)] pub(crate) fn recv_msg(&self, bar: &Bar0, buffer: &mut [u8], size: usi= ze) -> Result { if size =3D=3D 0 || size > buffer.len() { return Err(EINVAL); diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index a13d883373f0..4fb932f91da2 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -19,6 +19,15 @@ =20 use crate::regs; =20 +use crate::mctp::{ + MctpHeader, + NvdmHeader, + NvdmType, // +}; + +/// FSP message timeout in milliseconds. +const FSP_MSG_TIMEOUT_MS: i64 =3D 2000; + /// FSP secure boot completion timeout in milliseconds. const FSP_SECURE_BOOT_TIMEOUT_MS: i64 =3D 4000; =20 @@ -117,6 +126,37 @@ pub(crate) struct FmcSignatures { public_key: [u8; FSP_PKEY_SIZE], signature: [u8; FSP_SIG_SIZE], } + +/// FSP Command Response payload structure. +/// NVDM_PAYLOAD_COMMAND_RESPONSE structure. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct NvdmPayloadCommandResponse { + task_id: u32, + command_nvdm_type: u32, + error_code: u32, +} + +/// Complete FSP response structure with MCTP and NVDM headers. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct FspResponse { + mctp_header: u32, + nvdm_header: u32, + response: NvdmPayloadCommandResponse, +} + +// SAFETY: FspResponse is a packed C struct with only integral fields. +unsafe impl FromBytes for FspResponse {} + +/// Trait implemented by types representing a message to send to FSP. +/// +/// This provides [`Fsp::send_sync_fsp`] with the information it needs to = send +/// a given message, following the same pattern as GSP's `CommandToGsp`. +pub(crate) trait MessageToFsp: AsBytes { + /// NVDM type identifying this message to FSP. + const NVDM_TYPE: u32; +} /// FSP interface for Hopper/Blackwell GPUs. pub(crate) struct Fsp; =20 @@ -217,4 +257,87 @@ pub(crate) fn extract_fmc_signatures( =20 Ok(signatures) } + + /// Send message to FSP and wait for response. + #[expect(dead_code)] + fn send_sync_fsp( + dev: &device::Device, + bar: &crate::driver::Bar0, + fsp_falcon: &crate::falcon::Falcon, + msg: &M, + ) -> Result + where + M: MessageToFsp, + { + fsp_falcon.send_msg(bar, msg.as_bytes())?; + + let timeout =3D Delta::from_millis(FSP_MSG_TIMEOUT_MS); + let packet_size =3D read_poll_timeout( + || Ok(fsp_falcon.poll_msgq(bar)), + |&size| size > 0, + Delta::from_millis(10), + timeout, + ) + .map_err(|_| { + dev_err!(dev, "FSP response timeout\n"); + ETIMEDOUT + })?; + + let packet_size =3D packet_size as usize; + let mut response_buf =3D KVec::::new(); + response_buf.resize(packet_size, 0, GFP_KERNEL)?; + fsp_falcon.recv_msg(bar, &mut response_buf, packet_size)?; + + if response_buf.len() < core::mem::size_of::() { + dev_err!(dev, "FSP response too small: {}\n", response_buf.len= ()); + return Err(EIO); + } + + let response =3D FspResponse::from_bytes(&response_buf[..]).ok_or(= EIO)?; + + let mctp_header: MctpHeader =3D response.mctp_header.into(); + let nvdm_header: NvdmHeader =3D response.nvdm_header.into(); + let command_nvdm_type =3D response.response.command_nvdm_type; + let error_code =3D response.response.error_code; + + if !mctp_header.is_single_packet() { + dev_err!( + dev, + "Unexpected MCTP header in FSP reply: {:#x}\n", + mctp_header.raw() + ); + return Err(EIO); + } + + if !nvdm_header.validate(NvdmType::FspResponse) { + dev_err!( + dev, + "Unexpected NVDM header in FSP reply: {:#x}\n", + nvdm_header.raw() + ); + return Err(EIO); + } + + if command_nvdm_type !=3D M::NVDM_TYPE { + dev_err!( + dev, + "Expected NVDM type {:#x} in reply, got {:#x}\n", + M::NVDM_TYPE, + command_nvdm_type + ); + return Err(EIO); + } + + if error_code !=3D 0 { + dev_err!( + dev, + "NVDM command {:#x} failed with error {:#x}\n", + M::NVDM_TYPE, + error_code + ); + return Err(EIO); + } + + Ok(()) + } } --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011013.outbound.protection.outlook.com [52.101.62.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4C3C3FBEB6; Tue, 17 Mar 2026 22:54:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788078; cv=fail; b=YrDblBSOvUS1YQwsCJrAlOOUaAhbPNp60qTjtnjOkc1QaEgqwCM81o81gTp8Qab3hqFHBj+cZYIV2o3JqfS642x4Q14DxBWNc+6OUTCE6T5ZtRiVQCOKc+UYp4X2Zfg/qaGXDvqLoeHP5Nc1GXRcJ9jfiFMixkXr69G8x04IGYg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788078; c=relaxed/simple; bh=1Jk3K1LjP1e+X9y4b7AQJbE66/A9Izc/R8fJb5ht5Ew=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=G9H/Nc3aFiW2xw6ZRbxr6BX5c+emXyNGXoXN5WOqGuEH+AG3CS/07kvmVYa3rCIHgd5uBbMjZtsHDNSBUpBPFec5T6SQbxjxW+D2Jbhsa0yLeRmOTs5/kNthjsT9IIYd+XhK/IK8QZ6DLOze+EmTZf+kqVonVxGCj8eGo8o1dVI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ed1AqsDX; arc=fail smtp.client-ip=52.101.62.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ed1AqsDX" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fChhDvFud5Jv/yvKebIKnnw8Xm8xLVTGdEiS2gp7qNTqZzC+wFbE+F9Qj9bbN5aTXZld7bmT/rCgfGTRm+GKBmnOnZ7O4ZJSOlVFr8TJNpjdGp1E1BAPItnYZ27X4fv8ZfslO+j2kwvhX8cYny5xqvJS7/8VB4LtESkdVckuPurcmchU/z2EnKkN2womqkivWZYznWRg/Rm7Q7lnUhBkGuR0nKY0vfTknrY+iNy222bBC6ZXZXao+8yD+jED0+M6D1wXOClRxe8iAjB95KpwMKmC9iLq/pOm/c77WKsKfq/7JQkMZ+dPvsnxsVOGQKV1iM8V8Kj90UBeNAoEj4KUGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QnMJJVWVgc2OLmxCKARqgwbtgLXBO1LXgjP5+/bSqyI=; b=plc1pm5LRsUdg8sXdl/iC2LrJjGIK334T9tv/JdMTKOOx2+WJs8BM/jx/30fDWBwBHDdPf62lDjYCHJDnqQUGbdD/Ch1U0VQZiUfPrRwgkPh9J8lZ66lwmX81WsuL/kyOJlNCxzx3kIXCHEe5JJ854U75xFrKy8k3zgeSidKrT/NUiUtEP5cTwJQSMlFdKWgw3AdgffHt2Bkhnge7JL5JHQkmj5d46spWq8KMpeiT6AzzikQPBS1fsltseIujVD8O7q7/UTo7cDzQuv3zNg23qkzIJiz+Dg51GUu7aZZ9jG8YtEmhrewbKPTa+tJMHDGNWcZFu975tlKoKLC45tO/Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QnMJJVWVgc2OLmxCKARqgwbtgLXBO1LXgjP5+/bSqyI=; b=ed1AqsDXFMx0n7Nqpv7oGyS0lRrv84FrFthRS9VMvaxiC8obNc+nJwvDWbgSH0WAm4UxAz/BPhVccKj4CEwUm/KyzuB57CpBME8o4WVEBXGHUlaqiC8Xoz8TdgKJxqfAQYYvwweg5Rj2e+iqPYNGs28PZX0Q8np58Gnjuu7daM2VrUW4uxytyhDhx6c7t3d6WH0joqAZtzMsnvzKu42yLEHnfw2VItD8vYGfKN8bYVce+QMFuRlVSVMCFT9u6ofaeP4f7D+Te/bw/SuVoYubtc7IMFepi/aFHPZYNrAXkhgviCjHX3m+JoB9SUXr6AztowkT9Ep3fzdv3C8ia49Gtw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:54:27 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:27 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 22/31] gpu: nova-core: Hopper/Blackwell: add FspCotVersion type Date: Tue, 17 Mar 2026 15:53:46 -0700 Message-ID: <20260317225355.549853-23-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR07CA0057.namprd07.prod.outlook.com (2603:10b6:a03:60::34) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: 44f05265-d5c3-4c71-a575-08de84782408 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: u+Dc/p8GGNRJWqvdkBjN6uiOt07s0jDonM7VJ+QF8XSLzD0g1nKaVUuFXzVhLskPAeqsKOD43FbQlqckpXTMKtVZExHt/vFcy4Db+nqQw7lyb+L/jTxqzOny98oJCU9jT6XiLEjwhowN5Fc9HfTBrkAiTh989ZT1WDgPOX4yy2PKTYlx0ve6h2jHZu+vVW2c9U1SnRaCAZrGGrjtITV1+sQkfY8d5T/jdPWDN+o8cbYrfdGBdprZLCj7agRAs1khxfGZ4ba6UhYb5KJn/PiXVzbglG+QXgkJzbMDSqM74yYGZ2ypVZ2u04baAQeyB5RVk2K0seX484HAyLNWOyed4a+6yQ/NpZRHaDpbNKvZ1Ccq7tc+Q/x8O/erI4/rVv19WQJFConK5lZDm/QHt70tr9bqFUMa50g+MciVrl12pUSI1PDU5Sep3I9DigaeKEfHWirtqqgHGqFYdWfuQ7kXYCcfHeJipTD1giPfU4+VZ9bXdvu7DpsSsQl6rV95xvRZWZO4ehDkp97uQVxfrFe1JvObzcOwXZi6lRMSdkXzTpNAWQ/WRTbJFMWJjTrJWbOPziNyFwwwmzCejrXzhGfFuwXjtgR1zue65XxvC/zW3G8syUOUC+FBfW78+o1OEedfn3iWb24ViantjmIo09Pf2cO3cu20q9cWinJ2qh3xynovFOfyEZO1uVsG4O4Zc84tCVDe5V7bmrD26hnZNEu9RmF0pxd/Ur0gXjhnGg27Yjg= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?vC8gXsYWC3w16nA7GAm1+ibt60Ux7UcacvbhOxKG8zt8Y7fi3z4sOQ4AeCoU?= =?us-ascii?Q?aFR8XRnx2pNQa/4fX2rsCds/nihial+9qKgQLNqcHPnQDp7OCw7VbEJ+Hi/P?= =?us-ascii?Q?Edp5Buxe2Rsfac/2ju5h3GVAZ7xT7RnSx3LCRMGUoyQtMTyv/hzkamN+NYPX?= =?us-ascii?Q?tF5rkOLgdsfIYg0xykUDh+pehrBc6Arc6gngIHZic2VPgdFhNqt+1KGwBdk+?= =?us-ascii?Q?UdJr11fW7lx4wNPr/t0KJ63lo3LoSq3k2XUsONas0Slg7K2eEiDPHadAfZR2?= =?us-ascii?Q?old+0q+GIV3UUsl+hem03VPZewO9htj349n7tFNZCsf4SKCokIzw6eIej4FW?= =?us-ascii?Q?FaguuSwN0UxU/VoUtIpfGPSoKW52w41IcdIqA2Mu0570qNcWN72Qx/fPf1RV?= =?us-ascii?Q?hbl8adpzEY94KbCZN+VMX+m5ggmnl1eJ17Jk+dTfuy79Q4Qs81AdtkxB604h?= =?us-ascii?Q?uDYSOE4ZvBYZKyJm/f6rbRXbNIM95buOZenMclbUDZrXP/q8vhzEpsIpk1jM?= =?us-ascii?Q?iVtFyNARyytC/yaQXPahBQYZdMPUNzqoef5TR9si3PC/MOgOOD+Oq2Db89+Z?= =?us-ascii?Q?DkfO6ELvVemFVZ8emy4+Fql+SR+7L7aRyPp1bWKBoGg2Ic4NDuOOfgK1hmeC?= =?us-ascii?Q?JhTVwu4FFBH4WydhcStsnYMOn93vTp4+necY7VZrzvMoE2r24MUxJNxxpiJr?= =?us-ascii?Q?/3XkZCTqqWaxu+M0MYGeesBBKaIkVTRJxouGS3V0UhMINX+HS00YtgMBVhC9?= =?us-ascii?Q?F1vqCn9KCPqd55tjIN6IH4Ga4052xNQD93zRlY1o3+OfX7fOCjGRnU9C7gLe?= =?us-ascii?Q?aYP1UZ7qDto0YhUNYENi/YN/+p7e/Itm8JApW2OT3Eo8QHCWVvITObouqeBg?= =?us-ascii?Q?RVXjIsfq9lweCq345xHygACEUAS95KI3Tvc/AsX5EiddU50vT4Ln/81EXluz?= =?us-ascii?Q?2Ivc+roR8vga+RbTqGMVhjhpGYZb93HtctZRi6pRmZR8zlxEnistW7d5d09/?= =?us-ascii?Q?LpWNkId7nN9E8sQCVF3RTwJVAhfPIeHhd08FUl+DKTX7594RDT7Z6ip8fzN1?= =?us-ascii?Q?Aqk7G3iRwHjh8xgx7K3fo7WuHvcOosJMXVJUzE+Sr0VbYK+e7t1zCTk33UEa?= =?us-ascii?Q?WzXU619tWgEiWNm9gf5XpSGesix0GUL6R/xhRlWry6lKyeWUrj+7nzc7BTgW?= =?us-ascii?Q?wtkaexFCvaf3y3pb+/tSekZDuQP9BIPp9VL9vmwX3UnQrBxwbDx7a96iYHK5?= =?us-ascii?Q?RQNVyFolBVVhQwp7+gjnMjUGXOOZcmNbzMrOLmDmgqMUYZAH2tGz5zbgknxs?= =?us-ascii?Q?xSFToWx9/7cwjryTK0R1QltYjsyv9wumc4e/buGW+G1PagAln1Fi8mtp/92R?= =?us-ascii?Q?j/3TC3mtV8iaDU9PVz6Wqf+KjpHAF70UAKA+KuXFALbN827RfSlHULyWUwCg?= =?us-ascii?Q?vIIJXDaLMNf56po/AmBrrwtLWQ0HXG7BsJ1Vpj3b4uDPWois/FlsVnXesMVw?= =?us-ascii?Q?HhX+5/4M3uSV6pSNE8emZRTBLtBpNBBFSxTxiLqL0o6XvAzUPHfUoarr3xf0?= =?us-ascii?Q?MGJRCYQduux3YqOni0X2nkliXGy+KUewii2QIWrPwIx7uCzgq2CvOftBrgmJ?= =?us-ascii?Q?pY4iasFOB9gdmETh/Q1+vw9e5sVjOWXDFIlen3uwIvzlJX2U16bg7XBCn31d?= =?us-ascii?Q?7Yz7+OJfc+oJhpLmGFg8yYGFycsJtio9Kf3jFGmEzgriU2DuF3HDuMhlzsTy?= =?us-ascii?Q?LVnm2WEVEg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 44f05265-d5c3-4c71-a575-08de84782408 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:27.0069 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: yjDSzCa/fMJkZeohS2NWZz6vjBbp35ohtakYJ7WPoaYRiR4xZ9Kcpw1MU3gI8gBd8MfHTTB3dRTICxuX08DmpA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Add FspCotVersion to represent the FSP Chain of Trust protocol version, and Chipset::fsp_cot_version() which returns the version for each architecture. Hopper uses version 1, Blackwell uses version 2. Non-FSP architectures return None. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fsp.rs | 19 +++++++++++++++++++ drivers/gpu/nova-core/gpu.rs | 14 ++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index 4fb932f91da2..18edf7a1a8e4 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -25,6 +25,25 @@ NvdmType, // }; =20 +/// FSP Chain of Trust protocol version. +/// +/// Hopper (GH100) uses version 1, Blackwell uses version 2. +#[derive(Debug, Clone, Copy)] +pub(crate) struct FspCotVersion(u16); + +impl FspCotVersion { + /// Create a new FSP COT version. + pub(crate) const fn new(version: u16) -> Self { + Self(version) + } + + /// Return the raw protocol version number for the wire format. + #[expect(dead_code)] + pub(crate) const fn raw(self) -> u16 { + self.0 + } +} + /// FSP message timeout in milliseconds. const FSP_MSG_TIMEOUT_MS: i64 =3D 2000; =20 diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 93f861ba20f3..1d25513fef20 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -18,6 +18,7 @@ Falcon, // }, fb::SysmemFlush, + fsp::FspCotVersion, gfw, gsp::Gsp, regs, @@ -133,6 +134,19 @@ pub(crate) const fn arch(&self) -> Architecture { pub(crate) const fn needs_fwsec_bootloader(self) -> bool { matches!(self.arch(), Architecture::Turing) || matches!(self, Self= ::GA100) } + + /// Returns the FSP Chain of Trust (COT) protocol version for this chi= pset. + /// + /// Hopper (GH100) uses version 1, Blackwell uses version 2. + /// Returns `None` for architectures that do not use FSP. + #[expect(dead_code)] + pub(crate) const fn fsp_cot_version(&self) -> Option { + match self.arch() { + Architecture::Hopper =3D> Some(FspCotVersion::new(1)), + Architecture::Blackwell =3D> Some(FspCotVersion::new(2)), + _ =3D> None, + } + } } =20 // TODO --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011013.outbound.protection.outlook.com [52.101.62.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B7003FB07E; Tue, 17 Mar 2026 22:54:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788080; cv=fail; b=eqxsv5fVzmx6eFPmRQGUZWSyZtzmv8drYb9NYzOIkeF9+IhsSXzSqEVRzNseiCakQys8/jE4SnkKT7kIFPIsXtxasyNRCaGHWsnOAVEn8UTKd1UqgMB25xmxkSO778+pRY5Tr+ZNj6Jqpnq18FdVFj+9dsM/M6AkmbpSGB8fHIA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788080; c=relaxed/simple; bh=Z8wFYYXKqzYO9fHaKX4a31J2bHLXI80LtHf7mdhgk6c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=thiWb/mah4wpaVeBCeInwpFYZw5e081hcgLlx/Sx5Ynq1AiGeFCbhPVjxlQTu9bUdtrq1fF9VPIWFOY4fSJ9BixslP6F996nmU3KieXNQPcrHPiX4CgdItH0byWJKnzGgP2/GXLRyPXIaMm+iKsRmxoYnofA8Pu6UIP1teDuVeA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Sa4uWlmm; arc=fail smtp.client-ip=52.101.62.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Sa4uWlmm" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=RPRiCy7PrND27BwR9ba8y9lcfxV/xSH+KDyuJ6Sog0fY4Q3g/5cY8gGj80GQvngcPA60RKlv0FQRRDMqNciNsBeozcp19vpDOH9y84Be3GfKgD0Y7nDajprAL3chfNE5L8kR3zPLWd8b5bPBEoaQPlrTGbTZyf2HOtin9TzbRHgUSKkE0FbheCy+BxgVd/TfcN0gGwcPmtWMqUNV3KAT/HI92gKwlgVfXwFk9UAsnoDiB4LRhe4T9VIVYcW147qVCiV2f+Skqs3sm/H7KQ/65P4i/a3Y4YhLzvAv2YC/vHby3PWS+WNywJ4L4xwgOFm8YbAAyEN9ueQAYizd2VGNdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lFH1Lc2bn0mDibm+LFHNmx3AOI/x+Q1b1+c3JJOh73M=; b=b74V558DAf8Hh8EHFTkTlKzsZVGWk9l6K8njN8IshUn7LLmX9ZSkAZcjBZBTLQnz6yrzQtjfsRggqU6XLPogEONohbW2CDNx+srMsc2yPlApLzSe8AGs5MnErvhE7IX0HrhXCH9nlpejI6isw6izP5FE+IUDeL4/elzkc3k51CwdQB64+/wDi/9leO859hwP5KXuuQKyTp9qQ2P6pqLdYMRrbG8ARxWlB5YlKrRFiR1VstRGZTBWWM0r4H4NYvb3GQB4qirWaoHpZ9futlF/aU/Jc16bFWp6usRh5EpmHibFu+8dFn6r3wVHN4Z0gAZwGLTIQ8dM33BzOEYBZ2+NZQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lFH1Lc2bn0mDibm+LFHNmx3AOI/x+Q1b1+c3JJOh73M=; b=Sa4uWlmmtuflELOCsFXvnNmz2wm+b5NsoMlMKZAbfp/7UmOWcPZgEiqvUcxRy2rL+eG90Tz8EGGqlJ6kz4Qnj/DNv5j/T4djMRxpGhRsd0UPOfyDGLqzJtyBOV7UcRzQOfpn5TlVl4I2ZVzZvr7ldVGZZSFlcq8Jpwb61mYK0krgGk2ijDA3rkhK1QV891dTW78+EUff5kUnY2JKHv+iZ2bbHnT/Jo4SfTaBo8Yh9BK6xxwJwMamhUh5WIebZzmm8FN9WkosFvQ0wh1gHKcFdJamNkuJ7TPQ35nCm6X4A2KM6SfLSy17BSVeoUbNAZJtqftsYjAvu4v+jX87i9LbmQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:54:30 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:28 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 23/31] gpu: nova-core: Hopper/Blackwell: larger non-WPR heap Date: Tue, 17 Mar 2026 15:53:47 -0700 Message-ID: <20260317225355.549853-24-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR07CA0038.namprd07.prod.outlook.com (2603:10b6:a03:60::15) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: bf7c8c33-0c53-448b-7978-08de847824c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: C9prGvC4GdQJBLsLcc4Q9fl8sWAT0ec/Q3iKfV/K7f5/VD0wrQA0yzfiZCeqJrBvo82ikuCQXHs4IeHon8uc6HvGQL+RwMA4nv04EO675+khCIqxk0RNvCfO4gqca4+KJVo1wLotFg+ayCeVmpanpIgamUmrieVTgwSoxVqMTgd3kc1hbtLm9yXThj9COGOasMJX3gI1Wi6OAaOL5OeHFQIkmIU8PMPIogLintubvsDYmTbKO0dHbJjsl7MSe2iC/wxWnW6HlJv+YzNDlEk3WlbB+0UFzBscGLM73EBxt4W5pZTJRjSk6ScgDBPLft9SswuZVXeGlVFOIK2k/x9aVXaCOkoyxakSBvAFToxks0IajXSB5pokHWCoynzEc64QyLtQ2tGdH6Z96k/O1h4a9cXtAS+VJ+Ffrfh5Nl0mz8dP7IdHULf+Q96kiUuwPBaehy9IrgglgSh5RXlrN5Guko3xr8SOQH9rmTJOqK+Hu1DSDDwQ8CPHvULu+Cqv+Tlx7UiBknb5WnN9lE/oDNXiDcByNmmhMuhAr/9HOtq95jgo/V0eu3YWtNd/ol51wdAnjjGwLZcefSktM6eIpZd8EiWt9Vq+pR0Hn+8exnxEsb7dnOyTVWsn4YXuWEaQivsLAq99l0gr0TW6j05BzZyh8z/5dowfFxmo30HuwMM097Rm6Z8EJPtlcdAbZ3IHtWf/kKGNKUEeHJh/OMECKqvejDhpB6J9zKRiS2myj8rLmuY= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?ZQDHBRokIthJYvZHQUuBs6ZGNvHGZIPbCTRUIcVLQxMI7HSUseEszFcLewFP?= =?us-ascii?Q?+WwFszZ2Mmqe/g3QM3Wg8MMTdkvyQP/zST2Tl6AzzR51KKaQEVSuLEnHV9Ek?= =?us-ascii?Q?P0qChMYgIXZ7akfWfU+PQ64FY/Ve2f3gP3vN3wJnRDUwUMnP5MfyBEZq0v40?= =?us-ascii?Q?ZAOQ9IVtmLGePKr6mcj1ka/VaDj+XFzrgv+a4zlXCZmbP54Ir5uq0geJ0xmy?= =?us-ascii?Q?nWzd4Q2TlaX9lwK/wIlOmxcxa8f+eiQmG7PzvitDJE8XHdPxyQ0GU33wmeB5?= =?us-ascii?Q?NFkabz+zyjq3vtzH5re55RNARqEopkDANzhKvK2mbdDluEhu3gqx2p9LTekq?= =?us-ascii?Q?aj8ObqMzCHqfRxV8b+eiuh7vHCJJpfKeSRP8uYOY4cdZTWVJSO178oW72Mfd?= =?us-ascii?Q?2mAiuXnu0QOYqJIIKYNiYg9CoaPTKmYKRxCxTO+RAl05C7fwfVrqW6Saa7j3?= =?us-ascii?Q?2hfcBjH+rPRhmjJq82UEeu4pqtwrUqKfZqXbflTTY+Z0zRA75MFxps58FKiK?= =?us-ascii?Q?Xivdhg/L5czDAN4UcmsdotuqW1F2xgUmRWoBOVKw3rvR20dwbXkSJU8Nc+3+?= =?us-ascii?Q?WslnE3LDJTYCNMaCJYu9Y0qyAM618dxYRPS6+9sk21eOwZmfFBgZwUFle4Zr?= =?us-ascii?Q?2N1ExwOtoqU6vOb2/J4L8SbQOU3a4HGxA2qVJsS8MYqs9poJ7+y+UwQcSs6t?= =?us-ascii?Q?r3qfwTmH/RzErweE5qcjxlV/G7bTDFFs9HHg876XY1uoGcu9AAXMDaav3ztZ?= =?us-ascii?Q?pQyyVGpB9W9DddPVXssOa/sshxq4Q1uW+YITK9uZmUeLmQwN7mg8xzn0A44a?= =?us-ascii?Q?d3sFh/ZMaAHj8gIvtR0J74r6SZ7pXRqdRhn24LjrFzZI5qzdx3eWw+wOTx26?= =?us-ascii?Q?EjTpkCAVVlw86vlLue/22M6EtFGfYb5KCrXFVWe/9XrqV1uhCqLJrzSD9NfO?= =?us-ascii?Q?28tjY8rL3NdGVdcj6GGri1JqOI8D4saUeckS/Ub6gQJu3eoJwHOJi0XPGGJP?= =?us-ascii?Q?nZ8ZtkxYHXyafKGCx720MOmHqBkO0XWyXmf/kwDB+5w7x+atLwGpKsP4Wy6S?= =?us-ascii?Q?IM9UX0eTTS0HQRbNHrk3iZf3rnT4/VocLPUFrhuo2bBRtebOBYg/qCbMI85p?= =?us-ascii?Q?+tDBzUrvOVm5B9DOrDWenAebmPWUi8U9qxKqKluDqu0cToBjuRAG9rIuZBSB?= =?us-ascii?Q?MQd8L5gJCJpvc9OewX4igR9giNFhtA8Z3B9V7p4IqDwOCkUtbNSFGFtWmRTo?= =?us-ascii?Q?dBUiRRtxOLUsNGSOYhAFl7/oWw5LjYJAy5R3SbgzN4g/G12YLjBgGCiJSYdq?= =?us-ascii?Q?4DrdursUzysFpCWOgMQDEZpYLPSd0HIx153i9USTjaFt5u5Fp/798NOk80IF?= =?us-ascii?Q?PVNtzVcaSmNdTzWEyFfC6k7nbUSwAU44em8x2Xfs29zQJmLfIfqMPC2P8jTf?= =?us-ascii?Q?G8oZQ+56VN1RB64lFIc3H/p58zIoBWYmmbs80aEivR9kXqQMiQMWAetamRER?= =?us-ascii?Q?tYMg4tUnVeMOaUS353e6oxo61m70D7o6ewJ+4WJr6GKuwIYcxWRUFZUn7GK9?= =?us-ascii?Q?mtX8awrwRqGqsneCrQUz0R61rmHSPCRJSbxpVZuYmK3BTgFaN9EeLyxs/DPn?= =?us-ascii?Q?S7NL8kElXQIe93PNIodsvAsbGOUlxVnPyhpgNSxt9NhSkg4xA0x19j5yUBJK?= =?us-ascii?Q?52AQMR4V/sHDiMcu7K+IYEE27aTSgxIpo56WZlsZc+hsdi1wWWaULIyggoTj?= =?us-ascii?Q?IBgSUQ9Wfw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: bf7c8c33-0c53-448b-7978-08de847824c5 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:28.2325 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LgHG+b4nNMmVDd5abZ5AGajxStNWInKHVm7WwRW9r6u08XVBlQElIF0lJGsKc3AREkAHtk0RyvV1HbDGPsSZag== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Add dedicated FB HALs for Hopper (GH100) and Blackwell (GB100) with architecture-specific non-WPR heap sizes. Hopper uses 2 MiB, Blackwell uses 2 MiB + 128 KiB. These are needed for the larger reserved memory regions that Hopper/Blackwell GPUs require. Also adds the non_wpr_heap_size() method to the FbHal trait, and the total_reserved_size field to FbLayout. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fb.rs | 16 ++++++++--- drivers/gpu/nova-core/fb/hal.rs | 16 ++++++++--- drivers/gpu/nova-core/fb/hal/ga102.rs | 2 +- drivers/gpu/nova-core/fb/hal/gb100.rs | 38 +++++++++++++++++++++++++++ drivers/gpu/nova-core/fb/hal/gh100.rs | 38 +++++++++++++++++++++++++++ 5 files changed, 102 insertions(+), 8 deletions(-) create mode 100644 drivers/gpu/nova-core/fb/hal/gb100.rs create mode 100644 drivers/gpu/nova-core/fb/hal/gh100.rs diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index ffb996b918f8..c12705f5f742 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -31,7 +31,7 @@ regs, }; =20 -mod hal; +pub(crate) mod hal; =20 /// Type holding the sysmem flush memory page, a page of memory to be writ= ten into the /// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR*` registers and used to maintain memory= coherency. @@ -99,6 +99,15 @@ pub(crate) fn unregister(&self, bar: &Bar0) { } } =20 +/// Calculate non-WPR heap size based on chipset architecture. +/// This matches the logic used in FSP for consistency. +pub(crate) fn calc_non_wpr_heap_size(chipset: Chipset) -> u64 { + hal::fb_hal(chipset) + .non_wpr_heap_size() + .map(u64::from) + .unwrap_or(usize_as_u64(SZ_1M)) +} + pub(crate) struct FbRange(Range); =20 impl FbRange { @@ -253,9 +262,8 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw:= &GspFirmware) -> Result< }; =20 let heap =3D { - const HEAP_SIZE: u64 =3D usize_as_u64(SZ_1M); - - FbRange(wpr2.start - HEAP_SIZE..wpr2.start) + let heap_size =3D calc_non_wpr_heap_size(chipset); + FbRange(wpr2.start - heap_size..wpr2.start) }; =20 Ok(Self { diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index d33ca0f96417..ebd12247f771 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -12,6 +12,8 @@ =20 mod ga100; mod ga102; +mod gb100; +mod gh100; mod tu102; =20 pub(crate) trait FbHal { @@ -28,14 +30,22 @@ pub(crate) trait FbHal { =20 /// Returns the VRAM size, in bytes. fn vidmem_size(&self, bar: &Bar0) -> u64; + + /// Returns the non-WPR heap size for GPUs that need large reserved me= mory. + /// + /// Returns `None` for GPUs that don't need extra reserved memory. + fn non_wpr_heap_size(&self) -> Option { + None + } } =20 /// Returns the HAL corresponding to `chipset`. -pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal { +pub(crate) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal { match chipset.arch() { Architecture::Turing =3D> tu102::TU102_HAL, Architecture::Ampere if chipset =3D=3D Chipset::GA100 =3D> ga100::= GA100_HAL, - Architecture::Ampere =3D> ga102::GA102_HAL, - Architecture::Ada | Architecture::Hopper | Architecture::Blackwell= =3D> ga102::GA102_HAL, + Architecture::Ampere | Architecture::Ada =3D> ga102::GA102_HAL, + Architecture::Hopper =3D> gh100::GH100_HAL, + Architecture::Blackwell =3D> gb100::GB100_HAL, } } diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-core/= fb/hal/ga102.rs index 734605905031..f8d8f01e3c5d 100644 --- a/drivers/gpu/nova-core/fb/hal/ga102.rs +++ b/drivers/gpu/nova-core/fb/hal/ga102.rs @@ -8,7 +8,7 @@ regs, // }; =20 -fn vidmem_size_ga102(bar: &Bar0) -> u64 { +pub(super) fn vidmem_size_ga102(bar: &Bar0) -> u64 { regs::NV_USABLE_FB_SIZE_IN_MB::read(bar).usable_fb_size() } =20 diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/= fb/hal/gb100.rs new file mode 100644 index 000000000000..bead99a6ca76 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::prelude::*; + +use crate::{ + driver::Bar0, + fb::hal::FbHal, // +}; + +struct Gb100; + +impl FbHal for Gb100 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + super::ga100::read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + super::ga100::write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::ga102::vidmem_size_ga102(bar) + } + + fn non_wpr_heap_size(&self) -> Option { + // 2 MiB + 128 KiB non-WPR heap for Blackwell (see Open RM: kgspCa= lculateFbLayout_GB100). + Some(0x220000) + } +} + +const GB100: Gb100 =3D Gb100; +pub(super) const GB100_HAL: &dyn FbHal =3D &GB100; diff --git a/drivers/gpu/nova-core/fb/hal/gh100.rs b/drivers/gpu/nova-core/= fb/hal/gh100.rs new file mode 100644 index 000000000000..32d7414e6243 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/gh100.rs @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::prelude::*; + +use crate::{ + driver::Bar0, + fb::hal::FbHal, // +}; + +struct Gh100; + +impl FbHal for Gh100 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + super::ga100::read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + super::ga100::write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::ga102::vidmem_size_ga102(bar) + } + + fn non_wpr_heap_size(&self) -> Option { + // 2 MiB non-WPR heap for Hopper (see Open RM: kgspCalculateFbLayo= ut_GH100). + Some(0x200000) + } +} + +const GH100: Gh100 =3D Gh100; +pub(super) const GH100_HAL: &dyn FbHal =3D &GH100; --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011013.outbound.protection.outlook.com [52.101.62.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 487383F8819; Tue, 17 Mar 2026 22:54:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788081; cv=fail; b=fHZFSCokuBS0+GLRO81o4hHv/AbeJEsri0783HKXtlIphHddLELRnw97Dzh7gb3i/btTc6EpPJESScZsuBSvBSbJcCEm7cIScIUZfls2dEohn2CoGwryS7hW9zcMED0Aa6hhTYL+OguiLzGGJzl/eNxsmDqvgKyFeBvsh3Nws2A= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788081; c=relaxed/simple; bh=94FqYvlK2Mnkoz8Qno2s3x7woHE+AibFvga0huCWztI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=mhgVczbER6wXCNh66SuIuC57V7Zu6vu1P3l7qLEhXxVZChggM5h730g/AT9QhyYTgzdZtrTOnWRGN3IZCW+YlW8rnu0aMcOAXtpP528Tpo79Y29c6KEl0xQZwJ/Vzg9u1UeusEcwC5jd5jucJolvc00Gdijjplm/MbjGqUto3L8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=YyIS0G+j; arc=fail smtp.client-ip=52.101.62.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="YyIS0G+j" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=f9dSKB3OKDEs3MXo+W3i9v5XSEJ2zOTOIR7WUYK5ZvWFKpkVTlSRzK/StmnciBYVosypYVJNq5h6GgqX7XV47ZsQva7e5Fie6S+Px2WHr+zs4uIGTWHAgHb4bLEu+BU55nbyN05NVD8kkXA+7mGLO3HtbFNbLiRKTh1VYnd+23YeODcSrU/ZvEPkQjRk17SzxqXB1Ai27GfxdIBq9aGKd+zEpKvSyIPC9HrWAp9hv7uWkYm8Xtc50TeHhKnJ/DAH7klOD1XMITd2TRcXPir58oi1ehRanY558k7KPKTjzsOcGD+fQ+zbpdBwXoEHj76MD1rSOcWyycFKYRqb+72TiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YvfTjUVTcGtGYKs45EbawjgpwxTpwLZtl9Ni4pcA1ZU=; b=Se3fdWEv8cMf714eMiZXqmYJBgTvi88XRBccuupQm3RESOd8dF+6rLEcCLhHuu43PcdD5dPLuC44QPr7y4DUL6d1V4fMtz9usYVM2+JoI4r1DZgxH6fYJThBwhgQI9raYPYq/uIc7fCswatIIFocuqPIYjgsclkK5FDK++RvGPQEAKqKRPGtuQVrBm2J/IOczl4xm9ZvNgtuldzIY2wM3uKgLz5+O8VfJ4oYi9AWq/vfU6XVF/acyGLNRCPyorPpGYOfzNyrvwDypEgeudY2fkNEnLqDqu96HY1VembEuZ4vnTMjguwFFWyJOzbplfo9u+czcNCeefOQhPWhoH2rxg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YvfTjUVTcGtGYKs45EbawjgpwxTpwLZtl9Ni4pcA1ZU=; b=YyIS0G+jryDOC3klN/IjIY1bLn94Qvb3eBL/+f3/44MING0y+iEnjgKRFl8klzPBg3Eq3U4e1WNtZmbZo28O1pP38AEDRfYOvSxvReMY+V/P7c1Z7SOQ6kkuS2gHdQXkMva67tbAaNQYYFVReRwj2pauoTvJYI3XE6SOIX95/9VFtEdQu8Auz7+Tr8DCOIR9vaMr812i4KfHGxdClncqnN+rFVHVunUolBpj4/0YbzThjml8C9ICR98DZEmSKGIcBgO8Hwu7QewNkxS/C96tvP/eHjVKtkwNPQlpEbZlyjfJRuaDcLT+i8Q5vplLr0rcu5ZUbWqGKda9a2C8un9xcQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:54:30 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:30 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 24/31] gpu: nova-core: Hopper/Blackwell: add FSP Chain of Trust boot Date: Tue, 17 Mar 2026 15:53:48 -0700 Message-ID: <20260317225355.549853-25-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY3PR03CA0011.namprd03.prod.outlook.com (2603:10b6:a03:39a::16) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: 334dc8c0-31ed-4278-1439-08de847825cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: nPxj07Ns7QD5GKdYQ3YZ+tY3Zm6/4pg/sBHc4Zi2xb4knj6VThAuYgrtZzNVcZMV/2VKUHOFCcDiMwHMpViFKJZxOHShu6ZTz0VdkRYgFTR39f5asuWoAs0bEVc0JJEotVG91HTBeld6nF0js+MNYBUQxozumuGpdSxW3psmOHy7RC7oOY9gnUHhIAQFIlGvBNgs6/6yXljSg6AO9Zf7Rw0QWJieSFvs6sIDBT7jY53FBv9OiyrapCJsVW/Fm1wHJprX2sUBXBu1XEnG8mYctOs6onFFZH/YVH+3pRVXIXvJQGIrWrz1YXcqsHZuDHYzi7Kc3SVwVnu1tRS3qiFpw8w+crXmUS6vaDJ/G+/MR3+QDU1szyD9IhNjxW2bXiTJQL8pNiuBf8P0lDWjxuGPZMHBYG/JfNZMLZQKVRlVDaYgGMcpK534v6/F/qhzpnFcr9ShaIxvwJY6PL532xtFIh0fJ6N54DYXrnT12d209tHpBcqGz7+GyErCJx4nyq0IKx5STtY9AJESu2nkiupqlwoSUcyvK5NT2dgGZpgBCtve0LS/vUsVE2wjKoVZssKwAZzQKsRHkXU0LDq2QJrOWLNGPIuNMDCrqinOLpH+XM+YkFgARupybh1wdGMehrR/tM02hF/qHPMA98a8kQiKjvpAI9shp4atTs1fUMmIhuCieSQfqGQWFlKf50k4cUGTQGzglLbbzameU0MGfcV3yVMNQnkmEU1jzmfjg2104ik= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?x6LR7JJqcFJdgHIYy/eZGuvLg3Vnl0cosMqSLcgo/HeSBKQS6qNCjf3mI+Be?= =?us-ascii?Q?VRiy4bIdw8/LAUkJpzofTKqaYull2M/fdWTy9Le4jx+QxIjHYRd3kjXeeZw7?= =?us-ascii?Q?MuFPiwXIs3VFDKkGX4B1Grz7/CCWw7gxzV1H9iMLx3c+Ut+qD0UPTcZrmNqs?= =?us-ascii?Q?jJ39kkpqej3tMw8pq1uzNgY9ZGTBvslPSN1WO9dUzzVaNHN5Saw/UvCgucSm?= =?us-ascii?Q?JRJC1AWSxmOpvvflyoaqNjShenpuedz/FcPeG8YsExjmuAGndxojA6iXvs0R?= =?us-ascii?Q?SU53O6JLv+2HZVz5F960YEMnWCgKzis+tkSwHt17w+KX+xJLg/n4lZtnEv2t?= =?us-ascii?Q?79sOiTPjPHRxmqeYome7eWyzqNkQxrXnuqnw4bEezcSM9+GKlvGA5zIDOuzR?= =?us-ascii?Q?hFteGqqUlMCT3cVDNYVQL51LtgvG3fcjJXHnkz27Z80d0gg5jqwX2mDlE9Ls?= =?us-ascii?Q?hIIt4D1pBs1p5MLilmGTNJljif+QeQLO273rj1XVO5C7Rk7xUGmVG1ozyvdn?= =?us-ascii?Q?WULmrLN/A5gA0248v7Z4wOSl3j4OfpzbAnz41jy7kLwH21R8EFVOW0FaPiOg?= =?us-ascii?Q?iVxzKtbB5BgODkmaDd8JlciFTTcOa8955TukJV2ynbBwCjmcuZn7XO6IeX2M?= =?us-ascii?Q?avXtrWKLPagiaVwBwMh1jhSIifNa13RRJR7esaDUOD0jZsaH67oND6PB+4H0?= =?us-ascii?Q?V/tb3k+ZqcbF2V9tCkq1LStkFIjWLIQ1cHMO911S3m9eWfktpPGQTc1YpNQq?= =?us-ascii?Q?tvEPY3levxBxd768lbh9kQf03EUuQB1PLRra2EG2X61vGj6ze/VQ/8YcuFz3?= =?us-ascii?Q?Kut2H/oPrUG0DOrNImag1Fx9iF7Xdy3LmBuNqZDS4y4Sg590tC7x8AEARqHw?= =?us-ascii?Q?KMTovJClY/BT8gNsCaxbDFKrtR+EKZ3DO5Ej8aqma10UoGCNoCTs+jpFOqm7?= =?us-ascii?Q?tMRbNrQhwZd7KE+6+dYcNt3574cfKR5MlGI2PEHyDYr0HnPN6zsi9eFDx5Om?= =?us-ascii?Q?QacRpX5tpmpVlC8ZY+srs7NhoqF286hVEonws1X+h5pB4I0Vc1oIamXdbKkq?= =?us-ascii?Q?LU5ItpdUHDg9fCIgIT7cLfFFaBpALbmiQL/frpKqV1WrSZvhtKqiW9T8bTdD?= =?us-ascii?Q?jbnnkZp4kyteViLD0rLyjBcCYOYDCVa4fodrSawqvBuHBXM2FA2P6qIAkwOr?= =?us-ascii?Q?mP+tfFdQfTZdyfzmtIThaAjsMDz5ltue/7Q5pybbT3mgR9+kAUP09g5Fp53f?= =?us-ascii?Q?JQlY7jepGxwpjkzljxtHV+axGqzteLDlM7wI+Z8jgAXKQxkZQXJVyyDs5ujI?= =?us-ascii?Q?feX6NyhJPv4Uxcz10etaYjQ1KpDvnYavAMHjZDUutIhocSBA8+0LsqXmugWg?= =?us-ascii?Q?g0PyRx/YvGCgXkg83zpOyXoDIuhq6XjU6PIk8IHgo7yssApMY8xJjY/IyjnX?= =?us-ascii?Q?/oFqsSWT/TAPNwQFPudaL2C/zSgoZ3UoinI/2FboRuApDHSOnc23aSwMP2/n?= =?us-ascii?Q?trSrq08dm0GrXB8M2ojy/RI3pSkSdypj/EvsAllPYtjynqiRtxFhHgFbNj9F?= =?us-ascii?Q?+S8BnjlXUCAr6UiHhV8RFItiy+X43C3YvL4k0XWHbaEM80PCY4uSxvt7MZCX?= =?us-ascii?Q?rafRihQvQYMyAgUEuhAHjiXclWenzYbgnL/UGCNtBug86Fv6ue7+J6HFbTXI?= =?us-ascii?Q?eMNEKKNfH3dvH+CjNu9m4iNLUAXEvqRcgfia/53ekI26+6ZDX/enRTF4jY9S?= =?us-ascii?Q?+RZ8/iDhfg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 334dc8c0-31ed-4278-1439-08de847825cf X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:29.9798 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MTxCr0f28WSn7bC3Ajfg70O+QPGA2t4PIAnIWI4XpFirZqncRWui4Ofk5xf4pdw18YGolp/Oqc01iYY+ziyafQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Add boot_fmc() which builds and sends the Chain of Trust message to FSP, and FmcBootArgs which bundles the DMA-coherent boot parameters that FSP reads at boot time. The FspFirmware struct fields become pub(crate) and fmc_full changes from DmaObject to KVec for CPU-side signature extraction. Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware/fsp.rs | 12 +- drivers/gpu/nova-core/fsp.rs | 174 +++++++++++++++++++++++++- drivers/gpu/nova-core/gpu.rs | 1 - drivers/gpu/nova-core/mctp.rs | 7 -- 4 files changed, 179 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/nova-core/firmware/fsp.rs b/drivers/gpu/nova-core/= firmware/fsp.rs index 5aedee8e6d41..e5059d59a4b7 100644 --- a/drivers/gpu/nova-core/firmware/fsp.rs +++ b/drivers/gpu/nova-core/firmware/fsp.rs @@ -14,24 +14,22 @@ gpu::Chipset, // }; =20 -#[expect(unused)] +#[expect(dead_code)] pub(crate) struct FspFirmware { /// FMC firmware image data (only the "image" ELF section). - fmc_image: DmaObject, + pub(crate) fmc_image: DmaObject, /// Full FMC ELF data (for signature extraction). pub(crate) fmc_full: KVec, } =20 impl FspFirmware { - #[expect(unused)] + #[expect(dead_code)] pub(crate) fn new( dev: &device::Device, chipset: Chipset, ver: &str, ) -> Result { let fw =3D super::request_firmware(dev, chipset, "fmc", ver)?; - let mut fmc_full =3D KVec::with_capacity(fw.data().len(), GFP_KERN= EL)?; - fmc_full.extend_from_slice(fw.data(), GFP_KERNEL)?; =20 // FSP expects only the "image" section, not the entire ELF file. let fmc_image_data =3D elf::elf_section(fw.data(), "image").ok_or_= else(|| { @@ -39,6 +37,10 @@ pub(crate) fn new( EINVAL })?; =20 + // Copy the full ELF into a kernel vector for CPU-side signature e= xtraction. + let mut fmc_full =3D KVec::with_capacity(fw.data().len(), GFP_KERN= EL)?; + fmc_full.extend_from_slice(fw.data(), GFP_KERNEL)?; + Ok(Self { fmc_image: DmaObject::from_data(dev, fmc_image_data)?, fmc_full, diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index 18edf7a1a8e4..68bcfe45aec6 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -8,8 +8,14 @@ =20 use kernel::{ device, + dma::CoherentAllocation, io::poll::read_poll_timeout, prelude::*, + ptr::{ + Alignable, + Alignment, // + }, + sizes::{SZ_1M, SZ_2M}, time::Delta, transmute::{ AsBytes, @@ -38,7 +44,6 @@ pub(crate) const fn new(version: u16) -> Self { } =20 /// Return the raw protocol version number for the wire format. - #[expect(dead_code)] pub(crate) const fn raw(self) -> u16 { self.0 } @@ -156,6 +161,35 @@ struct NvdmPayloadCommandResponse { error_code: u32, } =20 +/// NVDM (NVIDIA Device Management) COT (Chain of Trust) payload structure. +/// This is the main message payload sent to FSP for Chain of Trust. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct NvdmPayloadCot { + version: u16, + size: u16, + gsp_fmc_sysmem_offset: u64, + frts_sysmem_offset: u64, + frts_sysmem_size: u32, + frts_vidmem_offset: u64, + frts_vidmem_size: u32, + hash384: [u8; FSP_HASH_SIZE], + public_key: [u8; FSP_PKEY_SIZE], + signature: [u8; FSP_SIG_SIZE], + gsp_boot_args_sysmem_offset: u64, +} + +/// Complete FSP message structure with MCTP and NVDM headers. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct FspMessage { + mctp_header: u32, + nvdm_header: u32, + cot: NvdmPayloadCot, +} + +// SAFETY: FspMessage is a packed C struct with only integral fields. +unsafe impl AsBytes for FspMessage {} /// Complete FSP response structure with MCTP and NVDM headers. #[repr(C, packed)] #[derive(Clone, Copy)] @@ -176,6 +210,84 @@ pub(crate) trait MessageToFsp: AsBytes { /// NVDM type identifying this message to FSP. const NVDM_TYPE: u32; } + +impl MessageToFsp for FspMessage { + const NVDM_TYPE: u32 =3D NvdmType::Cot as u32; +} + +/// Bundled arguments for FMC boot via FSP Chain of Trust. +pub(crate) struct FmcBootArgs<'a> { + chipset: crate::gpu::Chipset, + fmc_image_fw: &'a crate::dma::DmaObject, + fmc_boot_params: CoherentAllocation, + resume: bool, + signatures: &'a FmcSignatures, +} + +impl<'a> FmcBootArgs<'a> { + /// Build FMC boot arguments, allocating the DMA-coherent boot paramet= er + /// structure that FSP will read. + #[expect(dead_code)] + #[allow(clippy::too_many_arguments)] + pub(crate) fn new( + dev: &device::Device, + chipset: crate::gpu::Chipset, + fmc_image_fw: &'a crate::dma::DmaObject, + wpr_meta_addr: u64, + wpr_meta_size: u32, + libos_addr: u64, + resume: bool, + signatures: &'a FmcSignatures, + ) -> Result { + // `GSP_DMA_TARGET_*` is not in the current Rust bindings yet. + const GSP_DMA_TARGET_COHERENT_SYSTEM: u32 =3D 1; + const GSP_DMA_TARGET_NONCOHERENT_SYSTEM: u32 =3D 2; + + let fmc_boot_params =3D CoherentAllocation::::al= loc_coherent( + dev, + 1, + GFP_KERNEL | __GFP_ZERO, + )?; + + // Blackwell FSP expects wpr_carveout_offset and wpr_carveout_size= to be zero; + // it obtains WPR info from other sources. + kernel::dma_write!( + fmc_boot_params, + [0]?.boot_gsp_rm_params, + GspAcrBootGspRmParams { + target: GSP_DMA_TARGET_COHERENT_SYSTEM, + gsp_rm_desc_size: wpr_meta_size, + gsp_rm_desc_offset: wpr_meta_addr, + b_is_gsp_rm_boot: 1, + ..Default::default() + } + ); + + kernel::dma_write!( + fmc_boot_params, + [0]?.gsp_rm_params, + GspRmParams { + target: GSP_DMA_TARGET_NONCOHERENT_SYSTEM, + boot_args_offset: libos_addr, + } + ); + + Ok(Self { + chipset, + fmc_image_fw, + fmc_boot_params, + resume, + signatures, + }) + } + + /// DMA address of the FMC boot parameters, needed after boot for lock= down + /// release polling. + #[expect(dead_code)] + pub(crate) fn boot_params_dma_handle(&self) -> u64 { + self.fmc_boot_params.dma_handle() + } +} /// FSP interface for Hopper/Blackwell GPUs. pub(crate) struct Fsp; =20 @@ -277,8 +389,66 @@ pub(crate) fn extract_fmc_signatures( Ok(signatures) } =20 - /// Send message to FSP and wait for response. + /// Boot GSP FMC via FSP Chain of Trust. + /// + /// Builds the COT message from the pre-configured [`FmcBootArgs`], se= nds it + /// to FSP, and waits for the response. #[expect(dead_code)] + pub(crate) fn boot_fmc( + dev: &device::Device, + bar: &crate::driver::Bar0, + fsp_falcon: &crate::falcon::Falcon, + args: &FmcBootArgs<'_>, + ) -> Result { + dev_dbg!(dev, "Starting FSP boot sequence for {}\n", args.chipset); + + let fmc_addr =3D args.fmc_image_fw.dma_handle(); + let fmc_boot_params_addr =3D args.fmc_boot_params.dma_handle(); + + // frts_offset is relative to FB end: FRTS_location =3D FB_END - f= rts_offset + let frts_offset =3D if !args.resume { + let frts_reserved_size =3D crate::fb::calc_non_wpr_heap_size(a= rgs.chipset) + .checked_add(u64::from(crate::fb::PMU_RESERVED_SIZE)) + .ok_or(EINVAL)?; + + frts_reserved_size + .align_up(Alignment::new::()) + .ok_or(EINVAL)? + } else { + 0 + }; + let frts_size: u32 =3D if !args.resume { SZ_1M as u32 } else { 0 }; + + let msg =3D KBox::new( + FspMessage { + mctp_header: MctpHeader::single_packet().raw(), + nvdm_header: NvdmHeader::new(NvdmType::Cot).raw(), + + cot: NvdmPayloadCot { + version: args.chipset.fsp_cot_version().ok_or(ENOTSUPP= )?.raw(), + size: u16::try_from(core::mem::size_of::()) + .map_err(|_| EINVAL)?, + gsp_fmc_sysmem_offset: fmc_addr, + frts_sysmem_offset: 0, + frts_sysmem_size: 0, + frts_vidmem_offset: frts_offset, + frts_vidmem_size: frts_size, + hash384: args.signatures.hash384, + public_key: args.signatures.public_key, + signature: args.signatures.signature, + gsp_boot_args_sysmem_offset: fmc_boot_params_addr, + }, + }, + GFP_KERNEL, + )?; + + Self::send_sync_fsp(dev, bar, fsp_falcon, &*msg)?; + + dev_dbg!(dev, "FSP Chain of Trust completed successfully\n"); + Ok(()) + } + + /// Send message to FSP and wait for response. fn send_sync_fsp( dev: &device::Device, bar: &crate::driver::Bar0, diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 1d25513fef20..066bf1e03652 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -139,7 +139,6 @@ pub(crate) const fn needs_fwsec_bootloader(self) -> boo= l { /// /// Hopper (GH100) uses version 1, Blackwell uses version 2. /// Returns `None` for architectures that do not use FSP. - #[expect(dead_code)] pub(crate) const fn fsp_cot_version(&self) -> Option { match self.arch() { Architecture::Hopper =3D> Some(FspCotVersion::new(1)), diff --git a/drivers/gpu/nova-core/mctp.rs b/drivers/gpu/nova-core/mctp.rs index 9e052d916e79..c23e8ec69636 100644 --- a/drivers/gpu/nova-core/mctp.rs +++ b/drivers/gpu/nova-core/mctp.rs @@ -6,8 +6,6 @@ //! Device Management) messages between the kernel driver and GPU firmware //! processors such as FSP and GSP. =20 -#![expect(dead_code)] - /// NVDM message type identifiers carried over MCTP. #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u8)] @@ -101,11 +99,6 @@ pub(crate) fn nvdm_type(self) -> core::result::Result { NvdmType::try_from(self.raw_nvdm_type()) } =20 - /// Extract the NVDM type field as a raw value. - pub(crate) fn nvdm_type_raw(self) -> u32 { - u32::from(self.raw_nvdm_type()) - } - /// Set the NVDM type field from a typed value. pub(crate) fn set_nvdm_type(self, nvdm_type: NvdmType) -> Self { self.set_raw_nvdm_type(u8::from(nvdm_type)) --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011036.outbound.protection.outlook.com [52.101.57.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D079734104E; Tue, 17 Mar 2026 22:54:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.57.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788083; cv=fail; b=SCGifFOSuA7XtUin1Dx0iTwkT+l/4SeRdTLpwzmi2rSBCOf/vwdqjvdiAfUeq68CEFmVWpWs0w8PYaQGpa04STn/O1RpaWs5VxhQAwCm0BxHyrhXVjo0aUTJW+qm8TkbAo4FkOEri9yZpWsnW3/PvgmrGaIxmYWSRy/LjtLm7Ms= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788083; c=relaxed/simple; bh=Ufz7b/XV1g//18kWIUv87DdzYvjoXfoVha6VKFVrgnE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=VVttLb5mjdkjGCPpiphSJUphHOF//8tU7hDhYD0VNxU0JO3znPS+W9V88BtmRt/I6w/+Vp0T4lThAJUNHULvxrliMxiQh9SDQLJDSFp+IvbbIAxuMGB5AgFNj9h/QBsZG0e0BkkVS0dBue9L7jtoEuHiVUCtgySbJwNEmzvPgEc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=LwaQZZtp; arc=fail smtp.client-ip=52.101.57.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="LwaQZZtp" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=d42yQXV07hnQKHXsOZFIP5irw9O8cyfZquopz4876MuWXSs9MoXSC3mnR0SMNs9pBJRWCHvaXEZUyC48KDs+nNq9PQnbJHbYDvesVoO9DU8wl/6gnPbJt2pmvA7IUQOya8q9lmj17OOwdxMKqHzVM+Pt40c477/6p2RpCMTmo9YSdKK/Fkd+yMoBveOxnXEhDBo5LBwIRrhK/a5mri8KQIp0cby48Y7tzPUD9QFl1hMqmapbT7gUThsYIe+FruNOZmvjMnnCMbbttqKfaqM3zMCVQmCIdHGWL9b6fUXYM83ac3UM7IGTX1lFE2x5S2MIGtcot86PG9E0fVOJZs4MlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=X7RkJngPWVDn3zMnW4gjU7NsTWpAbeVZ9uQC40Aafjc=; b=amQfQlgX7d/IMreVBjW4kuW6oIkTwO/lzwzxXq22VVkBCvmo5BHapU0Z1XE5B1Jh6cwZ+ozeII01tVJEwRNRQwFKaTCeQQhCUoOVqGoZ7G1nW/1C7TPr5KAi+SzGRru9Ow9SypHkZC/wFTd4DF/rQwWIjv1UYiwqcOzgIbJOzUuBjnCqkxvJbBPolFfhGFN1p38QwMNaN2j2unycPtE+3gX1X47u3HtK0lT+Tta0TxUn47oiFSTjg5HeSw47nGQhfpX8Ez3f3Ia0kNwfube5tQtOqMPLEFmONgSNdBG/MjZHBtO3J34fDD/YMrRiAmDLxMRaOhJ0AX31gLKpQ85+Iw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=X7RkJngPWVDn3zMnW4gjU7NsTWpAbeVZ9uQC40Aafjc=; b=LwaQZZtpOhiu018BkdMsb811PpSH847g3C1fRLMq0QbIZQ+SzxPianzJ1/afNorCoZJCHy3XiO78x+aV/2bIG4W9anFMiyFwit+C5aCAcVeJFC4A9PFR4nek/9tfuBGsLNHfyX2DD1G5iYlKGPm1dixnSeNXw6ANdytDkTbmTbRwZB+rrQearpiGy35kjJFJ5n4OEVlE//8MLJ4ml2Zs+IL409XHRclOWlzrZHkY+zX/igKqpAY/t+Hlgd9lAIsLF/g+tqa2UkmhvWw5dNWMWSFHf65zqrt5NVnwnI7Q5PQlWFrEmvKhziSEphSLtqXpNkGs7yDzY4BHK7s/PZvKrQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:54:31 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:31 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 25/31] gpu: nova-core: Blackwell: use correct sysmem flush registers Date: Tue, 17 Mar 2026 15:53:49 -0700 Message-ID: <20260317225355.549853-26-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY3PR03CA0016.namprd03.prod.outlook.com (2603:10b6:a03:39a::21) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: bb64c1e9-d717-416c-ac18-08de8478269d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: /5wz+Z/h6MWWsUoIjR4RNvsv+MJEJqUPoF58wrw3S8aN4LZsxrUNJNibl4afscB2cGNFvg59agr4nIjrUDoaK8vMiBvE5JKwbV3uwmdluMAf2US5Ng0CE07GAeVBy99vhOID4M3I6WXFq+6FtWcz3+ttVCdWcsbVG8HUY5khQMBjU0Tz8Sdl1Dy228SbUIZY0mB0hK3Rn+bILg+W+NS/j0XWEUbOLbDRi8CSzWtgu/ecuusjROnQKq3fJ13NeifSm984YzVp9IgHWlAWO9pG+MQd1AST6I03akIF8YdROa6iR6tK2I/P1HrqSX9aRlM5wgkUUv1/C7J0i1wFfEZ0/37NWWyd0QudBeCgRGZvwh40cm5A3qw/+N8jLjECL3oaEeUb79hn0eh5HVhx9D/XSdZhOLYsNBXZBBcsp0Xw8yDZQPzVGZSDK3RozbDgx9VoZRf9S2WyeC/B5lzNUaBf63MdZsXpTCI5ki+l9+su0uwaEwkeG9vWeZn7N/JCFinuHg6uGpwwDeQ9bWjThsdE1dP9OU39ctvWhXsepHmQdb0L9RJCozQfgwEDqIh9qrrCLG0OuAAuvRqkxuclZH5aMNDBz/VUIPTk/HoSOKPCvbIQfe0cmKy8DV81gT6XuaSFJHRknKsXqfkpqHMh051bdpFfFtz5S8TVF6vElHRFYhKvhw8NqLgFyCvZPxs5TMpMyrY2GH+h6KmV3bAqKBl1pW+aQDmd1ckGKMm4ORh5x9Q= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?0TxJI580HWXtHCs8tJAvFT71otYOFFHMNUCasaH7JSZ3YciBKYBXSrb6AZJC?= =?us-ascii?Q?iB7mbs+LfBqF3gHDtfiw8mXry0XZYvCzJas/qJztZ7KD9KQNrV5xBWH1hanf?= =?us-ascii?Q?UC2Mn5NWfvg8Z4caqmk51+gAb9IjqMadyyazXGsBNeWY0pZKoCrvZPXqqr16?= =?us-ascii?Q?M2A7Zyl8XeJQqscPAX2QXIslbUjuhlYXALoyr+DJVFAbRSwRRCmjjIFA+Erf?= =?us-ascii?Q?j3+b/zixhFa2HvhpHx8oi7WlYSJoQUQ1dYXsQt3MvOxehYytKcXB0R4xQ9nz?= =?us-ascii?Q?PW3bwk8WbVKsUnZpCx8RBnaIRdyD7eFg+k2mSIJ7BS6bM2G8+oebb3GTEySI?= =?us-ascii?Q?VctsWkVTccmlhLp5y39B7nuj9IcN0sGSPIg81P207Zbi/ppRXZSekN/1o2xY?= =?us-ascii?Q?F2DBhzKKBPPnythv+9UjpCstC3ofKWj7ga78aa1UIK4CjaCs+16soleQAa4S?= =?us-ascii?Q?xjApnUuycvUAyULkhsBLNG9XldvTXO4CxgbbUAkLU4q3aAuVaiCYJ3wUKz8N?= =?us-ascii?Q?nf+V4YYD0nCtaE371wEJZIm/5ZrF+4xev+X5rpIsueVyQ6R4dxqk2fsZ+24j?= =?us-ascii?Q?384R/ek3I4Bo04UuZyVgH3ULnBCat2JYTiMVUaK18ds0aigyi+DB33Xq/Php?= =?us-ascii?Q?Ep9eC+4IQ7l3Rfm3wzFj5CSZu7G0iTJQNc3G6foWDiV9MS7hw7Kj0KJDEXws?= =?us-ascii?Q?pJW4ygNIQOgdvzs6YCMnxhO5w0pKaUlLaCU+Fv3E7v0NwovGoXeQHlNuiBGK?= =?us-ascii?Q?fpwl6u3NRHoxUv4dR8jT6+yGapz8epdk1zzR1pZxe+rwiLburDd3gnnyhoiF?= =?us-ascii?Q?4WZoZTKFt5P+w2b+PqNDk5O6GumAfDrY2JNt5EOApfc+lJx2ls1AOf22VA4X?= =?us-ascii?Q?cPyyZ8AKGarxmwaoXmU4LhbkjUS64EQ5aS1glLuHVZmrvoNH5ARtFbEvyoEL?= =?us-ascii?Q?iI3VLSb4DXf7QqXxAZA7Xax6fCmTtwh2NAtBw5XdRiG5dAc0+uJSOjN5FV2e?= =?us-ascii?Q?HtGK3BnjQ1ICRsLXSqW6bn0Hn0NX42wZU/PBIRDHy7Kuhk0OllPBE9M3L53o?= =?us-ascii?Q?taFhq3bvjBMVRPa+pIk08ffsHcKYSsp8ucpZSQ/CYBOIW/Gj+scFifylnf3k?= =?us-ascii?Q?GIhGUv0y3DK134dtTbQN3Rn3gCxEAerC5zrXQRNR2QocoZZkLnt2g2VWCrvP?= =?us-ascii?Q?ibaXNn5cCGC3Bkm0N79UmsHn9UBcvEc3hhKnLuofIszOK888F8v2PXXKir9y?= =?us-ascii?Q?yt9s66eZydO9nf4LYdoGiNMbPcRzLiTKrJd+Uz6BRx//6AHgtct3jBPV9lcE?= =?us-ascii?Q?IZKLM+MedV+iw8GRGHCYD18L+wYDug4QTNqe73wU9zQ8NK5envbaFzfVdXbW?= =?us-ascii?Q?P7ugH4fvgv8YHxz0YC1fIprmuHbPTdg7qywFZBv3vO8XJzvHp21prOCRcvfY?= =?us-ascii?Q?v2sBfp+E+3qGPixQBm8DYJnpA2Lrc6VxCqwcaBqCf8PIW7nFuaFz8fnWgOSO?= =?us-ascii?Q?EDp4d4/J9A++moXKQSOGIcKSXb+WovK8WbJXhLpDpXUr7PTmLLdDVVF7xoyP?= =?us-ascii?Q?vfZ1Qcm4ShRNixeB8YsaCcLT3VpaB8PzA+hKguEtky9M4a6+ChVsS3K99vCs?= =?us-ascii?Q?ErY8n1i8OBwkDWc/6c2YhLHWyrtfX35WJQShJuPuwo1tAd+QNSDw9Q80czgd?= =?us-ascii?Q?0tM8MaAoBambu7/8Kn7kE18Sl74ljxy18J0bALs/YXSKXioWXQ6HASDBlm96?= =?us-ascii?Q?KhgtjEuP7A=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: bb64c1e9-d717-416c-ac18-08de8478269d X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:31.3410 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WzRJh8hqufQPOKLdj5htIJ4l9To8BQ3YQYu3iaGN1dMW7R/3tiIuGaXjLPt2g1vsrv3T8IwUM+D8zwfKIPHbdw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Blackwell GPUs moved the sysmem flush page registers away from the legacy NV_PFB_NISO_FLUSH_SYSMEM_ADDR used by Ampere/Ada. GB10x uses HSHUB0 registers, with both a primary and EG (egress) pair that must be programmed to the same address. GB20x uses FBHUB0 registers. Add separate GB100 and GB202 fb HALs, and split the Blackwell HAL dispatch so that each uses its respective registers. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fb/hal.rs | 10 ++++- drivers/gpu/nova-core/fb/hal/gb100.rs | 47 +++++++++++++++++--- drivers/gpu/nova-core/fb/hal/gb202.rs | 62 +++++++++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 36 ++++++++++++++++ 4 files changed, 149 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/nova-core/fb/hal/gb202.rs diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index ebd12247f771..844b00868832 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -13,9 +13,14 @@ mod ga100; mod ga102; mod gb100; +mod gb202; mod gh100; mod tu102; =20 +/// Non-WPR heap size for Blackwell (2 MiB + 128 KiB). +/// See Open RM: kgspCalculateFbLayout_GB100. +const BLACKWELL_NON_WPR_HEAP_SIZE: u32 =3D 0x220000; + pub(crate) trait FbHal { /// Returns the address of the currently-registered sysmem flush page. fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64; @@ -46,6 +51,9 @@ pub(crate) fn fb_hal(chipset: Chipset) -> &'static dyn Fb= Hal { Architecture::Ampere if chipset =3D=3D Chipset::GA100 =3D> ga100::= GA100_HAL, Architecture::Ampere | Architecture::Ada =3D> ga102::GA102_HAL, Architecture::Hopper =3D> gh100::GH100_HAL, - Architecture::Blackwell =3D> gb100::GB100_HAL, + Architecture::Blackwell =3D> match chipset { + Chipset::GB100 | Chipset::GB102 =3D> gb100::GB100_HAL, + _ =3D> gb202::GB202_HAL, + }, } } diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/= fb/hal/gb100.rs index bead99a6ca76..831a058a388b 100644 --- a/drivers/gpu/nova-core/fb/hal/gb100.rs +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs @@ -1,21 +1,59 @@ // SPDX-License-Identifier: GPL-2.0 =20 +//! Blackwell GB10x framebuffer HAL. +//! +//! GB10x GPUs use HSHUB0 registers for the sysmem flush page. Both the pr= imary and EG (egress) +//! register pairs must be programmed to the same address, as required by = hardware. + use kernel::prelude::*; =20 use crate::{ driver::Bar0, - fb::hal::FbHal, // + fb::hal::FbHal, + regs, // }; =20 struct Gb100; =20 +fn read_sysmem_flush_page_gb100(bar: &Bar0) -> u64 { + let lo =3D u64::from(regs::NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO::re= ad(bar).adr()); + let hi =3D u64::from(regs::NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI::re= ad(bar).adr()); + + lo | (hi << 32) +} + +fn write_sysmem_flush_page_gb100(bar: &Bar0, addr: u64) { + // CAST: lower 32 bits. Hardware ignores bits 7:0. + let addr_lo =3D addr as u32; + // CAST: upper 32 bits, then masked to 20 bits by the register field. + let addr_hi =3D (addr >> 32) as u32; + + // Write HI first. The hardware will trigger the flush on the LO write. + + // Primary HSHUB pair. + regs::NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI::default() + .set_adr(addr_hi) + .write(bar); + regs::NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO::default() + .set_adr(addr_lo) + .write(bar); + + // EG (egress) pair -- must match the primary pair. + regs::NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_HI::default() + .set_adr(addr_hi) + .write(bar); + regs::NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_LO::default() + .set_adr(addr_lo) + .write(bar); +} + impl FbHal for Gb100 { fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { - super::ga100::read_sysmem_flush_page_ga100(bar) + read_sysmem_flush_page_gb100(bar) } =20 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { - super::ga100::write_sysmem_flush_page_ga100(bar, addr); + write_sysmem_flush_page_gb100(bar, addr); =20 Ok(()) } @@ -29,8 +67,7 @@ fn vidmem_size(&self, bar: &Bar0) -> u64 { } =20 fn non_wpr_heap_size(&self) -> Option { - // 2 MiB + 128 KiB non-WPR heap for Blackwell (see Open RM: kgspCa= lculateFbLayout_GB100). - Some(0x220000) + Some(super::BLACKWELL_NON_WPR_HEAP_SIZE) } } =20 diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-core/= fb/hal/gb202.rs new file mode 100644 index 000000000000..2a4c3e7961b2 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Blackwell GB20x framebuffer HAL. +//! +//! GB20x GPUs moved the sysmem flush registers from `NV_PFB_NISO_FLUSH_SY= SMEM_ADDR` to +//! `NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_{LO,HI}`. + +use kernel::prelude::*; + +use crate::{ + driver::Bar0, + fb::hal::FbHal, + regs, // +}; + +struct Gb202; + +fn read_sysmem_flush_page_gb202(bar: &Bar0) -> u64 { + let lo =3D u64::from(regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO::re= ad(bar).adr()); + let hi =3D u64::from(regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI::re= ad(bar).adr()); + + lo | (hi << 32) +} + +fn write_sysmem_flush_page_gb202(bar: &Bar0, addr: u64) { + // Write HI first. The hardware will trigger the flush on the LO write. + regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI::default() + // CAST: upper 32 bits, then masked to 20 bits by the register fie= ld. + .set_adr((addr >> 32) as u32) + .write(bar); + regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO::default() + // CAST: lower 32 bits. Hardware ignores bits 7:0. + .set_adr(addr as u32) + .write(bar); +} + +impl FbHal for Gb202 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + read_sysmem_flush_page_gb202(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + write_sysmem_flush_page_gb202(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::ga102::vidmem_size_ga102(bar) + } + + fn non_wpr_heap_size(&self) -> Option { + Some(super::BLACKWELL_NON_WPR_HEAP_SIZE) + } +} + +const GB202: Gb202 =3D Gb202; +pub(super) const GB202_HAL: &dyn FbHal =3D &GB202; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 183915a3bb31..e70be122e1c9 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -116,6 +116,42 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> k= ernel::fmt::Result { 23:0 adr_63_40 as u32; }); =20 +// Blackwell GB10x sysmem flush registers (HSHUB0). +// +// GB10x GPUs use two pairs of HSHUB registers for sysmembar: a primary pa= ir and an EG +// (egress) pair. Both must be programmed to the same address. Hardware ig= nores bits 7:0 +// of each LO register. HSHUB0 base is 0x00891000. + +register!(NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO @ 0x00891e50 { + 31:0 adr as u32; +}); + +register!(NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI @ 0x00891e54 { + 19:0 adr as u32; +}); + +register!(NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_LO @ 0x008916c0 { + 31:0 adr as u32; +}); + +register!(NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_HI @ 0x008916c4 { + 19:0 adr as u32; +}); + +// Blackwell GB20x sysmem flush registers (FBHUB0). +// +// Unlike the older NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers which encode t= he address with an +// 8-bit right-shift, these registers take the raw address split into lowe= r/upper 32-bit halves. +// The hardware ignores bits 7:0 of the LO register. + +register!(NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO @ 0x008a1d58 { + 31:0 adr as u32; +}); + +register!(NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI @ 0x008a1d5c { + 19:0 adr as u32; +}); + register!(NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE @ 0x00100ce0 { 3:0 lower_scale as u8; 9:4 lower_mag as u8; --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011013.outbound.protection.outlook.com [52.101.62.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B0953FD125; Tue, 17 Mar 2026 22:54:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788084; cv=fail; b=lcYr35WNRlFEZuEzPNtuMZBhrCr5D+rN3Oi5K7NMBVAjXCR1jCqjG3do5Z1mvtxKsxlnMj16zP8zMnWLvhfpEToLfS0JaF0S/5R+hN1jl56qtC0VaxOLnx5CNep0Gd/oT5z303t3tFXbmJ0DRlJA5JliiOvEatyOv/ye/B3yzXo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788084; c=relaxed/simple; bh=dW6hgLdw/5hpqM/XtREXFt1qnjVxpCzZW9VWK8wmYfI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=uCiBF52EOIh1IYyNw3Xjw8yMU3GQlJMwoWf+R44MCmNGxLZEpvvRR2r6vqZ0ux9OEZYlFuK0L6ATju+axi6yS3Mw87ECBCDd9sOvt9qI8H9R7FCxptCuek3wjUxaI5GYCnvHjG1zSgkbPHEAUuWHu4nv5O/c8Q8GZ4DR++1fNXI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=XlZ39wJB; arc=fail smtp.client-ip=52.101.62.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="XlZ39wJB" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=X3DAc6SrinUofHHN3nkjOd9GpttFA34dbvW4q/C7QIuAITN4kUFJrkb6uLyNpsgy4R/etu4YkZGgq5AKypnHtMdiuGWn84crXDOEoiHtO0oBTK3brjzYJECUsL84rY9NMeWjSoC8JFiQiSW7dAwJ5HPVSQCKLY5wmkGeI1SAv+HARWqusDyfXBPZhA1Ap1De0zAJd1UY9cfvhiz5wY4z8a+2A2IRFSYSrQ7TK0RU2P3gpP55WvO3LXV6Gd8s9jXio5n9Q4Ar2NdyYPJ97srvoVonf11CfCobxxDvtKbbJxRpmZenRaDqLLZYasJZHyW0kl49EvrhVGJV4VHSJOj36g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5jy1rKYFZF4pBkw7HgyarP3PH3DqXDFr8693LusEado=; b=Dw9vNOm5R3Wiq0yKct1MsCxGYmFqFImiwG0udzZ8l2fer67/EDSBUqfANvKxaJkGqroCBWNndFuVdi9I7lh7IJNpsriKUErynaqaZEQqtiYBIk/NpdiQgOAxQVJ3mRYkysfbI5Z1CJpOpbxovUyzwgpXa4OQJ/SE5AtnCk/3uvuqJRDWdWo7KELyqsLP7OidTCV9llOgW3zrLqHzjBbGFmFu6yNXV3/362G/N6h/olmDsfWVa1ZUwCxSceE0T/IDBvKEzKpcUgn6cUITs9z8zMO5wK6yxTyJkCGsTQ6dCKfPPZA/9sV39lZd/lUG7xT/LkHPQxYjvUKH/qt/2eqUdA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5jy1rKYFZF4pBkw7HgyarP3PH3DqXDFr8693LusEado=; b=XlZ39wJBeDWmkih2/07Y7oRu+nHqOQxJnHEQtWz6lPnzDkziGwkyH203esddPFjrFeLzOCPNprHrKdxRsgKnroSw3zeUKMsvLqnY+2TwBDYTuDLgqzkd6nVgbCHrF8MB6/3NKQxZmCT7xHO41acqnb94zljDCb+wzZLP8I8UJ7cBR8GhSXLMeenv5B9/ELSpHNAvtg1fJMZBg8sewg+GfQ3GvuwIx6ys5dwkG2nyjL9dxxq6IDM7pZwtXZYaZ6AQ45NcvbxDkCPYLK/auPUXxxrEK58DBqeC/GV2pCz2PBEq1n+dNHgZNMRBje8GNBSeSxrB4GXHhVvaSU2UnhtYYQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:54:32 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:32 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 26/31] gpu: nova-core: make WPR heap sizing fallible Date: Tue, 17 Mar 2026 15:53:50 -0700 Message-ID: <20260317225355.549853-27-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR07CA0041.namprd07.prod.outlook.com (2603:10b6:a03:60::18) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: e7f3982f-0fd6-4ff0-9410-08de84782758 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: i2HdMs7LQMmOVydSTxIsk1a2TMpyBKWNn9RgTRZOp0RBS+y+ZWEPQHzfYWRBFwUtxsMo/up1ifIUd5g4hht3tVr3AP/rl35rdzsDhskuFBQuw7jUee6Rtc/ArJHj6BY9kuKKJlKK5GOR6dOxIFh5htbloOA6UewCOylS6YW+HAu0ZsUh1g1KdgeuhrQh2InrS7ncPQsFkjmrjR+wDnaoGyFT0xiCrfX7sS3ha/Gkn4BqP3Ub5pCr+W1i6HPiv2aRjsV7Q2bhgxZEPT5ELo6z7KBhdyQV26WIOufh7a3CivfK8rRNYangNmXluZnj77U7Tsai1ZXHHyhssiB/phh+EOvnYHwN+p6+6Xv2UNlP/80SHdtgYp2tVWOM8+0q3HSGS3weUrDkpPBewf6W/yD8U29Is5pL8XMTNBvrYIiqxh7Qhy4S9ngpmP59MgJh0CHqvKyrO5ARNjsVJGVeUhMIgC6s1AsAB0dCNUKPiwe/ZvlK3l70GHgDuCZWnRQmMKRthS4FKApsuzBcOplcrNno5ToLsRtpMFKAGuv8TkVJeqPRcCdwEoO89psi+JDw3uR2XCfNxOc2pctvN4yBqNIa6ycO2uxB3YH7Kkn6g2qkFs7jrsRPygrayNx4Lpn1p/aO3KQ5OSyzYnx6ExijsUtRhBKeaUIqZofX/nMufwUd4B2YOrWj4V4KRa3V1pXZ7YF2iG1ZYHq6q1gw7i0s7rSC0S0gS8ZVdWc2kXDshQcznXo= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?KRONTp2u/ynsNK4uybK4osP0/XPIK41JGD3/hI1nbKKtP2OacYFa3nLpvwc2?= =?us-ascii?Q?yPp2c4ebuqBAShm0OTUF7svIETEEJrwABHpkqWlgCTK3yX0Bbs1GKR1z/W4f?= =?us-ascii?Q?akAxtCBLHKPLj0/DX9SyEkmSwp97CiNlcodH3BHPHuYEHeiTZ+8rJjVhXHC8?= =?us-ascii?Q?YV2F/XooUY2hNrBudN6PmGSN2ZOCQD+L+1CxeyrJAFjYFfC6y8Wu0f2hDMEz?= =?us-ascii?Q?hLsszfCFY0O+YRe/2RK/2cWhCxxioVt73TpdkcVD+0gkrkfjbxEK+n10l29S?= =?us-ascii?Q?8Jd4ok1ybT1NJjL5Q5+w4n9V5lF9kS2919rBB96qti4tJUXT0ScLXkzE1CBu?= =?us-ascii?Q?NeSNSM3OkapNXGaUUIZtZUkzE3Zjo6CKwPyOzbs9NSih4fCP2fCEmgprKslx?= =?us-ascii?Q?luDjtZIdpczIhFv9P/b0nmi7IYlEP3RWZVVp6pFwW8LzB1peYjnYn/kefG0I?= =?us-ascii?Q?cDjv47o/cRTyaphI5xsrfAt/URh7DvJe92Lko1P0hZChrPgiZf1jXnxgcRSa?= =?us-ascii?Q?4FRsARBqrwmx0yyL9pDKaFhxBfy5ZzcfxXl2ywOwSOPGWQLKyPr/ht0dU2gS?= =?us-ascii?Q?6C7JXAcligZ631X+qnKY6qWy+PS4DCz2ccqyrfpOv/eP+VXLKFNNKctpu5gm?= =?us-ascii?Q?l/ySPwkBc4wohcrodWZFSVBHGFemtt9avgCDH9pRsnI0ACGgqcLoOw2DwO2g?= =?us-ascii?Q?PWdNT/moXd64T2CdN/mcNFJR3z5QRf+pVsfhbRNRfmn9vWW+GWcWFQItp5uK?= =?us-ascii?Q?ucDotwwjZ2mapfv3oHnIrZ7woZyRUrTg90AmwYZ2meKidpy9Fwe6wia5HDCy?= =?us-ascii?Q?6BUQQ8ZpJsGg6luAtbPBDFlCDL6WKPCeymb3uXtDBdS1oXtifb5LGDrFswcC?= =?us-ascii?Q?a8zeIjyK07SyfKI0FZV3J/3EE7G8HJ+rjd2Xshbc5XjPmK/i+pUV7lqhUa2F?= =?us-ascii?Q?6Rgq6pFqyJ6mQ/vXF9OJ23SEByMbyXH9v/Hp0GNxqEyt7jj81GiHa7zK5gk5?= =?us-ascii?Q?z42tMUqa1SetovQE3LUGJ7VDPf/j3bhJ1R33yKcW2K+gD0q5dMs0srTDX7nF?= =?us-ascii?Q?OpVrs1t9wzjFsxLO8pN9NEn7TzdZ6SqQEThJyQ/GMZ7jQt4Ah00aYy4kuroU?= =?us-ascii?Q?cSuH7QCM62cVAKfWebLdwJJrtXEGOSywwGDZEUg9+ZvEoYLfHLhMLndrpGnE?= =?us-ascii?Q?PzY3n682YmfiHydBG/MeC9p9CNUZhwg/LT+xbe9POwJqr886CejlKhKyU1Mj?= =?us-ascii?Q?/vKK8dKZcd5Lj8xMIQZwa77K8RG+M1QWOQ6fdBiSvq+yNTjND587dzGeRovC?= =?us-ascii?Q?xejr3mtafc4uO9aXFOB6KY410BFJY2XcxmcRKHySSZ0IUxIN3MeoUUCXGKwc?= =?us-ascii?Q?imFIdsuxSumUbxGv7si2JRKZ6+kEZ5tqk6F+EVT2l27KjWKwOBPWA6qJ783R?= =?us-ascii?Q?rzLFrzfmGeoM2ciFRq6ei3z4Qh9rGPiCZw6MuSZq6olQQ7R8J7BzSddUDqsK?= =?us-ascii?Q?CglVxePH3Dk9K4IsISqEYCJYr22dwmHKNyFY3V+YSGAWyuySFMpBqQcxjfwd?= =?us-ascii?Q?Q+sXFwIVpoSorZKhn4Qov68kHLs0tyObv6RtbMtf6ERytYKjwxLD9/oSYxh5?= =?us-ascii?Q?nfucZ2gEPOMoJPNlHh87LyLcL61kwERDpoGP977h0yNlEtP91k92TMLXbJvo?= =?us-ascii?Q?dhTkZ5rhUywfbgCDvVfdByBxBqPN4hvAVLU8p02f2pV2I/kuoVBwidMpUMGr?= =?us-ascii?Q?kMoTW7wWHA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e7f3982f-0fd6-4ff0-9410-08de84782758 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:32.5696 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wK19o721mawykOHkBpwUN2W6tsK5RjeRUs83EGEAVXIQs+MixTKYG6jf/ecH+jiXzw5XcOjAedIMbc36Hqt/HQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Make management_overhead() fail on multiplication or alignment overflow instead of silently saturating. Propagate that failure through wpr_heap_size() and the framebuffer layout code that consumes it. This is not Blackwell-specific, so keep it separate from the larger WPR2 heap change that follows. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fb.rs | 2 +- drivers/gpu/nova-core/gsp/fw.rs | 16 +++++++++------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index c12705f5f742..5943db2b619b 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -247,7 +247,7 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw:= &GspFirmware) -> Result< let wpr2_heap =3D { const WPR2_HEAP_DOWN_ALIGN: Alignment =3D Alignment::new::(); let wpr2_heap_size =3D - gsp::LibosParams::from_chipset(chipset).wpr_heap_size(chip= set, fb.end); + gsp::LibosParams::from_chipset(chipset).wpr_heap_size(chip= set, fb.end)?; let wpr2_heap_addr =3D (elf.start - wpr2_heap_size).align_down= (WPR2_HEAP_DOWN_ALIGN); =20 FbRange(wpr2_heap_addr..(elf.start).align_down(WPR2_HEAP_DOWN_= ALIGN)) diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index 92335e7fc34a..4a8ba2721dd1 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -140,13 +140,14 @@ fn client_alloc_size() -> u64 { =20 /// Returns the amount of memory to reserve for management purposes fo= r a framebuffer of size /// `fb_size`. - fn management_overhead(fb_size: u64) -> u64 { + fn management_overhead(fb_size: u64) -> Result { let fb_size_gb =3D fb_size.div_ceil(u64::from_safe_cast(kernel::si= zes::SZ_1G)); =20 u64::from(bindings::GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB) - .saturating_mul(fb_size_gb) + .checked_mul(fb_size_gb) + .ok_or(EINVAL)? .align_up(GSP_HEAP_ALIGNMENT) - .unwrap_or(u64::MAX) + .ok_or(EINVAL) } } =20 @@ -189,18 +190,19 @@ pub(crate) fn from_chipset(chipset: Chipset) -> &'sta= tic LibosParams { =20 /// Returns the amount of memory (in bytes) to allocate for the WPR he= ap for a framebuffer size /// of `fb_size` (in bytes) for `chipset`. - pub(crate) fn wpr_heap_size(&self, chipset: Chipset, fb_size: u64) -> = u64 { + pub(crate) fn wpr_heap_size(&self, chipset: Chipset, fb_size: u64) -> = Result { // The WPR heap will contain the following: // LIBOS carveout, - self.carveout_size + Ok(self + .carveout_size // RM boot working memory, .saturating_add(GspFwHeapParams::base_rm_size(chipset)) // One RM client, .saturating_add(GspFwHeapParams::client_alloc_size()) // Overhead for memory management. - .saturating_add(GspFwHeapParams::management_overhead(fb_size)) + .saturating_add(GspFwHeapParams::management_overhead(fb_size)?) // Clamp to the supported heap sizes. - .clamp(self.allowed_heap_size.start, self.allowed_heap_size.en= d - 1) + .clamp(self.allowed_heap_size.start, self.allowed_heap_size.en= d - 1)) } } =20 --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011036.outbound.protection.outlook.com [52.101.57.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B55C83FD137; Tue, 17 Mar 2026 22:54:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.57.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788085; cv=fail; b=PU8BZCKoOtflelD5EA6FxcBkCvmQyrvXFzK4BIa4HdA/ePZHxOrXyLfmABwBKBIl5bo9xLExvcmCcNYPU6tzcYYOECAZbHPKi4jlQDBMmR1AeIo1v50N4E1yiaXA3wep/GyluTLXF3mtGJcvtH0gtOd/leIvHjgYeTUG6FzOcTo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788085; c=relaxed/simple; bh=cF30D6701HogBoOXmYnXFi9lu1miEzrDYQR8IYgU3a0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=O1BQwfRs7DRMwIq0buJsq3QkLOpbCLAyVkB3JWJYZLVJ7FYV5RzblK3R+nqlrATzaFvDgElcL1Wi6akfEb0CBSQ9FfY/F1zXaCUAIAZZmy06++3P5P78lJJIbvPzD85/Ffu3U3gIRXX3Xi+eopLAXyDsdO2WVBKfd09ryELg9Zo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=PshmE3Xj; arc=fail smtp.client-ip=52.101.57.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="PshmE3Xj" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=y0lZZ+Kmh3U1Y2KhV6GsAZgX+UFhzZPR4EkaZkiUREbY90TTXeK3zntK0sbhvwWx6x9VewSqSNE3aq4ctZ8b/hXaNUJTpGu5M/vD5jy1EDt6BKvkL4t8eS1C2HKvVAXWAWnxt/g72aRjLWuzUMioK7WPDFpFOr0oW1vBUGYQCvWL/+aYJTGqqnELhZtcsvAdtLxc8O33ST1X2atYDBHKmnO5Z5zJkRZzoXm6v5n1pfqmfcmTYrFJTwk/qbATEbJTzoEueTvEs8vV6gWHyuDFo/ncZqJ87D4qajNJHWCjgGkI+GfPcpKV27wq80M0ChtjiKArPU+JlzFluHDV+2k8AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SLTekVStI/SaaWTpw1O40ucEt00jVVhiq4DHthlQRxA=; b=B7eALOF3MmCdTWQ6t/kEHoaZUjyGM2iPHHeo09jnEGE3fjoqP7b8TxF39KW3wCetL0nZUhW5uyoKJTQPxiZtNy6YltdBC7STNuJJFIMw2QgqC0LY2abi8c6d50lZaMnBEvQNT7lZp+l/ZTdzwlC+tyAV7xtcKZmCN4pDti4/be/z3VpJPD5hYY5m12YQazOOXkEO2ZQgpsBA9A34C38p0u0Hy+/l3b3VtoCQyU8Lzw2I4AgM0ExvEnejRFeT5Bv0yxNanLwLtbT/O9iq+xUzHREt8PJYwmdgxMd7VC7CPnAtP7vA4WY3xFVfOvP99Zft6SdSgmIsCpVMoaZmnvtwRw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SLTekVStI/SaaWTpw1O40ucEt00jVVhiq4DHthlQRxA=; b=PshmE3XjBDgoVeo2wgN/LGP3i2s6qE3nlfMxu668/sAfqeyuBjwjFXjkRdC8OA+LWbRaAtLT99CLRdDjF1nvWsY5/3rxusOtYUsyRrxSEt3Ut4fU6TGer2lsYY8UdRCjvPy8snVpgq5jGxyy/631+I3jAXH44EgVoqtTFW2No15YOCsVFGmFIz/gui6RoG9EBLQFvyct8BwGa0zRgZHHNTE4PEb1K9hnxkgn1NqpSTJ19i20QJeLtEAiMxDW4Ew62tdCnO8w+dZgQbCNocwFpruObNI4kXAZph34sIJNrfPprKaLD9tLvCwT1ukThJQiLfasj4xufEvxRSsB5UZ5bQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:54:34 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:34 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 27/31] gpu: nova-core: Hopper/Blackwell: larger WPR2 (GSP) heap Date: Tue, 17 Mar 2026 15:53:51 -0700 Message-ID: <20260317225355.549853-28-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0253.namprd03.prod.outlook.com (2603:10b6:a03:3a0::18) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: 87694433-db86-4773-21f1-08de8478281f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: C16OWUQCHcrvTczTuFOOv3BgA54ZEOp4NQVI4w1mhwkAO4zfI17dxjlon2dRQmYVRmpGDZDitddrlY+c/3PsvFjhwyNKRrV/GKe4EZtf0/+ctNfghohF9wXnHlQTbLNZrsMo6ugvxBPFPWDnOiHk7/uXqKt7UN6ApnX0IzBuk8CsXlo+03vHQ9HbaPTELUu2nF40lW9hYs2+u39/GcelH6D3W9vE2URRom2ms5bRpum1YUUH8tM8Er5N0KF86i+bF+bTnht+Iua5GSzNhfmbSOEo7iaWE0ur1V+I6gMsAaTcvozLc0p3HeeNlkCrb5nRJ65/TM4LFY5fycxjjbvRU+aD4zN4nrqzmJehOTf1mYkgvTyMNhkmSwzv3Rg7ZF+cui711mmhS2pyCCY2PcZknZWMx9dt+7XcW0wqkiYeDhDO1y6tO7qd6VKFE5jG9zNA7e8PST0eMBQTzm9OJGyUgbNwMxbpcNNyEdxq+7Vo4VUHn2y6Mh1WeR8m7O76yR8J7rdamuSJuiy/D7p8vLbWzAxVsFfEwoz+cUzh76yGx+gVJrjLS3rl0QcdFXcIaPbsGX/PDesp81CNQNImEWtVN3FqkjWjWQrdqu0GWCgYOOo5twAEzP8agiAyY3qPPBTPIgv1SAvv1CgKPDNvqWBaJlPv/vJShCEF1n7xSl0CVRY/hDKOrKTHw/RqfZNIl5Fng0BUEEZhPkGz/i1XxumrZlws4yTajVTB6yO3RAL+vt8= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?wGPI28sJom25xxnBsoRSF5LOkByJn2QAfjRzGU6vEtn5dNL2oqlKTCX/iwAP?= =?us-ascii?Q?xEA6b7zgUbJVFP/oSWAOd+oaJsm5u3O45bdY7ZBEHXokS54tQ1FE9cR651Yq?= =?us-ascii?Q?12SYJvWoXlolN8s3Vzs3ibDVzhyKqqsni1OWUcPFvuZhSPwFn0FWH3wLOzlT?= =?us-ascii?Q?J2V9oyBmFcQXvN7m1T9xxNL5NnZchg0xnKlR/eOtLnNwED9Pb2prm3bQyZGS?= =?us-ascii?Q?ISEcHXU0UPFxHl2QNiXBLgEfI/4Ixmh0iF0/SjaqGe7kDC8JCHEUgVYfWC83?= =?us-ascii?Q?xtvJ/HxF06oSREUV1w1YSayDbFpn96YBF38bDqfKPOcWDsVYO1l42ug+k96b?= =?us-ascii?Q?W5SdyciuVjnqA3LF3OS6criYUjIYLqWVpKNPB/v6q7AJ6ibhLnJp7PceG+8P?= =?us-ascii?Q?ONyBcWKZiUvwe55N4Q6H5wWix9Pa8bjQ+/YyBzjsO6OFFmD5u1FYOzP+M3Dz?= =?us-ascii?Q?7afjguOpx/nr0Agwu/MMd8ReAeBxJ45yH8sSd0PgWrCgrKReJPyHGBJhLWdw?= =?us-ascii?Q?/1NyyjVgY5EslGbc5DF4mrmdFaj6f3cjIwZxNKFCaq5wb7KfqghrtQ5Ntr11?= =?us-ascii?Q?kXjOxAtAwwuaR2y3i/dGE1cb1XVb6wgKVbqElauSNl940g8D1/noYY+H+7UL?= =?us-ascii?Q?xQe8rXzj4fYFR0XGq6n08S5UwVmRgW5cQiS6CNHUJpWYYmM3yPV5EAyMuiEo?= =?us-ascii?Q?OIrFniELaG1qnWFwj7mMIQypHwxMFbgu+O1iwv+cBamGniZ7Xhi5bQ1PkjR5?= =?us-ascii?Q?Q8tEFqRFUbqR07oLpEOuuKk6yz9Wb7jAkKI+juoLDyNC4wd4APsHyAg/LmO1?= =?us-ascii?Q?M0apLXTNM156PY0Gg4tEcCQtGyTpt1wz7+HsrnMu/bvshl6ZgS9Ndz1QNjwD?= =?us-ascii?Q?SzaBMwEXnZQ9GKYfdJfxnJ2DUNwdb2eYLR/ZrEjgQ4gaGsj9Cv/14IJeVoIW?= =?us-ascii?Q?tv7S9Qez/yUOPdullsYnUc9BbdAIF6W0/lzxcvM2UH864qvQpnGnOO63ps6f?= =?us-ascii?Q?kuHlQdgvuCHmO8L3DuO/6C+1XnhYE8Bh0B8bb9QbvW5y5dPwQVKOLuFFkLBR?= =?us-ascii?Q?REi1ryPhgkiyF4zOTSbGkuNXkzV92wqNqPG8KMbA1cVFddcHCnCa8zrngJwH?= =?us-ascii?Q?+Wf5Ar0xoBB3XLwVmKSljAD7lfWt9QW1o7OX2UZovXSzxhTq1ubK5EfsQRmx?= =?us-ascii?Q?30WUj8spiIspU3/7lgO3WyFptcFHlA9W8DeffIv4+JE9ZGDbpgUAY1E9i7Yl?= =?us-ascii?Q?MVu90ENU42dkkN5V0GpsCW6/HiPQ/J9qDbmaTlnboZ9+1PMqqucK0+KxuJGG?= =?us-ascii?Q?z7MumReqagSNguoNtJVvgJs2m85NCbwd+KUcfGZuayo2QaWMW80ZmF6C+luB?= =?us-ascii?Q?zVP5IinqJcpNTr/nIIqDWuyk0H3cQGoL7RFCX780kH0ekDcv/P9Xx6oK6m4f?= =?us-ascii?Q?IuuZsauFm1oT4N9ZmLBf3BT5G8k8Aw8yvP0tv+tSPoBfYSsLHG0SgQunI4NS?= =?us-ascii?Q?dgaeyEkwRwnKlfJ8no+1TueEW3hnX5OBkT7FPmm4PvqeHRZh4AErttGr7prU?= =?us-ascii?Q?58rm8LtsktpGeEFV/+9H1jx4/PR0ZokVofM0Mdlaw1JzGCv7h7f0KOJ1Pv55?= =?us-ascii?Q?mboN8ZYQLTmWyLqOdbuT2Q/6gGbOUkLAoq2W7iOSPyavuQF/hP1YllwJwC1F?= =?us-ascii?Q?a15xCMil/+WIdqupBdSZkqUDZYF8mgXmoda4YWfvGIhRdBMmDg/IUE39ZO00?= =?us-ascii?Q?RUvg7chHaw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 87694433-db86-4773-21f1-08de8478281f X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:33.8874 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LjSolc3mvAfuRJttgDmJxOupoZfRdO99naHgJ7DTGk0GhQewBiUrpDFPvSkPtSkNcxu+X+Tao16n2B3oyB2nfw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Hopper, Blackwell and later GPUs require a larger heap for WPR2. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/gsp/fw.rs | 61 +++++++++++++++++++++++++-------- 1 file changed, 47 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index 4a8ba2721dd1..c2eee984bd4d 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -121,21 +121,41 @@ enum GspFwHeapParams {} /// Minimum required alignment for the GSP heap. const GSP_HEAP_ALIGNMENT: Alignment =3D Alignment::new::<{ 1 << 20 }>(); =20 +// These constants override the generated bindings for architecture-specif= ic heap sizing. +// See Open RM: kgspCalculateGspFwHeapSize and related functions. +// +// 14MB for Hopper/Blackwell+. +const GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100: u64 =3D 14 * num::usize_as_u64= (SZ_1M); +// 142MB client alloc for ~188MB total. +const GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE_GH100: u64 =3D 142 * num::usize_= as_u64(SZ_1M); +// Hopper/Blackwell+ minimum heap size: 170MB (88 + 12 + 70). +// See Open RM: GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB for the = base 88MB, +// plus Hopper+ additions in kgspCalculateGspFwHeapSize_GH100. +const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB_HOPPER: u64 =3D 17= 0; + impl GspFwHeapParams { /// Returns the amount of GSP-RM heap memory used during GSP-RM boot a= nd initialization (up to /// and including the first client subdevice allocation). - fn base_rm_size(_chipset: Chipset) -> u64 { - // TODO: this needs to be updated to return the correct value for = Hopper+ once support for - // them is added: - // u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100) - u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X) + fn base_rm_size(chipset: Chipset) -> u64 { + use crate::gpu::Architecture; + match chipset.arch() { + Architecture::Hopper | Architecture::Blackwell =3D> { + GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100 + } + _ =3D> u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10= X), + } } =20 /// Returns the amount of heap memory required to support a single cha= nnel allocation. - fn client_alloc_size() -> u64 { - u64::from(bindings::GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE) - .align_up(GSP_HEAP_ALIGNMENT) - .unwrap_or(u64::MAX) + fn client_alloc_size(chipset: Chipset) -> Result { + use crate::gpu::Architecture; + let size =3D match chipset.arch() { + Architecture::Hopper | Architecture::Blackwell =3D> { + GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE_GH100 + } + _ =3D> u64::from(bindings::GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE= ), + }; + size.align_up(GSP_HEAP_ALIGNMENT).ok_or(EINVAL) } =20 /// Returns the amount of memory to reserve for management purposes fo= r a framebuffer of size @@ -179,12 +199,25 @@ impl LibosParams { * num::usize_as_u64(SZ_1M), }; =20 + /// Hopper/Blackwell+ GPUs need a larger minimum heap size than the bi= ndings specify. + /// The r570 bindings set LIBOS3_BAREMETAL_MIN_MB to 88MB, but Hopper/= Blackwell+ actually + /// requires 170MB (88 + 12 + 70). + const LIBOS_HOPPER: LibosParams =3D LibosParams { + carveout_size: num::u32_as_u64(bindings::GSP_FW_HEAP_PARAM_OS_SIZE= _LIBOS3_BAREMETAL), + allowed_heap_size: GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_= MB_HOPPER + * num::usize_as_u64(SZ_1M) + ..num::u32_as_u64(bindings::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_B= AREMETAL_MAX_MB) + * num::usize_as_u64(SZ_1M), + }; + /// Returns the libos parameters corresponding to `chipset`. pub(crate) fn from_chipset(chipset: Chipset) -> &'static LibosParams { - if chipset < Chipset::GA102 { - &Self::LIBOS2 - } else { - &Self::LIBOS3 + use crate::gpu::Architecture; + match chipset.arch() { + Architecture::Turing =3D> &Self::LIBOS2, + Architecture::Ampere if chipset =3D=3D Chipset::GA100 =3D> &Se= lf::LIBOS2, + Architecture::Ampere | Architecture::Ada =3D> &Self::LIBOS3, + Architecture::Hopper | Architecture::Blackwell =3D> &Self::LIB= OS_HOPPER, } } =20 @@ -198,7 +231,7 @@ pub(crate) fn wpr_heap_size(&self, chipset: Chipset, fb= _size: u64) -> Result To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 28/31] gpu: nova-core: refactor SEC2 booter loading into BooterFirmware::run() Date: Tue, 17 Mar 2026 15:53:52 -0700 Message-ID: <20260317225355.549853-29-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0146.namprd03.prod.outlook.com (2603:10b6:a03:33c::31) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: 03b30785-80f1-43fe-b038-08de847828d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|7053199007|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: vG5zdwWcRK6oOGQ8mOhUyAUCb/GATO2sUNDDmFq5Fpj1PH46lAwjUHoBSKkm1bv9WgYNavfvSXgxgayyIKGrxLY5WZKL/wLcWaJxHQWnRxHtC31EVpP/aVcBiYYzN6AXPPQEWQr+ZzCgHm0hGgeP/c77vSmSe/el4cSC+W80SEY/UTO5Cx474Va+Qm2nQAZXqBH4IldN8gPLLF7J7oW21a/pj7zMCzWVa4GFRjRQMYP8J7ciTKuJeian4YKybtIwTNk/9l7z1b0oKlkM8pTommT+h1xNtJyvV7swjVLMi6wS5hlfOkJy/lHZgJbUMV+CC6OkXfiEXOciU0CaYtUXLritBFMt585QxNbJcEWSFnhV/X0C/SIyhGNodb0rYnSwTxasvWIJXlTcxdEdnWK26ghby3b20oU6QamCrSYjMuPuyu9B40/B0WvO6yh2SLkxJQAO7AsejTdRey5YB0G1VH2xhdyuzxlTffjOhdGx8o7qxu2+NmeRj83zi9vKGqcdslfJcFCAt/Bz7v01dKuPL+5yE82hdtrAls4Yr2ZNhxDWG96uXhIfp3LxAtmt2YWmN0Dd+uycmZ+I1QH1FZ5ii37BqSO2K47YrcoMdteM4+DHzO4fKueISmNmmvH+SjW1hDNg+EvedP2Wu5+EjFhsP7zwNZrKHBXJHArVfTNxbM4xQo0eqYkwT36WhILnhREqD0jvOVcpwSuIaMGvb19L7itqG/KcSGDGZImnFFY/C8I= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(7053199007)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?+x86IWuN1eZKcGcKhEZ70ljAB/GLykyBiIk/zal6v1E2YFXF/8HgnNoHpubv?= =?us-ascii?Q?sRwwTieN3Lpxe4SxLe/hOWLTASN5YjQhVtWc5chGUupPSDZK8YuwdUhIsQ2G?= =?us-ascii?Q?mgkGTsbiltUbNx3eyCSXDRbMmE70++a8fMUiyD+RDlIoSy+bY2n/qkQa5/pl?= =?us-ascii?Q?uAns3DO+3RUqra8rdy/3ej0bbh4HUu3UJVlSBQnBqonzU5MIJEfpSe07xpzj?= =?us-ascii?Q?5XczKg8+1MjY4WVvz21TD0aCxD/7fCK3nLEXkjs7GSktPTzaRQ6+Ux4S499F?= =?us-ascii?Q?iIBuoQkQ004zmhwxLGTRbgzn4Rkz4xYuESbQ4vks1s2xHhXeRm6eK38mDolD?= =?us-ascii?Q?Rv7slZGyKllfFM60/Dkt7j6tkwE1iJFuxWbWtTUlWyTlOJCCsguNY/xqRxvp?= =?us-ascii?Q?+GOyzNq+oqXqNpoPNltB6BK/5y4BLlpMxzTYp0vlI2kogiJHYTaRMEsSwA8u?= =?us-ascii?Q?c/bA/GDnrysj3kzT9vHjOpFDbcDAs3pcPPXYmNkBvzrJeIPMPt42YyUkEv4w?= =?us-ascii?Q?/aQ1uu6k3/XoMkZvpSssW+hFcX7ynK9lqXCDkpTwOoNoJDnNuSUycfw/n9UN?= =?us-ascii?Q?2G7KYnR6vejvoB7CJ1n9jM6visDB7lHpCvcH0umWpnw26d5tNm52vxg/n5so?= =?us-ascii?Q?kGJ+csR804Qf/1PyPLUxSJfKb8g0gydcARmMkB3HLjzO+AwmtCYuJVGlJuMM?= =?us-ascii?Q?MBfUbdP5tiNA1WJFJ8tG8v6qu7m8yjtYddJqBqcZCbTaqbhAK+y+YA44T8tW?= =?us-ascii?Q?U5yK22gDIPEm9LfHSP7N7rAk4nwbnoSSKkN7ADkISrJVrEJIjHDktaNDDgGV?= =?us-ascii?Q?SFCwqi7W88YHK0g9kknTdnb5UOlocFq+EbXZgDfM5bue1MO2IO5KKQHisqyc?= =?us-ascii?Q?b24GX4okAaPVweGi8IlbefC1cjyhtrB3GgO8OQxBtU7Gi6ORSP+f6jKydkR/?= =?us-ascii?Q?Xp/NUVbD8vHvdteHqeTaIpgD8tfAuYwD/X1gUw1RdIFqUDVebcMqAk89gJp0?= =?us-ascii?Q?D58dAIkoaVjn4XwE487dj96VAa9RE7m9GIHF3TAeg8rlKyhKFKiu2EBHH4b5?= =?us-ascii?Q?T1F4tFAQAjx3iVmg8nAS80vI3orbTN4EXdEnHYNw25yJk4Py1H5Jog5q2yMp?= =?us-ascii?Q?Dq9vU2LRm6DHnRbFAxYHiIb7VQ6uwf1oi5lF1NYBNHvStSd9etx/DFsP5Ssn?= =?us-ascii?Q?MK027HWqSD0BtPm0yRk7BHFo8D+piibvYUCHzMyX8nviR3GUE7pLYDMnxD5G?= =?us-ascii?Q?XS96LN8JJ3l80lne1+i0McQSlOqFcmRH2p99n7egBhSYjBJSRdwyQyUmYodf?= =?us-ascii?Q?jkZrxcBxwo7fJPVccLBIBrjy5USYrjugPbeuNYYBbqQ8+CKhsyjE1ESRQXN3?= =?us-ascii?Q?sL/0Gj33jWJ3N3XTYXoS7AEJJ4Lp5PYSxj8S3GUhawmMF7bh9fucCqr87K2d?= =?us-ascii?Q?+tGP4gA+1TWm9jz338WqR7VrihmAdYuYLpWoVlxgyteK2ujl8VHIP/7teIyx?= =?us-ascii?Q?zrFIV/nnVPU2Z4ce2SleOBammsoJBjBDc7G+FbR+9j+2GNafJK1YQGu67vtx?= =?us-ascii?Q?2qSvrvm4TH2vbCt9+8proSt9fCF7E3IyysemtKetE2Gu6u+UTfJilFu9O5Yx?= =?us-ascii?Q?QcA3eIwUJBOMXiAre7VsLj8xhhrfv7emzDYOl/5GL6fvur05PwubHb3VH+PX?= =?us-ascii?Q?CKlh6ud+SGYMYMmUbhHh5evhnT0dDBxMkEn2LEFVS7+3dE7NCSw6XIu4iLJX?= =?us-ascii?Q?TmYoetsVkg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 03b30785-80f1-43fe-b038-08de847828d6 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:35.0718 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xTCVLSEV3nONvSk2i4fUpVWLNSEuzDZpLaDdYJNIfo0prIPxQYAMuUcqEdU+RukpqkVo7c+5EGCzI7EH+md4OQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Move the SEC2 reset/load/boot sequence into a BooterFirmware::run() method, and call it from a thin run_booter() helper on Gsp. This is almost a pure refactoring with no behavior change, done in preparation for adding an alternative FSP boot path. The one slight difference is that an MBOX1 printing typo is fixed: Previous output: NovaCore 0000:e1:00.0: SEC2 MBOX0: 0x0, MBOX10x1 Fixed output: NovaCore 0000:e1:00.0: SEC2 MBOX0: 0x0, MBOX1: 0x1 Cc: Timur Tabi Suggested-by: Danilo Krummrich Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware/booter.rs | 35 ++++++++++++++++++- drivers/gpu/nova-core/gsp/boot.rs | 43 +++++++++++------------- 2 files changed, 54 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs index de2a4536b532..7595af8acfd8 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -8,8 +8,12 @@ =20 use kernel::{ device, + dma::CoherentAllocation, prelude::*, - transmute::FromBytes, // + transmute::{ + AsBytes, + FromBytes, // + }, }; =20 use crate::{ @@ -396,6 +400,35 @@ pub(crate) fn new( ucode: ucode_signed, }) } + + /// Load and run the booter firmware on SEC2. + /// + /// Resets SEC2, loads this firmware image, then boots with the WPR me= tadata + /// address passed via the SEC2 mailboxes. + pub(crate) fn run( + &self, + dev: &device::Device, + bar: &Bar0, + sec2_falcon: &Falcon, + wpr_meta: &CoherentAllocation, + ) -> Result { + sec2_falcon.reset(bar)?; + sec2_falcon.load(dev, bar, self)?; + let wpr_handle =3D wpr_meta.dma_handle(); + let (mbox0, mbox1) =3D sec2_falcon.boot( + bar, + Some(wpr_handle as u32), + Some((wpr_handle >> 32) as u32), + )?; + dev_dbg!(dev, "SEC2 MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1); + + if mbox0 !=3D 0 { + dev_err!(dev, "Booter-load failed with error {:#x}\n", mbox0); + return Err(ENODEV); + } + + Ok(()) + } } =20 impl FalconDmaLoadable for BooterFirmware { diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 6db2decbc6f5..ad0344db66b2 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -129,6 +129,25 @@ fn run_fwsec_frts( } } =20 + fn run_booter( + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + sec2_falcon: &Falcon, + wpr_meta: &CoherentAllocation, + ) -> Result { + let booter =3D BooterFirmware::new( + dev, + BooterKind::Loader, + chipset, + FIRMWARE_VERSION, + sec2_falcon, + bar, + )?; + + booter.run(dev, bar, sec2_falcon, wpr_meta) + } + /// Attempt to boot the GSP. /// /// This is a GPU-dependent and complex procedure that involves loadin= g firmware files from @@ -155,15 +174,6 @@ pub(crate) fn boot( =20 Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, &fb_lay= out)?; =20 - let booter_loader =3D BooterFirmware::new( - dev, - BooterKind::Loader, - chipset, - FIRMWARE_VERSION, - sec2_falcon, - bar, - )?; - let wpr_meta =3D CoherentAllocation::::alloc_coherent(dev, 1, GFP= _KERNEL | __GFP_ZERO)?; dma_write!(wpr_meta, [0]?, GspFwWprMeta::new(&gsp_fw, &fb_layout)); @@ -186,20 +196,7 @@ pub(crate) fn boot( "Using SEC2 to load and run the booter_load firmware...\n" ); =20 - sec2_falcon.reset(bar)?; - sec2_falcon.load(dev, bar, &booter_loader)?; - let wpr_handle =3D wpr_meta.dma_handle(); - let (mbox0, mbox1) =3D sec2_falcon.boot( - bar, - Some(wpr_handle as u32), - Some((wpr_handle >> 32) as u32), - )?; - dev_dbg!(pdev, "SEC2 MBOX0: {:#x}, MBOX1{:#x}\n", mbox0, mbox1); - - if mbox0 !=3D 0 { - dev_err!(pdev, "Booter-load failed with error {:#x}\n", mbox0); - return Err(ENODEV); - } + Self::run_booter(dev, bar, chipset, sec2_falcon, &wpr_meta)?; =20 gsp_falcon.write_os_version(bar, gsp_fw.bootloader.app_version); =20 --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011036.outbound.protection.outlook.com [52.101.57.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A27B13F7A9A; Tue, 17 Mar 2026 22:54:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.57.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788087; cv=fail; b=Nzq02dLZetBfKAVA4AbPyd6F5Zk4Cz5SDCUL4jUUvCXhiTPRTn0GWAzVMqqDFsCqZNUhRCJkYCpq4FLaD5TnzGtrbo1b6QJZQ6QuaOgBlTvPDVCxtsOrjHDBhBlV3QyTunys+BV3sDuCMYUjnJ1xFUkgX8XjAECniHP5bER5tMk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788087; c=relaxed/simple; bh=Lw+5B40/LV94exw13BwjzZ7faywTcCvvIuAZZGnP2d4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=sLLHrB4mVybdsQSc9rJCC5REYT7Abgebf3NLePoy8KIvb0+DER2p3BTUC5sQZCJ+yCo/FHzu3vC+MYl8M6JA3K2ViUIn8MvRvyVLEvD2v8DGpXNkqz0n9/BC5oU4r4SzaLKJFu7k8aWQdqF0aBnjnBL6Zlqf/IP/oKvKsFPYuPQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=cNk2bpEy; arc=fail smtp.client-ip=52.101.57.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="cNk2bpEy" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=kZ45XwkeLLd1oJYAvR0R2KW15YMD9G5vTu+Fb6uC4HtqUf+vm1CgZ1Q+0LusDSyd1aQGGlZaUCUzbBFbM4o7VdpjdMUMPnVhprYl4PfHVDIsMF3ctTFRCQiTQNXcpxk9btMXQNCAmjQqW+rekxxi2gjqROZ0oARzaACoh0LqyDByQ0xdb9d6sVuX6qGwDRGvGJFTx2yKOiUbolWrFqZ41ecj3jYZ2HRrAYtya9Es81GrRftMeXzv/0YtiVkoONw3QynGiAVS95m6kU4+JH5MU7/Y/pI5oUEZAzc5yTnweqcDZRDPJyVqKCu5W/E11YgY/KM/mItS7GmfQeIHyZBc6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vzIegi8esmooDTEBEx8z95RoAUogwS9fv4O91zHVZCk=; b=lN2vxGWAPikSTLstUOUPAB7cW05rGv3cXaNigNWWYCfgLUaEbcLpSpg7N/IAocmt0OfXqo7tcextTGXCzbTH8vpSWZ4Zrv4KXpPaDzxLBa3twtUTbVIm3JzUJ+Gtb+hXySjxbwXHW/Kp3N0oSpuWBvjW8W8dPKtOH5iY4cdZRCkNCxOzRZ9LO8JJOsRNzjM10dI8eqz1Wxk2C3Fuvqc8sWNOLXMOChEp5mF9MwwnC5Mss0zdFmiHGjmOaftr+S2KktnZ5W8BvL+CqgjGMlBSGjBt9jRgP+mcMtLnssm6W1KXjwDjhr3gvQZGUGkR3tn7PWUn3DwDpqTWr/EGEmLunA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vzIegi8esmooDTEBEx8z95RoAUogwS9fv4O91zHVZCk=; b=cNk2bpEyitbkEuXpEhSS6yE6yQX70bgeF6b4W/OfPg9lzXhE3gdBI/Aw3OphZBrJ2bqUewtkXolYuEJRTIlpLZsRS3at65N+p1wI33Xcx+uReNuApr8gAJPtQMt8OFleMKEq8Kl+0yptdn+8ukWGDeDutl3WWWtKv+hZAvEFOADgIqoHf4dQPbMsHeZzhUJ1J4O4bsyAtyjoQVh0o3BmR+Ya2ZJ3ZBSRx1Td/WkIUXJfh4oRf6N4azne9sGW4Ez51eGwDeCvXGYPAPCmiv3DVlAjVmvrb8nAacd1wwoeckMayzQg5WDYzmUj38k5sdDqquNFwoiWGIUPMR7NH+Funw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:54:36 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:54:36 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 29/31] gpu: nova-core: Hopper/Blackwell: add GSP lockdown release polling Date: Tue, 17 Mar 2026 15:53:53 -0700 Message-ID: <20260317225355.549853-30-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0101.namprd03.prod.outlook.com (2603:10b6:a03:333::16) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: 80678223-a7f1-42eb-ce9c-08de8478297a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: wAmHLhnZzcV8EBahnfb5+MehQtyyHRcVdxB7zoo+ZEUfalcLJFszfxWJQTP0Oc1yg5D04eaSNohxdMj+dVtnBXi6Jzdy3xrNGvkDyPkVkpdIIQcHk0lKUEERy8ThLBBEfpMSC6uUp8XfnsUx5NGVQfkfl5Brpr+FtYHt90o7ukJsZ1xvdQ3Ehg/Y7P7awVMrkisSoJYWV/SbLQvL85aN+nPZkBM4rCJ/ozY/xhhfBFORtASJbPai1nddIgqJGgohkoIkHI9IWUQ5EPioJTl7q0nGbq1oApG8Op7xqPkQmyTJoN/ObMz0W5CWGizyT6J/vQaSRiQm0DwvQLRF2mZepfGhDuH1CAyaRyeGot67mdRmJUlzagqMRALDbW+BOc/wyPN1skPH6aOk9AwLmZq5lb2LvhBsRnPAWmsgJunmtEbODPnv10fis38I/868J0pztlvk/MzyPpoJxFTuWo1384DMYEYCkixGSewMp2FwzNOBzKIK3czEbyTz/Pkk4Xq1q+8JpRe9wxDKETAuQqZv8K1Pp8fbzoODmjSx6bkPM9A43YSeL1/IyE62IoIPlECGuSzMKpPAmXR52gcePwhHMp7bBF9zfhzNf1CzHT5n+Wx8PPHHhVH+iQwKHYmXp7AcUcmi/dnQF2KBQSMylOycUGkvNRDjY64IqYXp2I+0tJzNEjfK2NBUqPgs3EBpZGSkkJ/oAAhumu+iLqGK1QiXcKoxlYgqbihKd3z+ZHWg3e4= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?f8+MYxVl1tOQkPGeDqN6kpBloTM7gpcy7RlG/hU4fjioXkhOh5EAW+RDAU//?= =?us-ascii?Q?JJndR5F4E7Bnjr2iWRc8R0AW9FNcmcAwihygciNWrtlgL6TeiZ4BEJABiBxf?= =?us-ascii?Q?U/kx2Skifc2ovHDkgAbB+vVYLWECP4fBiAdZC9p08Kflr5jL81LeKSVuZAmW?= =?us-ascii?Q?mrNlDoQ8a59C5jdmHpak2heMYFJjB8mXnOmrWH5HeEpwCGEr5do6h15afYbi?= =?us-ascii?Q?79EPMqa17VOlv1vJ9behF0tmNRiGR8NXd7cMN+fKablMPb0MJH6OFuU7q+MA?= =?us-ascii?Q?x5v6e2pB+8LWLXBGG3WjBp75cFprZ/W9j7Ig6XjeyE99EPaPnnn0uDLq8i14?= =?us-ascii?Q?3CoB1f9o3gKjtMjTWG38J/lCrXSCt8hQOtZ4TXOEdwPXIcIpUtSZbFbuoMde?= =?us-ascii?Q?eHyCxZj6UyKaY1qCakuqXRhy2yMzIt3STjh6sZoCCNqvi46Lg1zw0qURM0na?= =?us-ascii?Q?MGtbkipMBHvkB36B2LpG9pHswIMitt4784QtWG78zngzfuTKap4FCbsbb7IL?= =?us-ascii?Q?ya9n6JPyA4AVCImlo3CqDwx9wuOicZ7kLtpR1EJtV7S2Dhk/Jxj3go/LkIvs?= =?us-ascii?Q?k1hXzmEMZ2/9o1ID8vs62eHoRvGxk6wxEQEoNbpRBTIzV8rYz2zEUDGFxJuv?= =?us-ascii?Q?1wNwViMEMXpOlgaNU7T9HHrkAQdb0RfsR2BKlavOk5UcUJGVvX3bmpbRm7yd?= =?us-ascii?Q?O88DvkcLmNGoB1QTmcgvpALojyhuDQtgCt8vKvgMG94zon0CPalS+o8+kKCo?= =?us-ascii?Q?amdZSku8Skk7cSsDJmDJlZmCkq1zJJq2HNX+b41jSSD3ULcJu81GIAIh3Wrt?= =?us-ascii?Q?cq3gNOieydUC92cUPG301rSGbdYatUwNtvXnICJPQtld6/RTKDTVUwuYULwc?= =?us-ascii?Q?8eaeam+Ha4wWBvEEUQoi2FcRS5Z3DBp0x7RCZNpFx67UfjtHlXDFMbgXheAP?= =?us-ascii?Q?LTznHcfNJBNR4fwcvyUZGW3XKSwuRlTZ66TFzw1tR/C+Qe0MsTjDJeCzbbCp?= =?us-ascii?Q?9gdfQrQd3E1YOS3jjQFmjfRQ+xaHaoR2SSVsknJBzym7e/kIgHh65IsyE6By?= =?us-ascii?Q?WVc6XP4d8P96oP9ZATwpGhjOWYY0ovdSB4/rtEieymPKY04gjhZxFvGwn/DY?= =?us-ascii?Q?BYKaKOunn03pJHXw0StiCHdfX8zw3vMe+pjKUbzjmfIDAJOqMfWIDpxzY6AU?= =?us-ascii?Q?f4R19VgOmfp/BbYu1kld+/GMt06y//ROPP4OIbdccajQPDKEzWrjkQAe1TFW?= =?us-ascii?Q?faV9/KgguMHeTRj/JP9w+XGZpdhucXCD0oKfaTYtufjv0DWOwa1ilBP8zVrx?= =?us-ascii?Q?lvRdZaF41PoVPiPGgZMHxRXfw5cl69CwZ8j3C0H0Bvv5590wKge51J6iAINd?= =?us-ascii?Q?SqwslrVO3pl334mkMHPO4hdUre/RTtUBbPUDLa9xRil5PMPCETiH3TxCCY4H?= =?us-ascii?Q?E2K6QXP1jZSaUL1FSDiJG/+9klX9NU7V5SZHr2wNBYAGKay+Tsdapb3EsCHX?= =?us-ascii?Q?Rl9sOLADyNl1LBiBc6W0V4PfeuaqVDJWstXgDWS2KXXxWi5CX4vAPtmc64c1?= =?us-ascii?Q?QKq4nYYli69SFDMMaPxGUM/7BvV8Bia+g2S/AlHQMKWW8FUq+mmONplTWH79?= =?us-ascii?Q?Iq9AzK/YnsEDcolwOR7I4eFOdsiaqc2e5Aytua7ds/XUYWxkFijrdLVnHEYX?= =?us-ascii?Q?+ILKhe0THIDN7WYWrsPXY2nAhS90AtzIDUKNua5Dp33JTLafMu2v9E+RvmS2?= =?us-ascii?Q?3sty1tPfcg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 80678223-a7f1-42eb-ce9c-08de8478297a X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:36.1585 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mZTKO5cHj4K6fo7Tri5AoKqRjSj1vMiAqtoBieApA0ve4sQ/mKd7+xgrNKpjbndft3kRNOChMx7uJOXyhlDpfQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" On Hopper and Blackwell, FSP boots GSP with hardware lockdown enabled. After FSP Chain of Trust completes, the driver must poll for lockdown release before proceeding with GSP initialization. Add the register bit and helper functions needed for this polling. Cc: Gary Guo Cc: Timur Tabi Signed-off-by: John Hubbard --- drivers/gpu/nova-core/gsp/boot.rs | 80 ++++++++++++++++++++++++++++++- drivers/gpu/nova-core/regs.rs | 1 + 2 files changed, 80 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index ad0344db66b2..a3ab0bd7a317 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -15,7 +15,8 @@ falcon::{ gsp::Gsp, sec2::Sec2, - Falcon, // + Falcon, + FalconEngine, // }, fb::FbLayout, firmware::{ @@ -44,6 +45,54 @@ vbios::Vbios, }; =20 +/// GSP lockdown pattern written by firmware to mbox0 while RISC-V branch = privilege +/// lockdown is active. The low byte varies, the upper 24 bits are fixed. +const GSP_LOCKDOWN_PATTERN: u32 =3D 0xbadf4100; +const GSP_LOCKDOWN_MASK: u32 =3D 0xffffff00; + +/// GSP falcon mailbox state, used to track lockdown release status. +struct GspMbox { + mbox0: u32, + mbox1: u32, +} + +impl GspMbox { + /// Read both mailboxes from the GSP falcon. + fn read(gsp_falcon: &Falcon, bar: &Bar0) -> Self { + Self { + mbox0: gsp_falcon.read_mailbox0(bar), + mbox1: gsp_falcon.read_mailbox1(bar), + } + } + + /// Returns true if the lockdown pattern is present in mbox0. + fn is_locked_down(&self) -> bool { + self.mbox0 !=3D 0 && (self.mbox0 & GSP_LOCKDOWN_MASK) =3D=3D GSP_L= OCKDOWN_PATTERN + } + + /// Combines mailbox0 and mailbox1 into a 64-bit address. + fn combined_addr(&self) -> u64 { + (u64::from(self.mbox1) << 32) | u64::from(self.mbox0) + } + + /// Returns true if GSP lockdown has been released. + /// + /// Checks the lockdown pattern, validates the boot params address, + /// and verifies the HWCFG2 lockdown bit is clear. + fn lockdown_released(&self, bar: &Bar0, fmc_boot_params_addr: u64) -> = bool { + if self.is_locked_down() { + return false; + } + + if self.mbox0 !=3D 0 && self.combined_addr() !=3D fmc_boot_params_= addr { + return true; + } + + let hwcfg2 =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, &crate::f= alcon::gsp::Gsp::ID); + !hwcfg2.riscv_br_priv_lockdown() + } +} + impl super::Gsp { /// Helper function to load and run the FWSEC-FRTS firmware and confir= m that it has properly /// created the WPR2 region. @@ -148,6 +197,35 @@ fn run_booter( booter.run(dev, bar, sec2_falcon, wpr_meta) } =20 + /// Wait for GSP lockdown to be released after FSP Chain of Trust. + #[expect(dead_code)] + fn wait_for_gsp_lockdown_release( + dev: &device::Device, + bar: &Bar0, + gsp_falcon: &Falcon, + fmc_boot_params_addr: u64, + ) -> Result { + dev_dbg!(dev, "Waiting for GSP lockdown release\n"); + + let mbox =3D read_poll_timeout( + || Ok(GspMbox::read(gsp_falcon, bar)), + |mbox| mbox.lockdown_released(bar, fmc_boot_params_addr), + Delta::from_millis(10), + Delta::from_millis(4000), + ) + .inspect_err(|_| { + dev_err!(dev, "GSP lockdown release timeout\n"); + })?; + + if mbox.mbox0 !=3D 0 { + dev_err!(dev, "GSP-FMC boot failed (mbox: {:#x})\n", mbox.mbox= 0); + return Err(EIO); + } + + dev_dbg!(dev, "GSP lockdown released\n"); + Ok(()) + } + /// Attempt to boot the GSP. /// /// This is a GPU-dependent and complex procedure that involves loadin= g firmware files from diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index e70be122e1c9..e59d413dae06 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -321,6 +321,7 @@ pub(crate) fn vga_workspace_addr(self) -> Option { register!(NV_PFALCON_FALCON_HWCFG2 @ PFalconBase[0x000000f4] { 10:10 riscv as bool; 12:12 mem_scrubbing as bool, "Set to 0 after memory scrubbing is com= pleted"; + 13:13 riscv_br_priv_lockdown as bool, "RISC-V branch privilege lockd= own bit"; 31:31 reset_ready as bool, "Signal indicating that reset is complete= d (GA102+)"; }); =20 --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012042.outbound.protection.outlook.com [40.107.200.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2C2E39EF1F; Tue, 17 Mar 2026 22:55:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.42 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788116; cv=fail; b=Ksh3Z15veNXN3JtAvE0MAk96MD200EPe642zf0scY6OFVGUk/5qv/iXjMcFwOQ4NHGQxljxZj5K+qHDqB5uickaJ4EKqdy+AVVUouv5xct6/okIwZCjU0Gw00kS7Fc1sNFGbau+YZnIcW4BSnsYczqOYJ3Qfn8L54aiV17x6cjc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788116; c=relaxed/simple; bh=oloILfzl6POHALXbZewATt2a+upy1q7Sq1vRAw2dWGg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=oP47/o/e7xdv6gKBCPbXdTWJP76SvTcfTGmt0vyYXSwL3+jdnJp3CTT9S6XgmLCj2GTgK/T3/CvnUxCRRlXmsDpEMbGQeN+2R0aCa5n+nip6/QFMz3yxZ8VVF2XaP/jfqT0ESNaNYJZmLhZwZ35jSodgaF51k59ZdKwErFFRcHk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=hpHyP7eY; arc=fail smtp.client-ip=40.107.200.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="hpHyP7eY" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oQdD0loYDbn+mBx6FFQ/zQ9RMq50t65WeTpqaC9mzEld2IxkSqc/zzo/3ajqtvaKdlEZF2ca8teEE6dG1korQnDLR8KanxQSPjCMQ6r3e6Tp/lmCci7EoBJjqMkKi8NQEjdDzkGtySabwf1NIj9uXiGlVbqfmkBRM/ZXp1Za0ltkT9QAVvX/6rJOVC8DPL1VoimoMRzfX91rJOb8FxRuwNj2sbQk2P9DoxBn17YLzKP6vgk/4OS4CcSw8lJHZmdB34rUSAQKEfaxNejymq5J9boQBUFpMDpZNPgFTcbEmSUqwgKzb1JNfGN0pT/0bgagZjGdvM7kDm3I1ZN0uyICrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xMbbAv6GVsnMz91WNebXTNZ1UjV0J01NCdCXowHpysw=; b=qAc9wlpxRRrdX6IWtyBXCj+kBatUvnRDBsCBZ+Dd4i010rbRkkHHeAvrGpPHUYyBCiGQBbOeMPvfhZV5DxTNf7/P0RfdsBqmicen73oyq/Cd1pu+iI2M4qleZ513Xlwc+GRz86Vn1wW5OrRfJxJDv6Szh6vy4X36URKPcqlyD2EFGyv6Ov6Q8CKvaQLCisGQbPyt3jKzShMlHR1fg0rwpDFxPhtsHsn2W25mW7gpQe+qD9LPL8PlPm8J3ACkPOWCVhLpUHcV/wHtR121V8WLtjAzXB01JCVLuRwogXOOnFjC6NlDEgBvRvFxYMlZyF62oeFC79tZkupfM2CMmk1sLA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xMbbAv6GVsnMz91WNebXTNZ1UjV0J01NCdCXowHpysw=; b=hpHyP7eYEKh9wQwqilTrYyH0id1wBJITl7dfFwuYk1r5zgaSH8uYWyFC2Uhbdi9ILe071XT+7isdkTyGpVj5Zy0IZIgrS2SbyJrW4KXixDy/UQEknEd0NF+01snmyhJnwj4rhkRzL8ByafhIp8r6jZvlMV2FGRKX4OrpTuMFWQhgyU5FbP0LzC1HB3nEND3JzRoq4WdWvaMD2E8qazMVs02HMYIe2k5vx5ICnJLBrX0tOvbiTgNFqVx51KdYVLVmbGNGLFCswtBcYsITqQGucuTiHPFpCco8ACKPrQjZWMMy/bIhhj9Oe+qb3UtM6WlyJBcnvtxZ/TDNLzZFi8xBBw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:55:07 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:55:07 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 30/31] gpu: nova-core: Hopper/Blackwell: new location for PCI config mirror Date: Tue, 17 Mar 2026 15:53:54 -0700 Message-ID: <20260317225355.549853-31-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0245.namprd03.prod.outlook.com (2603:10b6:a03:3a0::10) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: 69952cef-9f19-4f59-ffb8-08de84782a20 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: ft37/bPXG9+asqyPlluh1p5BHRUsxVcK2uo9t7CurmTWENtHUKZ8YLYFl0VEjB63hz7+0HgF2Yk4dFJPAiR3tgx5hTEonz3JA5FcIVhIX+l654EXEWU7QFwm0CAyyyfxHYmrjAoPb8rw1/gZvsEL/DtxGQkqG3dc7YXtIcYWh/bML8GyQZ3Ahx30lCAXTo9Ylz58NIs78By3TsHY3bBa1U5dq2iBm2+H3pt26qBmBsVIjfkgIOwRP9osDUZk5k+B2uzCCBt3r4d/rsgDZDyV8U9zuwxPhI9lVwXSbuEkzF20Vtl0fD8o+nKH2auapBJZ4q0XkkLaMnZs7utYZVbA5rF2hD0yaxJ3djB9vz/5dbUw9w52ATc8UJNcZjWJNjJnbbqcnjoMzbcBByfR8hW+pQqoIMgyDv8NoL4M/xDfRcV7G1ELMNAZSMXuOFAEiHGJfDOuTLBidLgWagUd8plke8fs9Db3mMUbaYjqJzxtdO8MM0t9U5zillgGyi4PAR4gg7vBgIWUGxW5+8IgQqk6MkWULWX19uybRYvLcXh45bOF0+JoDJat6wTl33ZNOzOGmJh5YUjrIPIgELGQJiWUOvlRknwnytz9R1unyj30m6CkNv3QhuvdHjgE2Mpq0zeLRfCC8QAHjGceRd4I4YoewcYjtfk0W3RaNyZP41WsKRIu2ojHFnpXveAFFOk+UYIDFpwGT6EHGobBijspaxZaNo8+7+1dz09LXaiM5XAmsSM= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?04cTW0jJOpwCLw9ndzrNtmwhjGZ0xhnrmsl+5/LwUlaT98mTErFJfdsfJIAD?= =?us-ascii?Q?I1gRv564uYCfw5MnyNw8O5VU0q87AxwOo73IqpIfVqXgoJ1EpmTrqtMzjLu+?= =?us-ascii?Q?DZpNoTbgZcI5N7HHumYwDFo4BZKwaaYFB3zGUFrlZGMPqqgQ9iBavUPImzFt?= =?us-ascii?Q?49SlmZ/iZrb8tws0BBP/zUg5gmILMI/P7/T3QKbNqRRsGU1cv7BdD1bSLiQj?= =?us-ascii?Q?uPN7HkH1L3zZDrFj3biBLmus18WDfUkFqA8ZsanAsSIC3Lp1iqR/AhMBqA3q?= =?us-ascii?Q?uWcKLMUUcAQdi+QV1LzGmtDZ6MAbPiy5Ix7RXxWFb4AvwFrRmhv3VBYIPhut?= =?us-ascii?Q?qPfL9FpJbIC7rgJ183xwpSKtce2f3Lt5hNH5NrNXWsbhzJ6C4mhO8aLHyF4V?= =?us-ascii?Q?VTPlk3NbFft6CrWCIQyHdgO+8eHRVC9tByilfipoV2E8ww8pdSg9uenwPLo8?= =?us-ascii?Q?2L24TdqwmecTPr1tC+hBUIUbiG/DNqha9lABcRM8G/K5f6xh80oC24fd/FwY?= =?us-ascii?Q?QP/RngkwpwF/5w9lcM4LMS+raYyOcvJKROJwRVnQzRRbxHKU/OCkU7HKP3bn?= =?us-ascii?Q?fGIrVtdzruCa71cYG2vZC1XunLCQ45W1P/LAMACELES9UiJT7z7VNHT88E7q?= =?us-ascii?Q?GBgkykrt4GiFI+ia66eyGr1S9lbXRVaUCp1nNF9Q6hbBo40486Lph/OVXVIs?= =?us-ascii?Q?1D/UG/jH/lyuZ+xeeHpj6qFAqkPX8XcaOiJhvRfTu1I/F3akXXQE2MCij+VP?= =?us-ascii?Q?YzkRv8BHOidcuDpEQYUairjRAHciFb0mBsYIXMTv6W8hKIl+Aphb+vPchAFi?= =?us-ascii?Q?kl/8XergZL4efgOqEvXKYytlyCIWi/k0VWYLlDbFVt56hfZYW/eoKgRm7lOm?= =?us-ascii?Q?vPThxXdI+onBXQID9kl9gVuy8szkfdlP6n1Tvjr3PRC8Iah+hWCaOUSnueZ5?= =?us-ascii?Q?RumkrN5aneFBt+FkEvw+ZBLONvR2fMpK1GNePk73Tc7LJzDnX73c+ZczpqcD?= =?us-ascii?Q?ujyG3QouQKXJtKdKTV4VfyAt9LcJ/2pV6cATM5H8WbsPAr5+y0ocPAhTMNxb?= =?us-ascii?Q?NIA5hKFAhm0TniuELLQIscKLYJYJ3LJf+MW7MIs1BxqUxZwGw+5i6r9Zu6jz?= =?us-ascii?Q?5AGO9m5UvGUMwr7l3o+8onz3/fg2BKyDA43DiptKK9Z47RG19fThOcm5p3mA?= =?us-ascii?Q?py9kK5sPPN4biDSKu9QsO+a2zALlC6GySsUOtR/qnhg8XTKx7Y2+L7ZYYqSA?= =?us-ascii?Q?+hdQHJU/FnW5+aX2KEHN26aT4goLfifXIG58GEbtvFxajxvHUxq58NZLxBgZ?= =?us-ascii?Q?8spw9RzCsHTPelvMD66xk8hAIk9F1pM7sjhAYIb6soGUQXmBUeoOL/uIpj0k?= =?us-ascii?Q?LRNXFqWe33jIFC4wt6ytuvnTXnsrqs0E/R8bHTX4iA+bf1gX0hWxWZ9556vp?= =?us-ascii?Q?WetYsGIA5L0wXI4TrK9Hpnhr0yIzcCSRBjHIxbtXsOSKBnrXz8KSjNLshfKK?= =?us-ascii?Q?G5/Ul9t47o5ZnetFrr7Pk5DeOtVuvoyOdDRJWRauJPWEjqiM4lDSzSZ44cse?= =?us-ascii?Q?oS2gaGEHQ1jisD5e/CRKxmAy9zqEcptR/HqnrpvtZs0/+2d/Pf6WoALY6Deh?= =?us-ascii?Q?I4IlgMWlAxzU4mD0kFOZyCVAlPxwqi0t0vDSG5ys4whWkGVxa/FPtGzJJ5j7?= =?us-ascii?Q?e2ps0NFtvKytqmL4H4ZblUsKjXDrtOeh3DfvFph6JEDRQ+kOB1xzelifNQPD?= =?us-ascii?Q?Zj640av99Q=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 69952cef-9f19-4f59-ffb8-08de84782a20 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:37.2694 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2Zbxs2SCDfVA19gkCuf7lu6R+inaAbAMs0HmxNCeFPUsimbmyvboa5kxMo+F0bqZMIMGhMiuvTioctp5VzF2Vw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Hopper and Blackwell GPUs use a different PCI config space mirror address (0x088000) compared to older architectures (0x088480). Update SetSystemInfo to accept a chipset parameter and select the correct address based on architecture. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/gsp/boot.rs | 2 +- drivers/gpu/nova-core/gsp/commands.rs | 8 +++++--- drivers/gpu/nova-core/gsp/fw/commands.rs | 20 +++++++++++++++++--- 3 files changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index a3ab0bd7a317..7db811e90825 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -257,7 +257,7 @@ pub(crate) fn boot( dma_write!(wpr_meta, [0]?, GspFwWprMeta::new(&gsp_fw, &fb_layout)); =20 self.cmdq - .send_command(bar, commands::SetSystemInfo::new(pdev))?; + .send_command(bar, commands::SetSystemInfo::new(pdev, chipset)= )?; self.cmdq.send_command(bar, commands::SetRegistry::new())?; =20 gsp_falcon.reset(bar)?; diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index 8f270eca33be..e6a9a1fc6296 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -20,6 +20,7 @@ =20 use crate::{ driver::Bar0, + gpu::Chipset, gsp::{ cmdq::{ Cmdq, @@ -37,12 +38,13 @@ /// The `GspSetSystemInfo` command. pub(crate) struct SetSystemInfo<'a> { pdev: &'a pci::Device, + chipset: Chipset, } =20 impl<'a> SetSystemInfo<'a> { /// Creates a new `GspSetSystemInfo` command using the parameters of `= pdev`. - pub(crate) fn new(pdev: &'a pci::Device) -> Self { - Self { pdev } + pub(crate) fn new(pdev: &'a pci::Device, chipset: Chips= et) -> Self { + Self { pdev, chipset } } } =20 @@ -52,7 +54,7 @@ impl<'a> CommandToGsp for SetSystemInfo<'a> { type InitError =3D Error; =20 fn init(&self) -> impl Init { - GspSetSystemInfo::init(self.pdev) + GspSetSystemInfo::init(self.pdev, self.chipset) } } =20 diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-co= re/gsp/fw/commands.rs index db46276430be..1dca2552ed54 100644 --- a/drivers/gpu/nova-core/gsp/fw/commands.rs +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -10,7 +10,13 @@ }, // }; =20 -use crate::gsp::GSP_PAGE_SIZE; +use crate::{ + gpu::{ + Architecture, + Chipset, // + }, + gsp::GSP_PAGE_SIZE, // +}; =20 use super::bindings; =20 @@ -24,7 +30,10 @@ pub(crate) struct GspSetSystemInfo { impl GspSetSystemInfo { /// Returns an in-place initializer for the `GspSetSystemInfo` command. #[allow(non_snake_case)] - pub(crate) fn init<'a>(dev: &'a pci::Device) -> impl In= it + 'a { + pub(crate) fn init<'a>( + dev: &'a pci::Device, + chipset: Chipset, + ) -> impl Init + 'a { type InnerGspSystemInfo =3D bindings::GspSystemInfo; let init_inner =3D try_init!(InnerGspSystemInfo { gpuPhysAddr: dev.resource_start(0)?, @@ -35,7 +44,12 @@ pub(crate) fn init<'a>(dev: &'a pci::Device) -> impl Init 0x088000, + Architecture::Hopper | Architecture::Blackwell =3D> 0x0920= 00, + }, pciConfigMirrorSize: 0x001000, =20 PCIDeviceID: (u32::from(dev.device_id()) << 16) | u32::from(de= v.vendor_id().as_raw()), --=20 2.53.0 From nobody Mon Apr 6 21:32:23 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012042.outbound.protection.outlook.com [40.107.200.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E01D3F7E8B; Tue, 17 Mar 2026 22:55:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.42 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788118; cv=fail; b=mjQmsZU5NBEqAf+v7GLiR1VwCHOooGYaoOxbiSPcobCz8owOJUTxhKFI7sCyWeGK8iVQc49KrGtBLViQWX0yA3jlqKRKu0x6Wqk6XKpGW6LS7XtwDfALVGE9zRtm7Zl9iemW2ijnm/ANk7yW5focQ9CQyHTwwjN7xT4wI2Dq8is= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773788118; c=relaxed/simple; bh=uFiFZFWe2gRizISHB2jX3mDq9W/PvylOeP9Q+wly9Es=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=A+etFYze4QUAL7/8YwuZBFY8vw36Bwu1g0ycmErf+r+jEdK7/JL3G61oQYgnx+F4utJyotpftj7DsxqXlp1RCd+3ZdNdUuqaFonYoWDLAIj704cwkMG/XzZDiwW5iyvsKOYB+zRc7FuOhqZfA9QTq2TlHf7H0R3ngTehw8yvgi4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=N4ipS8xc; arc=fail smtp.client-ip=40.107.200.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="N4ipS8xc" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=JGfe+OrWz8wTWFX/CCYOfBq31XPETK5D5YsC5ybPqHgqZEnrP0yxeijnK3TE6NtpEJW5tmruJ8rBv4NEt46ydxbZPmglQSNNu2oij5Q9Qq49lyccTl48o5kko/sY8S5tIh/5TPufcWsTCW/CWRnQSEhEQZX0+BD5WM1gPoQ8y7/OiDVeNvRXaEXi7E5BzcwMvO+LA4jW0JfJwZEX8ad7tv7HXxpFOhmt7FwiKznIFykHCK6VRQHf+46BssQUEybno3WIOB8Pi+B7Fwg5Pw+G9/3Ia5G0esYi5/yNeYGelca6NdV/lOARmJH+Vo9JwrIM0qVwnZfljHLCyZ6CHwM6OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Go5sNPfOTph4tltNXQgP2r4jtPYuAKz5FtA2LqEcMfM=; b=G/QzwhtIKeYrbOojxYFa4uDTVjIQqTy8unS3pv/7ipoJ3HUvmnniDHahlfewyp4XY664r2zPd++5eAH3l11D0WSz5Dncw+3PnRjQTU5D0vmkgalIdLMtHkznpBUbDjnLRc2/OZ8iCP2tmhTqBrqzt44e/9TYMdo2ptvMvfS1JN4mIrghtDn2drnWZjfHwf9buJOtniAMBXG1AvYLn3MTYmwMN7cwl1WQ4he43UNNv2a1uBVaCLG064RkiS5gBwfmesmlotKKIUycztU7zYN/fburVbCpqGDbvoodsnKNGESznUbpois3CGVKcaS2umbmDaWl6whiLj4I3wMtbOehPg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Go5sNPfOTph4tltNXQgP2r4jtPYuAKz5FtA2LqEcMfM=; b=N4ipS8xcdd6pEikFNzRwn9rTxagZv/Z0tx9L/NeVrXvLGg45qqgj8zeWeDWRxZWyVYPcb4YFNFTdkcRuzYG6VcoqljEKmUf+/QV/5WjAZOC26eBZ0PxTizL+X8m0JCt45G2Nb/14M2GI1B+SaOujgMu7t6HHOlbV0LCTq1zWzCQ8kYQEtwErBrk5HHmOdrdO7y86Qzy0y7oO3svqj2bIL5Ji2J2PzkjfRY27rUf6t8FZ8e73G6/CsmNdlW10AcHJZTMys9Qwr+FWp9tzYAo8xJUikaPY8kl2Iepg/5YTpyK4aVe+Sx0GacryuC1WvK3zcV6yF4SYeJDiOohi1qWDyQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) by LV2PR12MB5848.namprd12.prod.outlook.com (2603:10b6:408:173::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19; Tue, 17 Mar 2026 22:55:11 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%7]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 22:55:11 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Joel Fernandes , Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , rust-for-linux@vger.kernel.org, LKML , John Hubbard Subject: [PATCH v7 31/31] gpu: nova-core: Hopper/Blackwell: integrate FSP boot path into boot() Date: Tue, 17 Mar 2026 15:53:55 -0700 Message-ID: <20260317225355.549853-32-jhubbard@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260317225355.549853-1-jhubbard@nvidia.com> References: <20260317225355.549853-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR13CA0138.namprd13.prod.outlook.com (2603:10b6:a03:2c6::23) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|LV2PR12MB5848:EE_ X-MS-Office365-Filtering-Correlation-Id: 91062126-2845-47f7-e1a8-08de84782ace X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: l59AN+zMvTM8VWaEv1HvAIACyRFRqNaRF8U9gBOdTyPzGm0JHfOzKY3QpB4C/iw1zQZnZAodDN6PUenPnrN9eqB2NrPJqsu/2rRBddY4CXPq0fnb9VSfXCd93Efiy1/ZwpkFh07SQXq5sHMAD5iQcoxg0aAEF/10BUzWiLKct7NTJ4GDQDFb+MVO0bBdUsEMF5jR5CzYGrbajDe4Oq0U7rlLaNQ83j+fhyLSIILljKjttqtGMD9FtLXTcppjv8HNza+n7Wb5htvyZujt1+d77TqYqSGqm8qmD/Apc/mBhVk1sYELKi3LoRqNCECwGqyOYPdHFXz/VC55zTgfpD3N4GVZFRz9XfzplyQSwK+tR2LYrrD0uREZuXfHU+RzgRNRkP+ndgdZq5jaBBo1PEIXZ37C7CB57a2UDYRyZBQpc93/hOFT6hXxqVMCve5qHrPj6flBUJHdOtk+nTtF8iEMzEb/Pf/XGMrU2S5v8pLnZORm4DyQWoT435uG/lSFgwJHwKePG0nmXXCDzCowktuqcRFbohcPHz3VEjxkblw+/wAHS/Sn2IrYemyD7/AfCz2ixL9xPUGHHUgbrp7HN4V8YuXc0sdruc28Ie/Kr1jEUVbFPUkQnC24FAgJzVgO2QjxNpYrdFIXQWf/eH6QsH38ZDmLBvGQezjHbUD0tdy9KDPkp+DU6YrMmoxl6QpLiduTflm5YC7L/n1l9TCB9s6aKLgQ4D3xtHDVyWAg2Hg8794= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM3PR12MB9416.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?N7bH6OmHoUl3moK+rnzBhmsQj9GulobZtYNQB40+Lt5wuWzaflYaGGsWz6wl?= =?us-ascii?Q?nyHaCpE1oWlQYr1ZYnm1D0u/esOjv+Uwi73wBbUuG3tf3mRuTUrYCoD5Bjob?= =?us-ascii?Q?uzpmDQR/xO0jrHuQY/7D9GXf5AFR3TS5E9o+P7pfmuRpZqtJhFyioZg92GFd?= =?us-ascii?Q?aG8zp1rQO4ZmN2bg2paRqCKs8kD2PlbB7v03WVmjELHZlCRL/mi/9oSuM9QL?= =?us-ascii?Q?uGRHYCOrIIOZxyqE9cSHjtz7OJgmN7Qvau3+B82/x/Hv4KtlYLtJvoyyOiae?= =?us-ascii?Q?hNTh71ZsmYOSZZFX/JDf1oSWLq8Is9lktvY7xjuL9k7HUR3BpqZ+8nDHU88i?= =?us-ascii?Q?YxJdLJLr9kHeb4pTzeZhNN8saOj5HShs8qGBGZzdvnVdDqbsak2CrOrSzg/t?= =?us-ascii?Q?vzdJqxWs8rJae6+/uX51TFdG2KbC30GmaLV9dlHrcJSX+ZwaTydjLNfAOcJG?= =?us-ascii?Q?p8X1BhXsU8Wt6oXYs0Af8tu4VHGYj0Npp0dnClOZc/4BNjE25StmZFlzE8OR?= =?us-ascii?Q?G2zg4pMraDjEPoldSnMm+X4QVT0OTWh6BJ5Ck9EcB5ZOUOgfM4WZ11F8tksV?= =?us-ascii?Q?V1TGHBh+twTkJJgeukHEvPTrUhzy+wWh6kYyPypsa+Nr4AfUyFRnNFlPFfB8?= =?us-ascii?Q?JSCNHIxYwsjgYCx6A7zi7cU/N8MCS9qcvaoSn/ORZ2TPU+Ow46d/2WUJI79F?= =?us-ascii?Q?dDcQewI7IdQW0GOMAvx+rz66WNby8ZCKvg+pQQEjwjVEKPOQgSfBsBzYIyd2?= =?us-ascii?Q?cOLVI40c+QRdANdaviyk1BbMJvmwfNYXSxkjDQrhqASapwfiyXxj9ahpkrtf?= =?us-ascii?Q?mCRBIv0rOVpyn/jdOo+0vAvli7CaDuZUfDfFMwf32WA7qdnI1WtF1s+aYKD3?= =?us-ascii?Q?qQxTHvQQz18XIzrhcw3iUf+MuRk731v4HMGS5VkK+6wqbvK0uFHX58op2cBy?= =?us-ascii?Q?cK5bb1eCQBRzSakv7KMeAAa93qVzfW8RinKVnkjI0OT313exTSaUYRtfnO9W?= =?us-ascii?Q?HCaKtGI/cV4Rry95qTtiZkUJ662vKiJuAzlTWLCExXre6Y5eFt1FhljdXzrJ?= =?us-ascii?Q?/lG3I0JKwEupR3v4QdLMsW0FXtzsvWwPpjBL69mskHKWU9OKoVQAasGmRR5l?= =?us-ascii?Q?998XupsqdSnYlkHIVaMxlfYCShZfTUkRczo7Couor/tz5BBDcXI9NH/XzuCK?= =?us-ascii?Q?GmxEhiTfQu2bpoIt9Z8AcAAoH8fXRNMxXVF+ZPwq8hblah54LKEtbHW3MqCm?= =?us-ascii?Q?Dn1vNbVdROUbypPKZY6H5odc7IyH1+hyfXXohYTJ6XJHmQ81gu7Nr7nSJnoP?= =?us-ascii?Q?ljSn3CClcg3iNnsSsKYddUMOmis9dKkM3unMijMuhyCeTKjh9YNr0PG2bfks?= =?us-ascii?Q?rUVII+0EWyFJwMZJ81gkxoFbnSBRZn1iW7eimVgFrceW47jvzjppfygMxWnc?= =?us-ascii?Q?I/twxq2MSOs8Uq1Z88VKQ/urleYmGbJjYXXycKPQlYmAlWgUzQz2OcpHaEtC?= =?us-ascii?Q?Y3/dtlojsSYAcR/A53P3Q9J6rYTHiVniQHqpIZiYAss/kiZk/l4sKjPLtE6S?= =?us-ascii?Q?FQziRsmehaQsMuGAtuSvGYwtxeyyFF76wAnRD9MjC0fzeu6IQmDmjZwsfWYz?= =?us-ascii?Q?ACczgfJsVX4CWhl5YfZ6vZMzLmdrHFGuo/LQDMOtH+Ue6ZdnC5rWgjfCO77Z?= =?us-ascii?Q?f938S9tcGuZxOPePk2W3mMgqh/uXCmHIqmDmRYy7xw+gfw6UZzFL1Kvcagbh?= =?us-ascii?Q?/Fwu5lQvJQ=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 91062126-2845-47f7-e1a8-08de84782ace X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 22:54:38.3830 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mSsvz2fqqjCvzBHuFfxOKZklK5kTj8IoPmxe79HtKkdawpsuLF4ShHmZzhgde3ma9oKgAIONxezOYw+ebtR0rA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5848 Content-Type: text/plain; charset="utf-8" Add the FSP boot path for Hopper and Blackwell GPUs. These architectures use FSP with FMC firmware for Chain of Trust boot, rather than SEC2. boot() now dispatches to boot_via_sec2() or boot_via_fsp() based on architecture. The SEC2 path keeps its original command ordering. The FSP path sends SetSystemInfo/SetRegistry after GSP becomes active. The GSP sequencer only runs for SEC2-based architectures. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware/fsp.rs | 2 - drivers/gpu/nova-core/fsp.rs | 5 - drivers/gpu/nova-core/gsp/boot.rs | 181 ++++++++++++++++++++------ 3 files changed, 144 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/nova-core/firmware/fsp.rs b/drivers/gpu/nova-core/= firmware/fsp.rs index e5059d59a4b7..e981f2316d01 100644 --- a/drivers/gpu/nova-core/firmware/fsp.rs +++ b/drivers/gpu/nova-core/firmware/fsp.rs @@ -14,7 +14,6 @@ gpu::Chipset, // }; =20 -#[expect(dead_code)] pub(crate) struct FspFirmware { /// FMC firmware image data (only the "image" ELF section). pub(crate) fmc_image: DmaObject, @@ -23,7 +22,6 @@ pub(crate) struct FspFirmware { } =20 impl FspFirmware { - #[expect(dead_code)] pub(crate) fn new( dev: &device::Device, chipset: Chipset, diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index 68bcfe45aec6..06909217e564 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -227,7 +227,6 @@ pub(crate) struct FmcBootArgs<'a> { impl<'a> FmcBootArgs<'a> { /// Build FMC boot arguments, allocating the DMA-coherent boot paramet= er /// structure that FSP will read. - #[expect(dead_code)] #[allow(clippy::too_many_arguments)] pub(crate) fn new( dev: &device::Device, @@ -283,7 +282,6 @@ pub(crate) fn new( =20 /// DMA address of the FMC boot parameters, needed after boot for lock= down /// release polling. - #[expect(dead_code)] pub(crate) fn boot_params_dma_handle(&self) -> u64 { self.fmc_boot_params.dma_handle() } @@ -296,7 +294,6 @@ impl Fsp { /// /// Polls the thermal scratch register until FSP signals boot completi= on /// or timeout occurs. - #[expect(dead_code)] pub(crate) fn wait_secure_boot( dev: &device::Device, bar: &crate::driver::Bar0, @@ -326,7 +323,6 @@ pub(crate) fn wait_secure_boot( /// /// Extracts real cryptographic signatures from FMC ELF32 firmware sec= tions. /// Returns signatures in a heap-allocated structure to prevent stack = overflow. - #[expect(dead_code)] pub(crate) fn extract_fmc_signatures( dev: &device::Device, fmc_fw_data: &[u8], @@ -393,7 +389,6 @@ pub(crate) fn extract_fmc_signatures( /// /// Builds the COT message from the pre-configured [`FmcBootArgs`], se= nds it /// to FSP, and waits for the response. - #[expect(dead_code)] pub(crate) fn boot_fmc( dev: &device::Device, bar: &crate::driver::Bar0, diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 7db811e90825..4bd226573b89 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -13,6 +13,7 @@ use crate::{ driver::Bar0, falcon::{ + fsp::Fsp as FspEngine, gsp::Gsp, sec2::Sec2, Falcon, @@ -24,6 +25,7 @@ BooterFirmware, BooterKind, // }, + fsp::FspFirmware, fwsec::{ bootloader::FwsecFirmwareWithBl, FwsecCommand, @@ -32,9 +34,17 @@ gsp::GspFirmware, FIRMWARE_VERSION, // }, - gpu::Chipset, + fsp::{ + FmcBootArgs, + Fsp, // + }, + gpu::{ + Architecture, + Chipset, // + }, gsp::{ commands, + fw::LibosMemoryRegionInitArgument, sequencer::{ GspSequencer, GspSequencerParams, // @@ -197,8 +207,83 @@ fn run_booter( booter.run(dev, bar, sec2_falcon, wpr_meta) } =20 + /// Boot GSP via SEC2 booter firmware (Turing/Ampere/Ada path). + /// + /// This path uses FWSEC-FRTS to set up WPR2, then boots GSP directly, + /// then uses SEC2 to run the booter firmware. + #[allow(clippy::too_many_arguments)] + fn boot_via_sec2( + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + gsp_falcon: &Falcon, + sec2_falcon: &Falcon, + fb_layout: &FbLayout, + libos: &CoherentAllocation, + wpr_meta: &CoherentAllocation, + ) -> Result { + // Run FWSEC-FRTS to set up the WPR2 region + let bios =3D Vbios::new(dev, bar)?; + Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, fb_layo= ut)?; + + // Reset and boot GSP before SEC2 + gsp_falcon.reset(bar)?; + let libos_handle =3D libos.dma_handle(); + let (mbox0, mbox1) =3D gsp_falcon.boot( + bar, + Some(libos_handle as u32), + Some((libos_handle >> 32) as u32), + )?; + dev_dbg!(dev, "GSP MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1); + dev_dbg!( + dev, + "Using SEC2 to load and run the booter_load firmware...\n" + ); + + // Run booter via SEC2 + Self::run_booter(dev, bar, chipset, sec2_falcon, wpr_meta) + } + + /// Boot GSP via FSP Chain of Trust (Hopper/Blackwell+ path). + /// + /// This path uses FSP to establish a chain of trust and boot GSP-FMC.= FSP handles + /// the GSP boot internally - no manual GSP reset/boot is needed. + fn boot_via_fsp( + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + gsp_falcon: &Falcon, + wpr_meta: &CoherentAllocation, + libos: &CoherentAllocation, + ) -> Result { + let fsp_falcon =3D Falcon::::new(dev, chipset)?; + + Fsp::wait_secure_boot(dev, bar, chipset.arch())?; + + let fsp_fw =3D FspFirmware::new(dev, chipset, FIRMWARE_VERSION)?; + + let signatures =3D Fsp::extract_fmc_signatures(dev, &fsp_fw.fmc_fu= ll)?; + + let args =3D FmcBootArgs::new( + dev, + chipset, + &fsp_fw.fmc_image, + wpr_meta.dma_handle(), + core::mem::size_of::() as u32, + libos.dma_handle(), + false, + &signatures, + )?; + + Fsp::boot_fmc(dev, bar, &fsp_falcon, &args)?; + + let fmc_boot_params_addr =3D args.boot_params_dma_handle(); + Self::wait_for_gsp_lockdown_release(dev, bar, gsp_falcon, fmc_boot= _params_addr)?; + + Ok(()) + } + /// Wait for GSP lockdown to be released after FSP Chain of Trust. - #[expect(dead_code)] fn wait_for_gsp_lockdown_release( dev: &device::Device, bar: &Bar0, @@ -242,40 +327,49 @@ pub(crate) fn boot( sec2_falcon: &Falcon, ) -> Result { let dev =3D pdev.as_ref(); - - let bios =3D Vbios::new(dev, bar)?; + let uses_sec2 =3D matches!( + chipset.arch(), + Architecture::Turing | Architecture::Ampere | Architecture::Ada + ); =20 let gsp_fw =3D KBox::pin_init(GspFirmware::new(dev, chipset, FIRMW= ARE_VERSION), GFP_KERNEL)?; =20 let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw)?; dev_dbg!(dev, "{:#x?}\n", fb_layout); =20 - Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, &fb_lay= out)?; - let wpr_meta =3D CoherentAllocation::::alloc_coherent(dev, 1, GFP= _KERNEL | __GFP_ZERO)?; dma_write!(wpr_meta, [0]?, GspFwWprMeta::new(&gsp_fw, &fb_layout)); =20 - self.cmdq - .send_command(bar, commands::SetSystemInfo::new(pdev, chipset)= )?; - self.cmdq.send_command(bar, commands::SetRegistry::new())?; + // Architecture-specific boot path + if uses_sec2 { + // SEC2 path: send commands before GSP reset/boot (original or= der). + self.cmdq + .send_command(bar, commands::SetSystemInfo::new(pdev, chip= set))?; + self.cmdq.send_command(bar, commands::SetRegistry::new())?; =20 - gsp_falcon.reset(bar)?; - let libos_handle =3D self.libos.dma_handle(); - let (mbox0, mbox1) =3D gsp_falcon.boot( - bar, - Some(libos_handle as u32), - Some((libos_handle >> 32) as u32), - )?; - dev_dbg!(pdev, "GSP MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1); - - dev_dbg!( - pdev, - "Using SEC2 to load and run the booter_load firmware...\n" - ); - - Self::run_booter(dev, bar, chipset, sec2_falcon, &wpr_meta)?; + Self::boot_via_sec2( + dev, + bar, + chipset, + gsp_falcon, + sec2_falcon, + &fb_layout, + &self.libos, + &wpr_meta, + )?; + } else { + Self::boot_via_fsp( + dev, + bar, + chipset, + gsp_falcon, + &wpr_meta, + &self.libos, + )?; + } =20 + // Common post-boot initialization gsp_falcon.write_os_version(bar, gsp_fw.bootloader.app_version); =20 // Poll for RISC-V to become active before running sequencer @@ -286,18 +380,31 @@ pub(crate) fn boot( Delta::from_secs(5), )?; =20 - dev_dbg!(pdev, "RISC-V active? {}\n", gsp_falcon.is_riscv_active(b= ar),); + dev_dbg!(dev, "RISC-V active? {}\n", gsp_falcon.is_riscv_active(ba= r)); =20 - // Create and run the GSP sequencer. - let seq_params =3D GspSequencerParams { - bootloader_app_version: gsp_fw.bootloader.app_version, - libos_dma_handle: libos_handle, - gsp_falcon, - sec2_falcon, - dev: pdev.as_ref().into(), - bar, - }; - GspSequencer::run(&mut self.cmdq, seq_params)?; + // For FSP path, send commands after GSP becomes active. + if matches!( + chipset.arch(), + Architecture::Hopper | Architecture::Blackwell + ) { + self.cmdq + .send_command(bar, commands::SetSystemInfo::new(pdev, chip= set))?; + self.cmdq.send_command(bar, commands::SetRegistry::new())?; + } + + // SEC2-based architectures need to run the GSP sequencer + if uses_sec2 { + let libos_handle =3D self.libos.dma_handle(); + let seq_params =3D GspSequencerParams { + bootloader_app_version: gsp_fw.bootloader.app_version, + libos_dma_handle: libos_handle, + gsp_falcon, + sec2_falcon, + dev: dev.into(), + bar, + }; + GspSequencer::run(&mut self.cmdq, seq_params)?; + } =20 // Wait until GSP is fully initialized. commands::wait_gsp_init_done(&mut self.cmdq)?; @@ -305,8 +412,8 @@ pub(crate) fn boot( // Obtain and display basic GPU information. let info =3D commands::get_gsp_info(&mut self.cmdq, bar)?; match info.gpu_name() { - Ok(name) =3D> dev_info!(pdev, "GPU name: {}\n", name), - Err(e) =3D> dev_warn!(pdev, "GPU name unavailable: {:?}\n", e), + Ok(name) =3D> dev_info!(dev, "GPU name: {}\n", name), + Err(e) =3D> dev_warn!(dev, "GPU name unavailable: {:?}\n", e), } =20 Ok(()) --=20 2.53.0