From nobody Mon Apr 6 21:33:52 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4C13337F74B for ; Tue, 17 Mar 2026 18:17:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773771433; cv=none; b=H50qAIDEJ1sqzhLGUwEHhnSw7ecvZnA1C6jjEJfQGopTDJOZHyeBOgqrY8TaUVQaVEhx5gqJia9RQEoHfnQTUK09orsHKWmQLxOSqDDcKhHldVM/DEcirZFOFVHC5lJ/Rc1oCPxJIff25ZvvUCLEU67Jx1uRYLO/UdamozLV3/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773771433; c=relaxed/simple; bh=bHG8mAyQCGN87SH0aQIIesKa/spGiziM2+5yRhuT5zw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ceg44L631nCpAqe5HwIRyTkRTexPd3aaNGFWImPysWU8GryTwtLCKcz7DTn/frzXxPiXOovr5iFPvWhpDfma9f4yWVkYSjiaTP7vI/nm8DpZeC8KmdpA7UwYJWLpDxyVaIceHlebOIJG2AKaL1hdlaBDDYgG5DcRpnOYjzoKGKo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 90D7516F2; Tue, 17 Mar 2026 11:17:05 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8A2403F7BD; Tue, 17 Mar 2026 11:17:10 -0700 (PDT) From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@linaro.org, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, Yeoreum Yun Subject: [PATCH 1/2] coresight: etm4x: fix inconsistencies with sysfs configration Date: Tue, 17 Mar 2026 18:17:04 +0000 Message-Id: <20260317181705.2456271-2-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317181705.2456271-1-yeoreum.yun@arm.com> References: <20260317181705.2456271-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current ETM4x configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. - Once a perf session is enabled, some read-only register fields (e.g., TRCSSCSR) may not be reported correctly, because drvdata->config is cleared while enabling with perf mode, even though the information was previously read via etm4_init_arch_data= (). To resolve these inconsistencies, the configuration should be separated int= o: - active_config, which represents the currently applied configuration - config, which stores the settings configured via sysfs. Signed-off-by: Yeoreum Yun --- .../hwtracing/coresight/coresight-etm4x-cfg.c | 2 +- .../coresight/coresight-etm4x-core.c | 45 +++++++++++-------- drivers/hwtracing/coresight/coresight-etm4x.h | 2 + 3 files changed, 30 insertions(+), 19 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hw= tracing/coresight/coresight-etm4x-cfg.c index c302072b293a..84213d40d1ae 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *= drvdata, struct cscfg_regval_csdev *reg_csdev, u32 offset) { int err =3D -EINVAL, idx; - struct etmv4_config *drvcfg =3D &drvdata->config; + struct etmv4_config *drvcfg =3D &drvdata->active_config; u32 off_mask; =20 if (((offset >=3D TRCEVENTCTL0R) && (offset <=3D TRCVIPCSSCTLR)) || diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index d565a73f0042..c552129c4a0c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -88,9 +88,11 @@ static int etm4_probe_cpu(unsigned int cpu); */ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) { + struct etmv4_config *config =3D &drvdata->active_config; + return (n < drvdata->nr_ss_cmp) && drvdata->nr_pe && - (drvdata->config.ss_status[n] & TRCSSCSRn_PC); + (config->ss_status[n] & TRCSSCSRn_PC); } =20 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) @@ -266,10 +268,11 @@ static void etm4x_prohibit_trace(struct etmv4_drvdata= *drvdata) static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) { u64 trfcr =3D drvdata->trfcr; + struct etmv4_config *config =3D &drvdata->active_config; =20 - if (drvdata->config.mode & ETM_MODE_EXCL_KERN) + if (config->mode & ETM_MODE_EXCL_KERN) trfcr &=3D ~TRFCR_EL1_ExTRE; - if (drvdata->config.mode & ETM_MODE_EXCL_USER) + if (config->mode & ETM_MODE_EXCL_USER) trfcr &=3D ~TRFCR_EL1_E0TRE; =20 return trfcr; @@ -277,7 +280,7 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvd= ata *drvdata) =20 /* * etm4x_allow_trace - Allow CPU tracing in the respective ELs, - * as configured by the drvdata->config.mode for the current + * as configured by the drvdata->active_config.mode for the current * session. Even though we have TRCVICTLR bits to filter the * trace in the ELs, it doesn't prevent the ETM from generating * a packet (e.g, TraceInfo) that might contain the addresses from @@ -288,12 +291,13 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_dr= vdata *drvdata) static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) { u64 trfcr, guest_trfcr; + struct etmv4_config *config =3D &drvdata->active_config; =20 /* If the CPU doesn't support FEAT_TRF, nothing to do */ if (!drvdata->trfcr) return; =20 - if (drvdata->config.mode & ETM_MODE_EXCL_HOST) + if (config->mode & ETM_MODE_EXCL_HOST) trfcr =3D drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); else trfcr =3D etm4x_get_kern_user_filter(drvdata); @@ -301,7 +305,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drv= data) write_trfcr(trfcr); =20 /* Set filters for guests and pass to KVM */ - if (drvdata->config.mode & ETM_MODE_EXCL_GUEST) + if (config->mode & ETM_MODE_EXCL_GUEST) guest_trfcr =3D drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); else guest_trfcr =3D etm4x_get_kern_user_filter(drvdata); @@ -494,7 +498,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata = *drvdata) static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; struct coresight_device *csdev =3D drvdata->csdev; struct device *etm_dev =3D &csdev->dev; struct csdev_access *csa =3D &csdev->access; @@ -666,7 +670,7 @@ static int etm4_config_timestamp_event(struct etmv4_drv= data *drvdata, { int ctridx; int rselector; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; =20 /* No point in trying if we don't have at least one counter */ if (!drvdata->nr_cntr) @@ -749,7 +753,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, { int ret =3D 0; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; struct perf_event_attr max_timestamp =3D { .ATTR_CFG_FLD_timestamp_CFG =3D U64_MAX, }; @@ -911,14 +915,17 @@ static int etm4_enable_sysfs(struct coresight_device = *csdev, struct coresight_pa =20 /* enable any config activated by configfs */ cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); + + raw_spin_lock(&drvdata->spinlock); + + drvdata->active_config =3D drvdata->config; + if (cfg_hash) { ret =3D cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); if (ret) return ret; } =20 - raw_spin_lock(&drvdata->spinlock); - drvdata->trcid =3D path->trace_id; =20 /* Tracer will never be paused in sysfs mode */ @@ -1028,7 +1035,7 @@ static void etm4_disable_trace_unit(struct etmv4_drvd= ata *drvdata) static void etm4_disable_hw(struct etmv4_drvdata *drvdata) { u32 control; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; struct coresight_device *csdev =3D drvdata->csdev; struct csdev_access *csa =3D &csdev->access; int i; @@ -1374,12 +1381,14 @@ static void etm4_init_arch_data(void *info) u32 etmidr5; struct etm4_init_arg *init_arg =3D info; struct etmv4_drvdata *drvdata; + struct etmv4_config *config; struct csdev_access *csa; struct device *dev =3D init_arg->dev; int i; =20 drvdata =3D dev_get_drvdata(init_arg->dev); csa =3D init_arg->csa; + config =3D &drvdata->active_config; =20 /* * If we are unable to detect the access mechanism, @@ -1440,7 +1449,7 @@ static void etm4_init_arch_data(void *info) =20 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ drvdata->s_ex_level =3D FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); - drvdata->config.s_ex_level =3D drvdata->s_ex_level; + config->s_ex_level =3D drvdata->s_ex_level; /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ drvdata->ns_ex_level =3D FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); /* @@ -1491,8 +1500,7 @@ static void etm4_init_arch_data(void *info) */ drvdata->nr_ss_cmp =3D FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); for (i =3D 0; i < drvdata->nr_ss_cmp; i++) { - drvdata->config.ss_status[i] =3D - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); + config->ss_status[i] =3D etm4x_relaxed_read32(csa, TRCSSCSRn(i)); } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ drvdata->numcidc =3D FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); @@ -1685,7 +1693,7 @@ static void etm4_set_default(struct etmv4_config *con= fig) static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 typ= e) { int nr_comparator, index =3D 0; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; =20 /* * nr_addr_cmp holds the number of comparator _pair_, so time 2 @@ -1726,7 +1734,7 @@ static int etm4_set_event_filters(struct etmv4_drvdat= a *drvdata, { int i, comparator, ret =3D 0; u64 address; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; struct etm_filters *filters =3D event->hw.addr_filters; =20 if (!filters) @@ -2246,7 +2254,8 @@ static int etm4_add_coresight_dev(struct etm4_init_ar= g *init_arg) if (!desc.name) return -ENOMEM; =20 - etm4_set_default(&drvdata->config); + etm4_set_default(&drvdata->active_config); + drvdata->config =3D drvdata->active_config; =20 pdata =3D coresight_get_platform_data(dev); if (IS_ERR(pdata)) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 89d81ce4e04e..76beb896f188 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1022,6 +1022,7 @@ struct etmv4_save_state { * allows tracing at all ELs. We don't want to compute this * at runtime, due to the additional setting of TRFCR_CX when * in EL2. Otherwise, 0. + * @active_config: structure holding current applied configuration paramet= ers. * @config: structure holding configuration parameters. * @save_state: State to be preserved across power loss * @skip_power_up: Indicates if an implementation can skip powering up @@ -1079,6 +1080,7 @@ struct etmv4_drvdata { bool skip_power_up : 1; bool paused : 1; u64 trfcr; + struct etmv4_config active_config; struct etmv4_config config; struct etmv4_save_state *save_state; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Mon Apr 6 21:33:52 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7D2B237F8DC for ; Tue, 17 Mar 2026 18:17:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773771435; cv=none; b=lnsfLNfwCk9dJ2AiFidlMKGw+XsbIEhbXgtCZkO1U9iHUaidMZhtMTdyY3wr9VWT3MNru3aYbX7jP3p2qW+d1nSXVArrRNl2F0q5Jnv8Lj70U/anVnBcJUX4/c/R6gXG/agqzeUAbx1f+O25ulBpypOcZajxhATbeL1lnFCewrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773771435; c=relaxed/simple; bh=40EpJEs0WaVO6ZN7UUiqmQPXqww499Yu1LeOXgerpuw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TqghnnjMvQjiWkwDe+FPgQamya4QkPuniempL1DzEl67y8NiuDo34SE4q8hcgzbjmFWY5SJSc/vanOpPubCTtpQQIZHwEGK3GW216IoAYqwGjJW1S96HGmLA7HsmUeQex9emwkufoOkHbYDhlvM726taNEk1OB5Ab/SaFWDSIRQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EEE291A32; Tue, 17 Mar 2026 11:17:06 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E684B3F7BD; Tue, 17 Mar 2026 11:17:11 -0700 (PDT) From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@linaro.org, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, Yeoreum Yun Subject: [PATCH 2/2] coresight: etm3x: fix inconsistencies with sysfs configration Date: Tue, 17 Mar 2026 18:17:05 +0000 Message-Id: <20260317181705.2456271-3-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317181705.2456271-1-yeoreum.yun@arm.com> References: <20260317181705.2456271-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current ETM3x configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. To resolve these inconsistencies, the configuration should be separated int= o: - active_config, which represents the currently applied configuration - config, which stores the settings configured via sysfs. Signed-off-by: Yeoreum Yun --- drivers/hwtracing/coresight/coresight-etm.h | 2 ++ drivers/hwtracing/coresight/coresight-etm3x-core.c | 11 +++++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracin= g/coresight/coresight-etm.h index 1d753cca2943..d94adb08a235 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -226,6 +226,7 @@ struct etm_config { * @etmccr: value of register ETMCCR. * @etmccer: value of register ETMCCER. * @traceid: value of the current ID for this component. + * @active_config: structure holding current running configuration paramet= ers. * @config: structure holding configuration parameters. */ struct etm_drvdata { @@ -248,6 +249,7 @@ struct etm_drvdata { u32 etmccr; u32 etmccer; u32 traceid; + struct etm_config active_config; struct etm_config config; }; =20 diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index a547a6d2e0bd..30390ec38762 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -308,7 +308,7 @@ void etm_config_trace_mode(struct etm_config *config) static int etm_parse_event_config(struct etm_drvdata *drvdata, struct perf_event *event) { - struct etm_config *config =3D &drvdata->config; + struct etm_config *config =3D &drvdata->active_config; struct perf_event_attr *attr =3D &event->attr; u8 ts_level; =20 @@ -367,7 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) { int i, rc; u32 etmcr; - struct etm_config *config =3D &drvdata->config; + struct etm_config *config =3D &drvdata->active_config; struct coresight_device *csdev =3D drvdata->csdev; =20 CS_UNLOCK(drvdata->csa.base); @@ -513,6 +513,8 @@ static int etm_enable_sysfs(struct coresight_device *cs= dev, struct coresight_pat =20 spin_lock(&drvdata->spinlock); =20 + drvdata->active_config =3D drvdata->config; + drvdata->traceid =3D path->trace_id; =20 /* @@ -563,7 +565,7 @@ static int etm_enable(struct coresight_device *csdev, s= truct perf_event *event, static void etm_disable_hw(struct etm_drvdata *drvdata) { int i; - struct etm_config *config =3D &drvdata->config; + struct etm_config *config =3D &drvdata->active_config; struct coresight_device *csdev =3D drvdata->csdev; =20 CS_UNLOCK(drvdata->csa.base); @@ -877,7 +879,8 @@ static int etm_probe(struct amba_device *adev, const st= ruct amba_id *id) if (etm_arch_supported(drvdata->arch) =3D=3D false) return -EINVAL; =20 - etm_set_default(&drvdata->config); + etm_set_default(&drvdata->active_config); + drvdata->config =3D drvdata->active_config; =20 pdata =3D coresight_get_platform_data(dev); if (IS_ERR(pdata)) --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}