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Tue, 17 Mar 2026 10:18:46 -0700 (PDT) Received: from localhost ([2a02:a03f:b7dc:2b00:a97a:8551:7733:cb60]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f13edad8sm23641566b.6.2026.03.17.10.18.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2026 10:18:46 -0700 (PDT) Sender: Olivier Sobrie From: Olivier Sobrie To: Miquel Raynal Cc: Michal Simek , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Andrea Scian , stable@vger.kernel.org Subject: [PATCH v2] mtd: rawnand: pl353: make sure optimal timings are applied Date: Tue, 17 Mar 2026 18:18:07 +0100 Message-ID: <20260317171807.652642-1-olivier@sobrie.be> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Timings of the nand are adjusted by pl35x_nfc_setup_interface() but actually applied by the pl35x_nand_select_target() function. If there is only one nand chip, the pl35x_nand_select_target() will only apply the timings once since the test at its beginning will always be true after the first call to this function. As a result, the hardware will keep using the default timings set at boot to detect the nand chip, not the optimal ones. With this patch, we program directly the new timings when pl35x_nfc_setup_interface() is called. Fixes: 08d8c62164a3 ("mtd: rawnand: pl353: Add support for the ARM PL353 SM= C NAND controller") Signed-off-by: Olivier Sobrie Cc: stable@vger.kernel.org --- Changes in v2: - added Fixes tag. - added stable in Cc. drivers/mtd/nand/raw/pl35x-nand-controller.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/raw/pl35x-nand-controller.c b/drivers/mtd/nan= d/raw/pl35x-nand-controller.c index 947fd86ac5fa..f2c65eb7a8d9 100644 --- a/drivers/mtd/nand/raw/pl35x-nand-controller.c +++ b/drivers/mtd/nand/raw/pl35x-nand-controller.c @@ -862,6 +862,9 @@ static int pl35x_nfc_setup_interface(struct nand_chip *= chip, int cs, PL35X_SMC_NAND_TAR_CYCLES(tmgs.t_ar) | PL35X_SMC_NAND_TRR_CYCLES(tmgs.t_rr); =20 + writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES); + pl35x_smc_update_regs(nfc); + return 0; } =20 --=20 2.53.0