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Tue, 17 Mar 2026 05:36:14 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Chris Brandt , Hugo Villeneuve , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 1/2] drm: renesas: rzg2l_mipi_dsi: Use fsleep() for 1ms delay in D-PHY init Date: Tue, 17 Mar 2026 12:36:00 +0000 Message-ID: <20260317123610.329630-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260317123610.329630-1-biju.das.jz@bp.renesas.com> References: <20260317123610.329630-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Replace udelay(1) with fsleep(1000) in rzg2l_mipi_dsi_dphy_init() to follow the power-on sequence described in Figure 34.5 of section "34.4.2.1 Reset" of the RZ/G2L hardware manual Rev.1.50 May 2025. Signed-off-by: Biju Das --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index a87a301326c7..e53b48e4de56 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -528,7 +528,7 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_d= si *dsi, if (ret < 0) return ret; =20 - udelay(1); + fsleep(1000); =20 return 0; } --=20 2.43.0 From nobody Mon Apr 6 23:23:27 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56E803C3434 for ; Tue, 17 Mar 2026 12:36:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; 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Tue, 17 Mar 2026 05:36:16 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:e16b:fc56:e220:9aa9]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b4f845841sm3247444f8f.11.2026.03.17.05.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2026 05:36:16 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Philipp Zabel Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Chris Brandt , Hugo Villeneuve , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 2/2] drm: renesas: rzg2l_mipi_dsi: Fix the power-on sequence Date: Tue, 17 Mar 2026 12:36:01 +0000 Message-ID: <20260317123610.329630-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260317123610.329630-1-biju.das.jz@bp.renesas.com> References: <20260317123610.329630-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Move reset_control_deassert() and reset_control_assert() from rzg2l_mipi_dsi_dphy_init()/rzg2l_mipi_dsi_dphy_exit() to atomic_pre_enable() and atomic_post_disable() respectively, and move rzg2l_mipi_dsi_set_display_timing() from atomic_pre_enable() to atomic_enable(), to align with the power-on sequence described in Figure 34.5 of section "34.4.2.1 Reset" of the RZ/G2L hardware manual Rev.1.50 May 2025. According to the hardware manual, LINK registers must be written before deasserting CMN_RSTB, and the 1ms delay is retained in atomic_pre_enable() after the deassert. Signed-off-by: Biju Das --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 27 +++++++++++-------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index e53b48e4de56..9053ce037b75 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -484,7 +484,6 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_d= si *dsi, u32 dphytim1; u32 dphytim2; u32 dphytim3; - int ret; =20 /* All DSI global operation timings are set with recommended setting */ for (i =3D 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) { @@ -524,12 +523,6 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_= dsi *dsi, rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM2, dphytim2); rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM3, dphytim3); =20 - ret =3D reset_control_deassert(dsi->rstc); - if (ret < 0) - return ret; - - fsleep(1000); - return 0; } =20 @@ -541,8 +534,6 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_= dsi *dsi) =20 dphyctrl0 &=3D ~(DSIDPHYCTRL0_EN_LDO1200 | DSIDPHYCTRL0_EN_BGR); rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0); - - reset_control_assert(dsi->rstc); } =20 static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long = mode_freq, @@ -1030,24 +1021,37 @@ static void rzg2l_mipi_dsi_atomic_pre_enable(struct= drm_bridge *bridge, connector =3D drm_atomic_get_new_connector_for_encoder(state, bridge->enc= oder); crtc =3D drm_atomic_get_new_connector_state(state, connector)->crtc; mode =3D &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode; - ret =3D rzg2l_mipi_dsi_startup(dsi, mode); if (ret < 0) return; =20 - rzg2l_mipi_dsi_set_display_timing(dsi, mode); + ret =3D reset_control_deassert(dsi->rstc); + if (ret < 0) + return; + + if (dsi->rstc) + fsleep(1000); } =20 static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge, struct drm_atomic_state *state) { struct rzg2l_mipi_dsi *dsi =3D bridge_to_rzg2l_mipi_dsi(bridge); + const struct drm_display_mode *mode; + struct drm_connector *connector; + struct drm_crtc *crtc; int ret; =20 ret =3D rzg2l_mipi_dsi_start_hs_clock(dsi); if (ret < 0) goto err_stop; =20 + connector =3D drm_atomic_get_new_connector_for_encoder(state, bridge->enc= oder); + crtc =3D drm_atomic_get_new_connector_state(state, connector)->crtc; + mode =3D &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode; + + rzg2l_mipi_dsi_set_display_timing(dsi, mode); + ret =3D rzg2l_mipi_dsi_start_video(dsi); if (ret < 0) goto err_stop_clock; @@ -1074,6 +1078,7 @@ static void rzg2l_mipi_dsi_atomic_post_disable(struct= drm_bridge *bridge, { struct rzg2l_mipi_dsi *dsi =3D bridge_to_rzg2l_mipi_dsi(bridge); =20 + reset_control_assert(dsi->rstc); rzg2l_mipi_dsi_stop(dsi); } =20 --=20 2.43.0