From nobody Thu Apr 2 09:40:43 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E58AC3A5E87 for ; Tue, 17 Mar 2026 10:16:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773742602; cv=none; b=P4rmZTg/zbNg98bj26Msuv8Hg43zNtYYD4ET5K8zjpeMMsLXI4XJN2Idzul0QjRMCnLP2S8HiFqDfsJwwpOtXavApnooTUkwG6mbzcyVCKX5nkGboKqzLd4c2YVSAYDnX7O0BKpPVwz/fO1/LoLDYw+4wNo0Hr2CSSJD2eaRS9k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773742602; c=relaxed/simple; bh=MToUqiQLSOCiKLLmLKpsTiluVNFD5qK7fzHRpHV2EL4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jWhHFNMYZgh9yjo/YagT5M9MWdp1727SAGbFo2cx/2xhQJfo4xy3ZHMjP+PHUIqIt7VnQPljvoxj8KJJp0lflguqm7PBpG8p+y/EBEJNsChL43sDFubDmHcTwWrz4bN+70srfjWtptavkmtoEG9I1XamYPTUhQ7Z5BMTv/bb74o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=fx8z1JAi; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fx8z1JAi" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-48540d21f7dso64155265e9.0 for ; Tue, 17 Mar 2026 03:16:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773742599; x=1774347399; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V35Cp1YeMeEi1oS2JHcbUtKh1eWOizu2qXICGsho11k=; b=fx8z1JAiTwzubCllYwb3LiKyHEDhvUg7Wy9CBEL0BToTwvwtyJC1+yNbwDlnj1xjBe CM0GK1CDBJbMleh3mytw5gAuULdJWA1kGKJh+NhvfzV7pOlfMXCcGrbZatP5v4F7XohK wUUuGcYZuIqHPsWl4GzbLtHG8e+S9x72sj3neku3gEbagHv4VaNFYUH/wwtjvtZaR2gw JiOR5WhBClUgfIAMs41kTLqwddmYt3LKJUIg1JcG/2AOQF8DDQRDEHYe3vSf1OdnjydE bfp2dmfgq1cmdpZk0ySbcqnTQxkZzV/6aj7Z/iGPl8PJho1BJD741BjHfJ+QE+pzA6cY 7UZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773742599; x=1774347399; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=V35Cp1YeMeEi1oS2JHcbUtKh1eWOizu2qXICGsho11k=; b=NPtRcNnzcWr9IOcwbCUETjUXb4xrJDW1rzXYERFuMAkBo3nSyTRfZTEOiJX++/o4gA BkeDzpVNXsI+Q5Epgo1fe7jJnhbpHOFr95XUTM9/XkkjJorhODwTSwWjQ/thzjRsaOl9 7VtaKYqQTAbJofNbeBpfmxuaP+zrFSLL8phNlCHm0CdGhPjTK9C1bnZD6t/XroHL1XIt KOL5utD8b6bo8YJQ6Suz5nug9WT/uHCCWxQCBGBKu6U3MHLcDI7v8d+BzW+D5VuZI8X7 6xrlQJA8Cadeh1bRp2iq8LI/M8s/V8wXndEyN6ZXKqCgBKpCAdRbTs285t71sEg68aWC MT7g== X-Forwarded-Encrypted: i=1; AJvYcCXJA/eObu9CdS1XkhgKz88K/56MepugAeEmMX2G5kKsEqPxNjNo2cKOrnmDe41T8XunJtNh+pwXHpYso4c=@vger.kernel.org X-Gm-Message-State: AOJu0YwBEQ96zkDcrMsWkQJhfDQp31Qujebz+DOGDQvwJR4F2GPQKrG9 H55BGwP8jrxuIsneXYn8PC5AsHcAc+Cm1iVHr9R6SMOEqi8KGjbLam4892LYxg== X-Gm-Gg: ATEYQzyKB6Shi+pssbP2Pq//VBU0R4VJhVqsGoXd5P6uRktBVnFowfR0Actfr/KsjcA JF/kHiGexmTCj2lmKPbOtj1YL6OpldnwNCPGNZ2XRM7HQGc6Pdn01BkmiRpbCs0DBF5p2/HWTBE gVSEpAzH4xOEOYTaIW3Pw0mwLI71Xp2xHg8AXjVFRkjkrlV7Sfcm5B6FGwPsdqM7LLVQsqXVkt5 IWkJABy6HmFhnCzmm06UL7s3mZdjtg3aauMlWEe6wbiP6c+YrT9YsqCvj5pXIBuO+LJsI5XgkTK xQa8VQzJEj399PbEa8m2N23QIK2NRkF21x6m8iU/DM+T2ByHt36GHUmiSJo5/oDCvK4T/4MVNF0 dO3okOEiurYej3tI4cMkiAKLKlP3+CUadS3YPZMgscyzZwczeDlfJbwPekiZOsN4fV9fYtp0iGf 07o6o9a24VOOtI6P/dOHfJQj3vYTKWKGb/Z6xreTs/cgAoHPM3 X-Received: by 2002:a05:600c:8a09:10b0:483:badb:618e with SMTP id 5b1f17b1804b1-485566d6e33mr193059745e9.8.1773742598976; Tue, 17 Mar 2026 03:16:38 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:e16b:fc56:e220:9aa9]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4856eaee510sm53903275e9.14.2026.03.17.03.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2026 03:16:38 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij , Magnus Damm Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 8/8] pinctrl: renesas: rzg2l: Add support for clone channel control Date: Tue, 17 Mar 2026 10:16:21 +0000 Message-ID: <20260317101627.174491-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260317101627.174491-1-biju.das.jz@bp.renesas.com> References: <20260317101627.174491-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has some IP such as I2C ch{2,3},SCIF ch{3,4,5}, RSPI ch{1,2} and RSCI ch{1,2,3} need to control the clone channel for proper operation. As per the RZ/G3L hardware manual, the clone channel setting is to be done before the mux setting. Signed-off-by: Biju Das --- v3: * New patch. --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 218 ++++++++++++++++++++++++ 1 file changed, 218 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 3cef8a8d3712..b8ce110f95d8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -11,12 +11,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include =20 @@ -152,6 +154,26 @@ FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \ FIELD_PREP_CONST(PIN_CFG_MASK, (cfg))) =20 +#define RZG3L_CLONE_CHANNEL_CFG_PIN_START_MASK GENMASK(31, 29) +#define RZG3L_CLONE_CHANNEL_CFG_PIN_END_MASK GENMASK(28, 26) +#define RZG3L_CLONE_CHANNEL_CFG_PORT_MASK GENMASK(25, 21) +#define RZG3L_CLONE_CHANNEL_CFG_DATA_MASK GENMASK(9, 0) +#define RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(port, start_pin, end_pin, cfg) \ + (FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_CFG_PIN_START_MASK, (start_pin)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_CFG_PIN_END_MASK, (end_pin)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_CFG_PORT_MASK, (port)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_CFG_DATA_MASK, (cfg))) + +#define RZG3L_CLONE_CHANNEL_BIT_MASK GENMASK(9, 6) +#define RZG3L_CLONE_CHANNEL_VAL_MASK BIT(5) +#define RZG3L_CLONE_CHANNEL_SHARED_PIN_MASK BIT(4) +#define RZG3L_CLONE_CHANNEL_PFC_MASK GENMASK(3, 0) +#define RZG3L_CLONE_CHANNEL_PACK(bit, val, shared_pin, pfc) \ + (FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_BIT_MASK, (bit)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_VAL_MASK, (val)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_SHARED_PIN_MASK, (shared_pin)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PFC_MASK, (pfc))) + #define P(off) (0x0000 + (off)) #define PM(off) (0x0100 + (off) * 2) #define PMC(off) (0x0200 + (off)) @@ -311,6 +333,8 @@ struct rzg2l_pinctrl_data { const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; + const u32 *clone_pin_configs; + unsigned int n_clone_pins; const struct rzg2l_hwcfg *hwcfg; const u64 *variable_pin_cfg; unsigned int n_variable_pin_cfg; @@ -346,6 +370,7 @@ struct rzg2l_pinctrl_pin_settings { * @pupd: PUPD registers cache * @ien: IEN registers cache * @smt: SMT registers cache + * @clone: Clone registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache * @other_poc: OTHER_POC register cache @@ -361,6 +386,7 @@ struct rzg2l_pinctrl_reg_cache { u32 *ien[2]; u32 *pupd[2]; u32 *smt; + u32 *clone; u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; @@ -379,6 +405,8 @@ struct rzg2l_pinctrl { =20 struct clk *clk; =20 + struct regmap *syscon; + struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); @@ -392,6 +420,7 @@ struct rzg2l_pinctrl { struct rzg2l_pinctrl_reg_cache *cache; struct rzg2l_pinctrl_reg_cache *dedicated_cache; atomic_t wakeup_path; + u32 clone_offset; }; =20 static const u16 available_ps[] =3D { 1800, 2500, 3300 }; @@ -617,6 +646,54 @@ static int rzg2l_validate_pin(struct rzg2l_pinctrl *pc= trl, return 0; } =20 +static int rzg2l_pinctrl_set_clone_mode(struct rzg2l_pinctrl *pctrl, + u8 port, u8 pin, u8 func) +{ + static const u8 pfc_table_lut[] =3D { 2, 4, 5, 6, 7 }; + u8 start_pin, end_pin; + unsigned int i; + + if (!pctrl->data->clone_pin_configs) + return 0; + + for (i =3D 0; i < ARRAY_SIZE(pfc_table_lut); i++) + if (pfc_table_lut[i] =3D=3D func) + break; + + if (i =3D=3D ARRAY_SIZE(pfc_table_lut)) + return 0; + + for (i =3D 0; i < pctrl->data->n_clone_pins; i++) { + u32 pin_data =3D pctrl->data->clone_pin_configs[i]; + bool is_shared_pin =3D FIELD_GET(RZG3L_CLONE_CHANNEL_SHARED_PIN_MASK, pi= n_data); + u8 pin_func =3D FIELD_GET(RZG3L_CLONE_CHANNEL_PFC_MASK, pin_data); + unsigned int j, num_pins; + + if ((pin_func !=3D func && !(is_shared_pin && (pin_func + 1) =3D=3D func= )) || + FIELD_GET(RZG3L_CLONE_CHANNEL_CFG_PORT_MASK, pin_data) !=3D port) + continue; + + start_pin =3D FIELD_GET(RZG3L_CLONE_CHANNEL_CFG_PIN_START_MASK, pin_data= ); + end_pin =3D FIELD_GET(RZG3L_CLONE_CHANNEL_CFG_PIN_END_MASK, pin_data); + num_pins =3D end_pin - start_pin + 1; + + for (j =3D 0; j < num_pins; j++) { + u32 bit, val; + + if ((start_pin + j) !=3D pin) + continue; + + bit =3D FIELD_GET(RZG3L_CLONE_CHANNEL_BIT_MASK, pin_data); + val =3D FIELD_GET(RZG3L_CLONE_CHANNEL_VAL_MASK, pin_data); + + return regmap_update_bits(pctrl->syscon, pctrl->clone_offset, + BIT(bit), field_prep(BIT(bit), val)); + } + } + + return 0; +} + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -692,6 +769,10 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *p= ctldev, func =3D psel_val[i] - hwcfg->func_base; dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", port, pin, off, = func); =20 + ret =3D rzg2l_pinctrl_set_clone_mode(pctrl, port, pin, func); + if (ret) + return ret; + rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, func); } =20 @@ -2647,6 +2728,110 @@ static const struct rzg2l_dedicated_configs rzg3l_d= edicated_pins[] =3D { (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, }; =20 +static const u32 r9a08g046_clone_channel_pin_cfg[] =3D { + /* I2C ch2 Bit:0 Value:0 PFC:4 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PG, 6, 7, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PH, 2, 3, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PK, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PA, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PA, 4, 5, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PB, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PB, 4, 5, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PC, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PD, 2, 3, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PD, 6, 7, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PE, 2, 3, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PE, 6, 7, RZG3L_CLONE_CHANNEL_PACK= (0, 0, 0, 4)), + /* I2C ch2 Bit:0 Value:1 PFC:4 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P5, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (0, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P5, 4, 5, RZG3L_CLONE_CHANNEL_PACK= (0, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 1, 2, RZG3L_CLONE_CHANNEL_PACK= (0, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 5, 6, RZG3L_CLONE_CHANNEL_PACK= (0, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P8, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (0, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P8, 4, 5, RZG3L_CLONE_CHANNEL_PACK= (0, 1, 0, 4)), + /* I2C ch3 Bit:1 Value:0 PFC:4 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PF, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (1, 0, 0, 4)), + /* I2C ch3 Bit:1 Value:1 PFC:4 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P2, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (1, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P5, 2, 3, RZG3L_CLONE_CHANNEL_PACK= (1, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P5, 6, 6, RZG3L_CLONE_CHANNEL_PACK= (1, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 0, 0, RZG3L_CLONE_CHANNEL_PACK= (1, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 3, 4, RZG3L_CLONE_CHANNEL_PACK= (1, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P7, 6, 7, RZG3L_CLONE_CHANNEL_PACK= (1, 1, 0, 4)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P8, 2, 3, RZG3L_CLONE_CHANNEL_PACK= (1, 1, 0, 4)), + /* SCIF ch3 Bit:4 Value:0 PFC:{6,7} */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PG, 4, 6, RZG3L_CLONE_CHANNEL_PACK= (4, 0, 0, 6)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PH, 3, 5, RZG3L_CLONE_CHANNEL_PACK= (4, 0, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PA, 2, 4, RZG3L_CLONE_CHANNEL_PACK= (4, 0, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PB, 3, 5, RZG3L_CLONE_CHANNEL_PACK= (4, 0, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PD, 0, 2, RZG3L_CLONE_CHANNEL_PACK= (4, 0, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PE, 1, 3, RZG3L_CLONE_CHANNEL_PACK= (4, 0, 0, 7)), + /* SCIF ch3 Bit:4 Value:1 PFC:7 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P5, 0, 2, RZG3L_CLONE_CHANNEL_PACK= (4, 1, 0, 7)), + /* SCIF ch4 Bit:5 Value:0 PFC:7 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PK, 0, 2, RZG3L_CLONE_CHANNEL_PACK= (5, 0, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PA, 5, 7, RZG3L_CLONE_CHANNEL_PACK= (5, 0, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PB, 6, 7, RZG3L_CLONE_CHANNEL_PACK= (5, 0, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PC, 0, 0, RZG3L_CLONE_CHANNEL_PACK= (5, 0, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PD, 3, 5, RZG3L_CLONE_CHANNEL_PACK= (5, 0, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PE, 4, 6, RZG3L_CLONE_CHANNEL_PACK= (5, 0, 0, 7)), + /* SCIF ch4 Bit:5 Value:1 PFC:7 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P5, 3, 5, RZG3L_CLONE_CHANNEL_PACK= (5, 1, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 2, 4, RZG3L_CLONE_CHANNEL_PACK= (5, 1, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P7, 5, 7, RZG3L_CLONE_CHANNEL_PACK= (5, 1, 0, 7)), + /* SCIF ch5 Bit:6 Value:0 PFC:7 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PE, 7, 7, RZG3L_CLONE_CHANNEL_PACK= (6, 0, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PF, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (6, 0, 0, 7)), + /* SCIF ch5 Bit:6 Value:1 PFC:7 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P5, 6, 6, RZG3L_CLONE_CHANNEL_PACK= (6, 1, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (6, 1, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 5, 6, RZG3L_CLONE_CHANNEL_PACK= (6, 1, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P7, 0, 0, RZG3L_CLONE_CHANNEL_PACK= (6, 1, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P7, 2, 4, RZG3L_CLONE_CHANNEL_PACK= (6, 1, 0, 7)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P8, 0, 2, RZG3L_CLONE_CHANNEL_PACK= (6, 1, 0, 7)), + /* RSPI ch1 Bit:8 Value:0 PFC:2 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PH, 0, 5, RZG3L_CLONE_CHANNEL_PACK= (8, 0, 0, 2)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PD, 5, 7, RZG3L_CLONE_CHANNEL_PACK= (8, 0, 0, 2)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PE, 0, 3, RZG3L_CLONE_CHANNEL_PACK= (8, 0, 0, 2)), + /* RSPI ch1 Bit:8 Value:1 PFC:2 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P5, 0, 6, RZG3L_CLONE_CHANNEL_PACK= (8, 1, 0, 2)), + /* RSPI ch2 Bit:9 Value:0 PFC:2 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PE, 4, 7, RZG3L_CLONE_CHANNEL_PACK= (9, 0, 0, 2)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PF, 0, 2, RZG3L_CLONE_CHANNEL_PACK= (9, 0, 0, 2)), + /* RSPI ch2 Bit:9 Value:1 PFC:2 */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 0, 6, RZG3L_CLONE_CHANNEL_PACK= (9, 1, 0, 2)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P7, 7, 7, RZG3L_CLONE_CHANNEL_PACK= (9, 1, 0, 2)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P8, 0, 5, RZG3L_CLONE_CHANNEL_PACK= (9, 1, 0, 2)), + /* RSCI ch1 Bit:12 Value:0 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PG, 0, 3, RZG3L_CLONE_CHANNEL_PACK= (12, 0, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PA, 0, 3, RZG3L_CLONE_CHANNEL_PACK= (12, 0, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PB, 6, 7, RZG3L_CLONE_CHANNEL_PACK= (12, 0, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PC, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (12, 0, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PD, 4, 7, RZG3L_CLONE_CHANNEL_PACK= (12, 0, 1, 5)), + /* RSCI ch1 Bit:12 Value:1 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P5, 0, 3, RZG3L_CLONE_CHANNEL_PACK= (12, 1, 1, 5)), + /* RSCI ch2 Bit:13 Value:0 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PH, 0, 3, RZG3L_CLONE_CHANNEL_PACK= (13, 0, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PK, 0, 3, RZG3L_CLONE_CHANNEL_PACK= (13, 0, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PA, 4, 7, RZG3L_CLONE_CHANNEL_PACK= (13, 0, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PD, 0, 3, RZG3L_CLONE_CHANNEL_PACK= (13, 0, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PE, 0, 3, RZG3L_CLONE_CHANNEL_PACK= (13, 0, 1, 5)), + /* RSCI ch2 Bit:13 Value:1 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P5, 4, 6, RZG3L_CLONE_CHANNEL_PACK= (13, 1, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 0, 0, RZG3L_CLONE_CHANNEL_PACK= (13, 1, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 5, 6, RZG3L_CLONE_CHANNEL_PACK= (13, 1, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P7, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (13, 1, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P7, 6, 7, RZG3L_CLONE_CHANNEL_PACK= (13, 1, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P8, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (13, 1, 1, 5)), + /* RSCI ch3 Bit:14 Value:0 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PE, 6, 7, RZG3L_CLONE_CHANNEL_PACK= (14, 0, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_PF, 0, 1, RZG3L_CLONE_CHANNEL_PACK= (14, 0, 1, 5)), + /* RSCI ch3 Bit:14 Value:1 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P6, 1, 4, RZG3L_CLONE_CHANNEL_PACK= (14, 1, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P7, 2, 5, RZG3L_CLONE_CHANNEL_PACK= (14, 1, 1, 5)), + RZG3L_CLONE_CHANNEL_PIN_CFG_PACK(RZG3L_P8, 2, 5, RZG3L_CLONE_CHANNEL_PACK= (14, 1, 1, 5)), +}; + static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl = *pctrl) { const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[virq]; @@ -2961,6 +3146,10 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2= l_pinctrl *pctrl) if (!cache->smt) return -ENOMEM; =20 + cache->clone =3D devm_kzalloc(pctrl->dev, sizeof(*cache->clone), GFP_KERN= EL); + if (!cache->clone) + return -ENOMEM; + for (u8 i =3D 0; i < 2; i++) { u32 n_dedicated_pins =3D pctrl->data->n_dedicated_pins; =20 @@ -3204,6 +3393,19 @@ static int rzg2l_pinctrl_probe(struct platform_devic= e *pdev) "failed to enable GPIO clk\n"); } =20 + if (pctrl->data->clone_pin_configs) { + struct device_node *np =3D pctrl->dev->of_node; + u32 offset; + + pctrl->syscon =3D syscon_regmap_lookup_by_phandle_args(np, "renesas,clon= ech", + 1, &offset); + if (IS_ERR(pctrl->syscon)) + return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->syscon), + "Failed to parse renesas,clonech\n"); + + pctrl->clone_offset =3D offset; + } + raw_spin_lock_init(&pctrl->lock); spin_lock_init(&pctrl->bitmap_lock); mutex_init(&pctrl->mutex); @@ -3437,6 +3639,14 @@ static int rzg2l_pinctrl_suspend_noirq(struct device= *dev) if (regs->other_poc) cache->other_poc =3D readb(pctrl->base + regs->other_poc); =20 + if (pctrl->syscon) { + int ret; + + ret =3D regmap_read(pctrl->syscon, pctrl->clone_offset, cache->clone); + if (ret) + return ret; + } + if (!atomic_read(&pctrl->wakeup_path)) clk_disable_unprepare(pctrl->clk); else @@ -3454,6 +3664,12 @@ static int rzg2l_pinctrl_resume_noirq(struct device = *dev) unsigned long flags; int ret; =20 + if (pctrl->syscon) { + ret =3D regmap_write(pctrl->syscon, pctrl->clone_offset, *cache->clone); + if (ret) + return ret; + } + if (!atomic_read(&pctrl->wakeup_path)) { ret =3D clk_prepare_enable(pctrl->clk); if (ret) @@ -3667,6 +3883,8 @@ static struct rzg2l_pinctrl_data r9a08g046_data =3D { .dedicated_pins =3D rzg3l_dedicated_pins, .n_port_pins =3D ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins =3D ARRAY_SIZE(rzg3l_dedicated_pins), + .clone_pin_configs =3D r9a08g046_clone_channel_pin_cfg, + .n_clone_pins =3D ARRAY_SIZE(r9a08g046_clone_channel_pin_cfg), .hwcfg =3D &rzg3l_hwcfg, .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, --=20 2.43.0