From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout06.his.huawei.com (canpmsgout06.his.huawei.com [113.46.200.221]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BECF37FF5B; Tue, 17 Mar 2026 08:20:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.221 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735609; cv=none; b=jp7pnEB2TX40UCdzFOCyO3FhhyuGO/t+HwZbW3aQetqKVI0yXZR2yFcAWu8GlwJWNMAMQPwlytcEyj8cfoXSvysjqsvhSgqAjHDcqmwRcGhygK2m0V8a2D2yq5xX+Ez8rV1eK9wrJcmYDpIc5nws6MZoVB9azAciamd6cBc/HWE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735609; c=relaxed/simple; bh=serGm1rUs+m82eoFVjhBlpo3u6+JxH3Uai4mDd1TxTo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fKrhoerZDWEX2/vEuTJgt8bQil1OEgzwoA9/4aEzrYRFm2t+q+tKZ7YnoLY1CBJXPW5WihlypwnPXoRw71aQtn4M3ySEAK3/W9szKQ/WiUInIs5RIFpFyuUbVhU+75mA7DBLjism8xJ/NowRdhVYoOn67xoRNhpzYD+D/Qm32a4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=I9kIsBq0; arc=none smtp.client-ip=113.46.200.221 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="I9kIsBq0" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=GLJ5XubJBfDJfUuOM58o11k78XnXZ7Y2DNp2dl1D/fs=; b=I9kIsBq0rEldvH1pV/t2PPj5ksmYCRu9Ea0cHuZ6xohcPJTXps0Xy1ioEe9+cguZFqBqCcZug /PUbYSXX6nPI5l0nOX2zkFQQp1bUPwyT0L88FmN9VqtA48YtrpX8FQ/aYX9VabX89Mq77ZNH/a8 m7m3LydRbGb6fEV+Uy/WVgg= Received: from mail.maildlp.com (unknown [172.19.162.144]) by canpmsgout06.his.huawei.com (SkyGuard) with ESMTPS id 4fZlBK5cMrzRhR0; Tue, 17 Mar 2026 16:15:05 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id DC93F40567; Tue, 17 Mar 2026 16:20:03 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 17 Mar 2026 16:20:01 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 01/14] arm64/ptrace: Refactor syscall_trace_enter/exit() to accept flags parameter Date: Tue, 17 Mar 2026 16:20:07 +0800 Message-ID: <20260317082020.737779-2-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Refactor syscall_trace_enter() and syscall_trace_exit() to move thread flag reading to the caller. This aligns arm64's syscall trace enter/exit function signature with generic entry framework. [Changes] 1. Function signature changes: - syscall_trace_enter(regs) =E2=86=92 syscall_trace_enter(regs, flags) - syscall_trace_exit(regs) =E2=86=92 syscall_trace_exit(regs, flags) 2. Move flags reading to caller: - Previously: read_thread_flags() called inside each function. - Now: caller (like el0_svc_common) passes flags as parameter. 3. Update syscall.c: - el0_svc_common() now passes flags to tracing functions and re-fetches flags before exit to handle potential TIF updates. [Why this matters] - Aligns arm64 with the generic entry interface. - Makes future migration to generic entry framework. No functional changes intended. Cc: Will Deacon Cc: Catalin Marinas Reviewed-by: Kevin Brodsky Signed-off-by: Jinjie Ruan Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/include/asm/syscall.h | 4 ++-- arch/arm64/kernel/ptrace.c | 7 ++----- arch/arm64/kernel/syscall.c | 5 +++-- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/syscall.h b/arch/arm64/include/asm/sysc= all.h index 5e4c7fc44f73..30b203ef156b 100644 --- a/arch/arm64/include/asm/syscall.h +++ b/arch/arm64/include/asm/syscall.h @@ -120,7 +120,7 @@ static inline int syscall_get_arch(struct task_struct *= task) return AUDIT_ARCH_AARCH64; } =20 -int syscall_trace_enter(struct pt_regs *regs); -void syscall_trace_exit(struct pt_regs *regs); +int syscall_trace_enter(struct pt_regs *regs, unsigned long flags); +void syscall_trace_exit(struct pt_regs *regs, unsigned long flags); =20 #endif /* __ASM_SYSCALL_H */ diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index ba5eab23fd90..e4d524ccbc7b 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -2408,9 +2408,8 @@ static void report_syscall_exit(struct pt_regs *regs) } } =20 -int syscall_trace_enter(struct pt_regs *regs) +int syscall_trace_enter(struct pt_regs *regs, unsigned long flags) { - unsigned long flags =3D read_thread_flags(); int ret; =20 if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) { @@ -2432,10 +2431,8 @@ int syscall_trace_enter(struct pt_regs *regs) return regs->syscallno; } =20 -void syscall_trace_exit(struct pt_regs *regs) +void syscall_trace_exit(struct pt_regs *regs, unsigned long flags) { - unsigned long flags =3D read_thread_flags(); - audit_syscall_exit(regs); =20 if (flags & _TIF_SYSCALL_TRACEPOINT) diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c index c062badd1a56..e8fd0d60ab09 100644 --- a/arch/arm64/kernel/syscall.c +++ b/arch/arm64/kernel/syscall.c @@ -124,7 +124,7 @@ static void el0_svc_common(struct pt_regs *regs, int sc= no, int sc_nr, */ if (scno =3D=3D NO_SYSCALL) syscall_set_return_value(current, regs, -ENOSYS, 0); - scno =3D syscall_trace_enter(regs); + scno =3D syscall_trace_enter(regs, flags); if (scno =3D=3D NO_SYSCALL) goto trace_exit; } @@ -143,7 +143,8 @@ static void el0_svc_common(struct pt_regs *regs, int sc= no, int sc_nr, } =20 trace_exit: - syscall_trace_exit(regs); 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charset="utf-8" Use syscall_get_nr() to get syscall number for syscall_trace_enter(). This aligns arm64's internal tracing logic with the generic entry framework. [Changes] 1. Use syscall_get_nr() helper: - Replace direct regs->syscallno access with syscall_get_nr(current, regs). - This helper is functionally equivalent to direct access on arm64. 2. Re-read syscall number after tracepoint: - Re-fetch the syscall number after trace_sys_enter() as it may have been modified by BPF or ftrace probes, matching generic entry behavior. [Why this matters] - Aligns arm64 with the generic entry interface. - Makes future migration to generic entry framework. - Properly handles syscall number modifications by tracers. - Uses standard architecture-independent helpers. No functional changes intended. Cc: Will Deacon Cc: Catalin Marinas Reviewed-by: Kevin Brodsky Signed-off-by: Jinjie Ruan Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/kernel/ptrace.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index e4d524ccbc7b..8d296a07fbf7 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -2410,6 +2410,7 @@ static void report_syscall_exit(struct pt_regs *regs) =20 int syscall_trace_enter(struct pt_regs *regs, unsigned long flags) { + long syscall; int ret; =20 if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) { @@ -2422,13 +2423,23 @@ int syscall_trace_enter(struct pt_regs *regs, unsig= ned long flags) if (secure_computing() =3D=3D -1) return NO_SYSCALL; =20 - if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) - trace_sys_enter(regs, regs->syscallno); + /* Either of the above might have changed the syscall number */ + syscall =3D syscall_get_nr(current, regs); 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spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="zBji1bSp" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=egLlSVzHKLlWrE+C1u4R4GAY3SI2tDu6OysUmWNLQGo=; b=zBji1bSpBelhC7PD5LAuv3cDCWhKFnwrRZ0FgtFV8Z0eftCOx8GJPRFWH9ju9qbS/g1a7AaKF l/jSZlBK0Aq3Hu9/5UjscYjNJRmGrTSfmDEs0AewVRmzPp8Xu8ky3+WP7nfBAfSZ42EJD5hulna O8aoV/VLnU1f2lzQPy3fuCE= Received: from mail.maildlp.com (unknown [172.19.162.223]) by canpmsgout03.his.huawei.com (SkyGuard) with ESMTPS id 4fZl9y2XYxzpT04; Tue, 17 Mar 2026 16:14:46 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 35D1540561; Tue, 17 Mar 2026 16:20:08 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 17 Mar 2026 16:20:05 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 03/14] arm64/ptrace: Expand secure_computing() in place Date: Tue, 17 Mar 2026 16:20:09 +0800 Message-ID: <20260317082020.737779-4-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Refactor syscall_trace_enter() by open-coding the seccomp check to align with the generic entry framework. [Background] The generic entry implementation expands the seccomp check in-place instead of using the secure_computing() wrapper. It directly tests SYSCALL_WORK_SECCOMP and calls the underlying __secure_computing() function to handle syscall filtering. [Changes] 1. Open-code seccomp check: - Instead of calling the secure_computing() wrapper, explicitly check the 'flags' parameter for _TIF_SECCOMP. - Call __secure_computing() directly if the flag is set. 2. Refine return value handling: - Use 'return ret ? : syscall' to propagate the return value. - Ensures any unexpected non-zero return from __secure_computing() is properly propagated is properly propagated. - This matches the logic in the generic entry code. [Why this matters] - Aligns the arm64 syscall path with the generic entry implementation, simplifying future migration to the generic entry framework. - No functional changes are intended; seccomp behavior remains identical. Cc: Will Deacon Cc: Catalin Marinas Reviewed-by: Kevin Brodsky Signed-off-by: Jinjie Ruan Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/kernel/ptrace.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 8d296a07fbf7..d68f872339c7 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -2420,8 +2420,11 @@ int syscall_trace_enter(struct pt_regs *regs, unsign= ed long flags) } =20 /* Do the secure computing after ptrace; failures should be fast. */ - if (secure_computing() =3D=3D -1) - return NO_SYSCALL; + if (flags & _TIF_SECCOMP) { + ret =3D __secure_computing(); + if (ret =3D=3D -1) + return NO_SYSCALL; + } =20 /* Either of the above might have changed the syscall number */ syscall =3D syscall_get_nr(current, regs); @@ -2439,7 +2442,7 @@ int syscall_trace_enter(struct pt_regs *regs, unsigne= d long flags) audit_syscall_entry(syscall, regs->orig_x0, regs->regs[1], regs->regs[2], regs->regs[3]); =20 - return syscall; + return ret ? : syscall; } =20 void syscall_trace_exit(struct pt_regs *regs, unsigned long flags) --=20 2.34.1 From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout01.his.huawei.com (canpmsgout01.his.huawei.com [113.46.200.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD090399351; Tue, 17 Mar 2026 08:20:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.216 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735615; cv=none; b=oRri02CYhGxeJEr+Ma+sMwtFJoIs9pgTbSFq4847uh/GQRe3BYcVN34NTqOL/fnPTQPcvJakeaOLFo/xrIPQqwJe+Yc94bnwqUwu0a0XeCjGPMeDglGDjgdFvyvmvYe9cIYqOvWV39rj/FBCWnoiG6HoordWJ7Mqiw9Zp/HMMXU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735615; c=relaxed/simple; bh=lprEyZwSvvY7oYLKAef1Q7ik1sFF41UBb5hN8a26DKI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rXEJep9PGxBoQ66Ns/P5GnTCohXSaj18BpqVljXWY11tTnWYs04sNFPgwXi2okcpGQ4PNQ/I8bjkHo2wZ/NzEOSN1XSeYCcY7B4xqgK55V8Suy7Ck3ImlWcxdwXkO54MsI/VJdHATq1KEZvvqu/YXYOswn71Z5wu6xMxBsYt1W4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=NDABjQXu; arc=none smtp.client-ip=113.46.200.216 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="NDABjQXu" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=2C3xUm5DjLxc/SIMZ8u7vfUUWnpj82cAfyp1WR99tWc=; b=NDABjQXunNMnlF7oHYKZVrxDBaFs/eqPG52mvXUBJL4aiYZeV11EIZJCWQfKMTgeBBo5G4W0b WBDZuMjPF7dG1A/7Ey1xqEIN3teGKZQG98dhjPZhWUEKRyP98M74TY/54ktv3GNA/53iqP1fKul oghNToMR+H4P0Na21iJ6JYs= Received: from mail.maildlp.com (unknown [172.19.162.140]) by canpmsgout01.his.huawei.com (SkyGuard) with ESMTPS id 4fZlB24TT6z1T4GZ; Tue, 17 Mar 2026 16:14:50 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 6426720168; Tue, 17 Mar 2026 16:20:10 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 17 Mar 2026 16:20:08 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 04/14] arm64/ptrace: Use syscall_get_arguments() helper for audit Date: Tue, 17 Mar 2026 16:20:10 +0800 Message-ID: <20260317082020.737779-5-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Extract syscall_enter_audit() helper and use syscall_get_arguments() to get syscall arguments, matching the generic entry implementation. The new code: - Checks audit_context() first to avoid unnecessary memcpy when audit is not active. - Uses syscall_get_arguments() helper instead of directly accessing regs fields. - Is now exactly equivalent to generic entry's syscall_enter_audit(). No functional changes. Cc: Will Deacon Cc: Catalin Marinas Reviewed-by: Kevin Brodsky Signed-off-by: Jinjie Ruan Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/kernel/ptrace.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index d68f872339c7..3cb497b2bd22 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -2408,6 +2408,16 @@ static void report_syscall_exit(struct pt_regs *regs) } } =20 +static inline void syscall_enter_audit(struct pt_regs *regs, long syscall) +{ + if (unlikely(audit_context())) { + unsigned long args[6]; + + syscall_get_arguments(current, regs, args); + audit_syscall_entry(syscall, args[0], args[1], args[2], args[3]); + } +} + int syscall_trace_enter(struct pt_regs *regs, unsigned long flags) { long syscall; @@ -2439,8 +2449,7 @@ int syscall_trace_enter(struct pt_regs *regs, unsigne= d long flags) syscall =3D syscall_get_nr(current, regs); } =20 - audit_syscall_entry(syscall, regs->orig_x0, regs->regs[1], - regs->regs[2], regs->regs[3]); + syscall_enter_audit(regs, syscall); =20 return ret ? : syscall; } --=20 2.34.1 From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout02.his.huawei.com (canpmsgout02.his.huawei.com [113.46.200.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28AB539C64E; Tue, 17 Mar 2026 08:20:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.217 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735624; cv=none; b=WsnPc+QpwTluw9J5UGQtUG7m1m7AeBicIgSIFDV2woVtSZfZY3zdIsGTPAwc1HtGYKURMCuy2PhH/MDDc9xCHd5wAV0BEbFVCmfePTNPWhGWgxsDOgMFfy+LJI758GA37s/Za5UY+ESH+BcWJckPlrZ8gSrTkqce+0Xp0y1mpGU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735624; c=relaxed/simple; bh=uFVdStJqmRo7KB97x+mpX0spYL1NBEeBhooV7DPVnsA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NaDf1huJqMl+HLpFBsdYNyiUxxfHZH2ybnRynPnbhKc5tvAfyMKh/iJ7moDPbpPX270EFwRkeMZ48PYYtRX9ARxiV4pZymxBIAQm5EfvpJfTsMenwMnBjKss7CNpXPvxyf/idypuqw3mTFmW7Qh+nei2np1eC8D+yXHhS/mH4EU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=HjFxAALP; arc=none smtp.client-ip=113.46.200.217 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="HjFxAALP" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=sBX9yVD1XwVBO8/P5Xrrvv9cm0iqe1Ko3v6FFuPSOFQ=; b=HjFxAALPHxYUpjdG8BniAoY8E6KltAJYcQ6OfO9o1z6CuBN91Is6Oi3zT0k6mS8JZiJpohCqO Du8KKijUHzOPyNGzp/WiQ+OB5+rF4PAs3D5SXBorpf4u5RL/oMkYd41cmVj6P3dgYPzN1149sA8 0zwGhWkLslJz29IiPSja+Hs= Received: from mail.maildlp.com (unknown [172.19.162.140]) by canpmsgout02.his.huawei.com (SkyGuard) with ESMTPS id 4fZl9l38d5zcbN6; Tue, 17 Mar 2026 16:14:35 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 994022025E; Tue, 17 Mar 2026 16:20:12 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 17 Mar 2026 16:20:10 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 05/14] arm64: ptrace: Move rseq_syscall() before audit_syscall_exit() Date: Tue, 17 Mar 2026 16:20:11 +0800 Message-ID: <20260317082020.737779-6-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Move the rseq_syscall() check earlier in the syscall exit path to ensure it operates on the original instruction pointer (regs->pc) before any potential modification by a tracer. [Background] When CONFIG_DEBUG_RSEQ is enabled, rseq_syscall() verifies that a system call was not executed within an rseq critical section by examining regs->pc. If a violation is detected, it triggers a SIGSEGV. [Problem] Currently, arm64 invokes rseq_syscall() after report_syscall_exit(). However, during report_syscall_exit(), a ptrace tracer can modify the task's instruction pointer via PTRACE_SETREGS. This leads to an inconsistency where rseq may analyze a post-trace PC instead of the actual PC at the time of syscall exit. [Why this matters] The rseq check is intended to validate the execution context of the syscall itself. Analyzing a tracer-modified PC can lead to incorrect detection or missed violations. Moving the check earlier ensures rseq sees the authentic state of the task. [Alignment] This change aligns arm64 with: - Generic entry, which calls rseq_syscall() first. - arm32 implementation, which also performs the check before audit. [Impact] There is no functional change to signal delivery; SIGSEGV will still be processed in arm64_exit_to_user_mode() at the end of the exit path. Cc: Thomas Gleixner Cc: Will Deacon Cc: Catalin Marinas Reviewed-by: Kevin Brodsky Signed-off-by: Jinjie Ruan Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/kernel/ptrace.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 3cb497b2bd22..f3d3dec85828 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -2456,6 +2456,8 @@ int syscall_trace_enter(struct pt_regs *regs, unsigne= d long flags) =20 void syscall_trace_exit(struct pt_regs *regs, unsigned long flags) { + rseq_syscall(regs); + audit_syscall_exit(regs); =20 if (flags & _TIF_SYSCALL_TRACEPOINT) @@ -2463,8 +2465,6 @@ void syscall_trace_exit(struct pt_regs *regs, unsigne= d long flags) =20 if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) report_syscall_exit(regs); - - rseq_syscall(regs); } =20 /* --=20 2.34.1 From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout04.his.huawei.com (canpmsgout04.his.huawei.com [113.46.200.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2D0B39B49D; Tue, 17 Mar 2026 08:20:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.219 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735618; cv=none; b=aCI1fB0RoUBBJ09LhR5kBsFb3FYZVFCS2hkPbmghK5ANDWrwUrzdN6GyjfOJynbNTZearfufPPZ4dsFlSy/CI3iSf/Z8w/mmLIOp+cIGVBQF4vngWQPIyRrucuu7AoI48hlvmn6oe0hAt4pHYHMNdt31vUM8VEWgNzEbwpoQmrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735618; c=relaxed/simple; bh=Ffkcy0ldhQWh7808bc1mPoDFvFpl7hBdQwYbVsJp7Oo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g202V8Cd3w3cIVyVqN8q/qCIaLJ5SQXoNuPVeTUKTZBFWs1t9hj/ZRccG43p/LsVXAcRhgFD3mPdD+brth2R5ZILHA37hbhUC0/JoHd3eW2oylVKhHhDY5gbaF1wmKzfhF3wUA4yAfD8XkE8oBLAIeCZF0emiltKQJrnMEzOqWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=iGfebN3K; arc=none smtp.client-ip=113.46.200.219 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="iGfebN3K" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=aEtyFU5WBbpoWitgxxqzE5NpRmFr3ZRmwUCq9lwp1j8=; b=iGfebN3Kod53zJG61UzIm8n/YjKeBCBuLBFUlWznXkOH31RE8rMkPGLTyMLYuZInkFs8dTc0x r4xr7Wt0xLqi7AGtswm5CKxpoMa37AwPtUyVyYQ3alD2nFvv1cnLph1oLspzmpMBUQo25g+sM0J MYzzRF70yE8/RCXZgs02Kbg= Received: from mail.maildlp.com (unknown [172.19.163.104]) by canpmsgout04.his.huawei.com (SkyGuard) with ESMTPS id 4fZlBT4KDqz1prKL; Tue, 17 Mar 2026 16:15:13 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id BF1B14056D; Tue, 17 Mar 2026 16:20:14 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 17 Mar 2026 16:20:12 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 06/14] arm64: syscall: Introduce syscall_exit_to_user_mode_work() Date: Tue, 17 Mar 2026 16:20:12 +0800 Message-ID: <20260317082020.737779-7-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Refactor the system call exit path to align with the generic entry framework. This consolidates thread flag checking, rseq handling, and syscall tracing into a structure that mirrors the generic syscall_exit_to_user_mode_work() implementation. [Rationale] The generic entry code employs a hierarchical approach for syscall exit work: 1. syscall_exit_to_user_mode_work(): The entry point that handles rseq and checks if further exit work (tracing/audit) is required. 2. syscall_exit_work(): Performs the actual tracing, auditing, and ptrace reporting. [Changes] - Rename and Encapsulate: Rename syscall_trace_exit() to syscall_exit_work() and make it static, as it is now an internal helper for the exit path. - New Entry Point: Implement syscall_exit_to_user_mode_work() to replace the manual flag-reading logic in el0_svc_common(). This function now encapsulates the rseq_syscall() call and the conditional execution of syscall_exit_work(). - Simplify el0_svc_common(): Remove the complex conditional checks for tracing and CONFIG_DEBUG_RSEQ at the end of the syscall path, delegating this responsibility to the new helper. - Helper Migration: Move has_syscall_work() to asm/syscall.h to allow its reuse across ptrace.c and syscall.c. - Clean up RSEQ: Remove the explicit IS_ENABLED(CONFIG_DEBUG_RSEQ) check in the caller, as rseq_syscall() is already a no-op when the config is disabled. Cc: Will Deacon Cc: Catalin Marinas Reviewed-by: Kevin Brodsky Signed-off-by: Jinjie Ruan Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/include/asm/syscall.h | 7 ++++++- arch/arm64/kernel/ptrace.c | 14 +++++++++++--- arch/arm64/kernel/syscall.c | 20 +------------------- 3 files changed, 18 insertions(+), 23 deletions(-) diff --git a/arch/arm64/include/asm/syscall.h b/arch/arm64/include/asm/sysc= all.h index 30b203ef156b..c469d09a7964 100644 --- a/arch/arm64/include/asm/syscall.h +++ b/arch/arm64/include/asm/syscall.h @@ -120,7 +120,12 @@ static inline int syscall_get_arch(struct task_struct = *task) return AUDIT_ARCH_AARCH64; } =20 +static inline bool has_syscall_work(unsigned long flags) +{ + return unlikely(flags & _TIF_SYSCALL_WORK); +} + int syscall_trace_enter(struct pt_regs *regs, unsigned long flags); -void syscall_trace_exit(struct pt_regs *regs, unsigned long flags); +void syscall_exit_to_user_mode_work(struct pt_regs *regs); =20 #endif /* __ASM_SYSCALL_H */ diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index f3d3dec85828..35efa2062408 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -2454,10 +2454,8 @@ int syscall_trace_enter(struct pt_regs *regs, unsign= ed long flags) return ret ? : syscall; } =20 -void syscall_trace_exit(struct pt_regs *regs, unsigned long flags) +static void syscall_exit_work(struct pt_regs *regs, unsigned long flags) { - rseq_syscall(regs); - audit_syscall_exit(regs); =20 if (flags & _TIF_SYSCALL_TRACEPOINT) @@ -2467,6 +2465,16 @@ void syscall_trace_exit(struct pt_regs *regs, unsign= ed long flags) report_syscall_exit(regs); } =20 +void syscall_exit_to_user_mode_work(struct pt_regs *regs) +{ + unsigned long flags =3D read_thread_flags(); + + rseq_syscall(regs); + + if (has_syscall_work(flags) || flags & _TIF_SINGLESTEP) + syscall_exit_work(regs, flags); +} + /* * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a. * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which = is diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c index e8fd0d60ab09..66d4da641d97 100644 --- a/arch/arm64/kernel/syscall.c +++ b/arch/arm64/kernel/syscall.c @@ -65,11 +65,6 @@ static void invoke_syscall(struct pt_regs *regs, unsigne= d int scno, choose_random_kstack_offset(get_random_u16()); } =20 -static inline bool has_syscall_work(unsigned long flags) -{ - return unlikely(flags & _TIF_SYSCALL_WORK); -} - static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, const syscall_fn_t syscall_table[]) { @@ -130,21 +125,8 @@ static void el0_svc_common(struct pt_regs *regs, int s= cno, int sc_nr, } =20 invoke_syscall(regs, scno, sc_nr, syscall_table); - - /* - * The tracing status may have changed under our feet, so we have to - * check again. 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This aligns arm64 with the generic entry framework's SYSCALL_WORK_EXIT semantics. [Rationale] The current syscall exit path uses _TIF_SYSCALL_WORK to decide whether to invoke syscall_exit_work(). However, _TIF_SYSCALL_WORK includes flags that are only relevant during syscall entry: 1. _TIF_SECCOMP: Seccomp filtering (__secure_computing) only runs on entry. There is no seccomp callback for syscall exit. 2. _TIF_SYSCALL_EMU: In PTRACE_SYSEMU mode, the syscall is intercepted and skipped on entry. Since the syscall is never executed, reporting a syscall exit stop is unnecessary. [Changes] - Define _TIF_SYSCALL_EXIT_WORK: A new mask containing only flags requiring exit processing: _TIF_SYSCALL_TRACE, _TIF_SYSCALL_AUDIT, and _TIF_SYSCALL_TRACEPOINT. - Update exit path: Use _TIF_SYSCALL_EXIT_WORK in syscall_exit_to_user_mode_work() to avoid redundant calls to audit and ptrace reporting when only entry-flags are set. - Cleanup: Remove the has_syscall_work() helper as it is no longer needed. Direct flag comparison is now used to distinguish between entry and exit work requirements. [Impact] audit_syscall_exit() and report_syscall_exit() will no longer be triggered for seccomp-only or emu-only syscalls. This matches the generic entry behavior and improves efficiency by skipping unnecessary exit processing. Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Jinjie Ruan Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/include/asm/syscall.h | 5 ----- arch/arm64/include/asm/thread_info.h | 3 +++ arch/arm64/kernel/ptrace.c | 2 +- arch/arm64/kernel/syscall.c | 2 +- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/syscall.h b/arch/arm64/include/asm/sysc= all.h index c469d09a7964..dea392c081ca 100644 --- a/arch/arm64/include/asm/syscall.h +++ b/arch/arm64/include/asm/syscall.h @@ -120,11 +120,6 @@ static inline int syscall_get_arch(struct task_struct = *task) return AUDIT_ARCH_AARCH64; } =20 -static inline bool has_syscall_work(unsigned long flags) -{ - return unlikely(flags & _TIF_SYSCALL_WORK); -} - int syscall_trace_enter(struct pt_regs *regs, unsigned long flags); void syscall_exit_to_user_mode_work(struct pt_regs *regs); =20 diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/= thread_info.h index 7942478e4065..4ae83cb620bb 100644 --- a/arch/arm64/include/asm/thread_info.h +++ b/arch/arm64/include/asm/thread_info.h @@ -109,6 +109,9 @@ void arch_setup_new_exec(void); _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | \ _TIF_SYSCALL_EMU) =20 +#define _TIF_SYSCALL_EXIT_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \ + _TIF_SYSCALL_TRACEPOINT) + #ifdef CONFIG_SHADOW_CALL_STACK #define INIT_SCS \ .scs_base =3D init_shadow_call_stack, \ diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 35efa2062408..3cac9668aaa8 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -2471,7 +2471,7 @@ void syscall_exit_to_user_mode_work(struct pt_regs *r= egs) =20 rseq_syscall(regs); =20 - if (has_syscall_work(flags) || flags & _TIF_SINGLESTEP) + if (unlikely(flags & _TIF_SYSCALL_EXIT_WORK) || flags & _TIF_SINGLESTEP) syscall_exit_work(regs, flags); } =20 diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c index 66d4da641d97..ec478fc37a9f 100644 --- a/arch/arm64/kernel/syscall.c +++ b/arch/arm64/kernel/syscall.c @@ -101,7 +101,7 @@ static void el0_svc_common(struct pt_regs *regs, int sc= no, int sc_nr, return; } =20 - if (has_syscall_work(flags)) { + if (unlikely(flags & _TIF_SYSCALL_WORK)) { /* * The de-facto standard way to skip a system call using ptrace * is to set the system call to -1 (NO_SYSCALL) and set x0 to a --=20 2.34.1 From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout05.his.huawei.com (canpmsgout05.his.huawei.com [113.46.200.220]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65DE339C65D; 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Tue, 17 Mar 2026 16:20:16 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 08/14] arm64/ptrace: Skip syscall exit reporting for PTRACE_SYSEMU_SINGLESTEP Date: Tue, 17 Mar 2026 16:20:14 +0800 Message-ID: <20260317082020.737779-9-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Align the syscall exit reporting logic with the generic entry framework by skipping the exit stop when PTRACE_SYSEMU_SINGLESTEP is in effect. [Rationale] When a tracer uses PTRACE_SYSEMU_SINGLESTEP, both _TIF_SYSCALL_EMU and _TIF_SINGLESTEP flags are set. Currently, arm64 reports a syscall exit stop whenever _TIF_SINGLESTEP is set, regardless of the emulation state. However, as per the generic entry implementation (see include/linux/entry-common.h): "If SYSCALL_EMU is set, then the only reason to report is when SINGLESTEP is set (i.e. PTRACE_SYSEMU_SINGLESTEP). This syscall instruction has been already reported in syscall_trace_enter()." Since PTRACE_SYSEMU intercepts and skips the actual syscall execution, reporting a subsequent exit stop is redundant and inconsistent with the expected behavior of emulated system calls. [Changes] - Introduce report_single_step(): Add a helper to encapsulate the logic for deciding whether to report a single-step stop at syscall exit. It returns false if _TIF_SYSCALL_EMU is set, ensuring the emulated syscall does not trigger a duplicate report. - Update syscall_exit_work(): Use the new helper to determine the stepping state instead of directly checking _TIF_SINGLESTEP. [Impact] - PTRACE_SINGLESTEP: Continues to report exit stops for actual instructions. - PTRACE_SYSEMU: Continues to skip exit stops. - PTRACE_SYSEMU_SINGLESTEP: Now correctly skips the redundant exit stop, aligning arm64 with the generic entry infrastructure. Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Jinjie Ruan Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/kernel/ptrace.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 3cac9668aaa8..766de3584cff 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -2454,14 +2454,25 @@ int syscall_trace_enter(struct pt_regs *regs, unsig= ned long flags) return ret ? : syscall; } =20 +static inline bool report_single_step(unsigned long flags) +{ + if (flags & _TIF_SYSCALL_EMU) + return false; + + return flags & _TIF_SINGLESTEP; +} + static void syscall_exit_work(struct pt_regs *regs, unsigned long flags) { + bool step; + audit_syscall_exit(regs); =20 if (flags & _TIF_SYSCALL_TRACEPOINT) trace_sys_exit(regs, syscall_get_return_value(current, regs)); =20 - if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) + step =3D report_single_step(flags); + if (step || flags & _TIF_SYSCALL_TRACE) report_syscall_exit(regs); } =20 --=20 2.34.1 From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout09.his.huawei.com (canpmsgout09.his.huawei.com [113.46.200.224]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87779399342; Tue, 17 Mar 2026 08:20:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.224 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735626; cv=none; b=bOhbaH8Azf3YiQrbSBrMDoXZzUVjwjq21uXqyQjTgcGUe3idXUBJrCpI+Sf2U2wE+WctkdEiSxUhyrFyH7RP7ZqxCbbxHwmJYBItPLxPQOB+he3Sk+kOhQTQyTsdPrpZ11yvkdzNuhbENF4FfErAtyuJyViMuX/aIQJbdRC7aLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735626; c=relaxed/simple; bh=g2P5kry99vr8cw61yDTqpGuFCBdmhJOjoQJItv6ps38=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hczh+xU+3Uyb05P/AjP04sBVK2FhcUmsk6UDjLkVcCbNEElPGpUOSklmWcYM+L0K0SW3hLQ9UcXOlt0rf5Muo/BwmgFupoa2qZYjruZtgOahiggIasEBIKOwNL5E0zuDPLRoX25JBep97veFWdMFlqivCofx/6WoCZVB2psxdRY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=uplXnx0C; arc=none smtp.client-ip=113.46.200.224 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="uplXnx0C" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=kCbAK0miUhM9M7h0e+ohSl2GXkOQmbZWJph6U0/6ORw=; b=uplXnx0C55LxS+4tf9CMRpZH7S+iuqu6NlD9tg76Q5uJTgvcsRDqdr/gN7W/XpWnxBIm3ftL+ WDNyAX4y7BMXGD7svc/nMdzA/wxXy4Lg91FAMzpHjX7Fwq2539Rsd0lHbe2Wp4SI/tvxXbiPvOJ BT93eA3RZg/HBg8P6GuM+ZE= Received: from mail.maildlp.com (unknown [172.19.162.92]) by canpmsgout09.his.huawei.com (SkyGuard) with ESMTPS id 4fZlBf4H3Hz1cyPH; Tue, 17 Mar 2026 16:15:22 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 4CB0A40568; Tue, 17 Mar 2026 16:20:21 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 17 Mar 2026 16:20:19 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 09/14] arm64: entry: Convert to generic entry Date: Tue, 17 Mar 2026 16:20:15 +0800 Message-ID: <20260317082020.737779-10-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Implement the generic entry framework for arm64 to handle system call entry and exit. This follows the migration of x86, RISC-V, and LoongArch, consolidating architecture-specific syscall tracing and auditing into the common kernel entry infrastructure. [Background] Arm64 has already adopted generic IRQ entry. Completing the conversion to the generic syscall entry framework reduces architectural divergence, simplifies maintenance, and allows arm64 to automatically benefit from improvements in the common entry code. [Changes] 1. Kconfig and Infrastructure: - Select GENERIC_ENTRY and remove GENERIC_IRQ_ENTRY (now implied). - Migrate struct thread_info to use the syscall_work field instead of TIF flags for syscall-related tasks. 2. Thread Info and Flags: - Remove definitions for TIF_SYSCALL_TRACE, TIF_SYSCALL_AUDIT, TIF_SYSCALL_TRACEPOINT, TIF_SECCOMP, and TIF_SYSCALL_EMU. - Replace _TIF_SYSCALL_WORK and _TIF_SYSCALL_EXIT_WORK with the generic SYSCALL_WORK bitmask. - Map single-step state to SYSCALL_EXIT_TRAP in debug-monitors.c. 3. Architecture-Specific Hooks (asm/entry-common.h): - Implement arch_ptrace_report_syscall_entry() and _exit() by porting the existing arm64 logic to the generic interface. - Add arch_syscall_is_vdso_sigreturn() to asm/syscall.h to support Syscall User Dispatch (SUD). 4. Differentiate between syscall and interrupt entry/exit paths to handle RSEQ slice extensions correctly. - For irq/exception entry/exit: use irqentry_enter_from_user_mode() and irqentry_exit_to_user_mode_prepare(). - For syscall entry/exit: use enter_from_user_mode() and syscall_exit_to_user_mode_prepare(). - Remove exit_to_user_mode_prepare_legacy() which is no longer necessary. 5. rseq_syscall() will be replaced with the static key version, that is "rseq_debug_syscall_return()" 6. Cleanup and Refactoring: - Remove redundant arm64-specific syscall tracing functions from ptrace.c, including syscall_trace_enter(), syscall_exit_work(), and related audit/step helpers. - Update el0_svc_common() in syscall.c to use the generic syscall_work checks and entry/exit call sites. [Why this matters] - Unified Interface: Aligns arm64 with the modern kernel entry standard. - Improved Maintainability: Bug fixes in kernel/entry/common.c now apply to arm64 automatically. - Feature Readiness: Simplifies the implementation of future cross-architecture syscall features. [Compatibility] This conversion maintains full ABI compatibility with existing userspace. The ptrace register-saving behavior, seccomp filtering, and syscall tracing semantics remain identical to the previous implementation. Cc: Will Deacon Cc: Catalin Marinas Cc: Thomas Gleixner Cc: Peter Zijlstra Reviewed-by: Kevin Brodsky Suggested-by: Kevin Brodsky Suggested-by: Mark Rutland Signed-off-by: Jinjie Ruan Acked-by: Peter Zijlstra (Intel) Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/Kconfig | 2 +- arch/arm64/include/asm/entry-common.h | 76 +++++++++++++ arch/arm64/include/asm/syscall.h | 19 +++- arch/arm64/include/asm/thread_info.h | 19 +--- arch/arm64/kernel/debug-monitors.c | 7 ++ arch/arm64/kernel/entry-common.c | 25 ++++- arch/arm64/kernel/ptrace.c | 154 -------------------------- arch/arm64/kernel/signal.c | 2 +- arch/arm64/kernel/syscall.c | 6 +- include/linux/irq-entry-common.h | 8 -- include/linux/rseq_entry.h | 18 --- 11 files changed, 127 insertions(+), 209 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 38dba5f7e4d2..96fef01598be 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -154,9 +154,9 @@ config ARM64 select GENERIC_CPU_DEVICES select GENERIC_CPU_VULNERABILITIES select GENERIC_EARLY_IOREMAP + select GENERIC_ENTRY select GENERIC_IDLE_POLL_SETUP select GENERIC_IOREMAP - select GENERIC_IRQ_ENTRY select GENERIC_IRQ_IPI select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD select GENERIC_IRQ_PROBE diff --git a/arch/arm64/include/asm/entry-common.h b/arch/arm64/include/asm= /entry-common.h index cab8cd78f693..d8bf4bf342e8 100644 --- a/arch/arm64/include/asm/entry-common.h +++ b/arch/arm64/include/asm/entry-common.h @@ -3,14 +3,21 @@ #ifndef _ASM_ARM64_ENTRY_COMMON_H #define _ASM_ARM64_ENTRY_COMMON_H =20 +#include #include =20 +#include #include #include #include #include #include =20 +enum ptrace_syscall_dir { + PTRACE_SYSCALL_ENTER =3D 0, + PTRACE_SYSCALL_EXIT, +}; + #define ARCH_EXIT_TO_USER_MODE_WORK (_TIF_MTE_ASYNC_FAULT | _TIF_FOREIGN_F= PSTATE) =20 static __always_inline void arch_exit_to_user_mode_work(struct pt_regs *re= gs, @@ -54,4 +61,73 @@ static inline bool arch_irqentry_exit_need_resched(void) =20 #define arch_irqentry_exit_need_resched arch_irqentry_exit_need_resched =20 +static __always_inline unsigned long ptrace_save_reg(struct pt_regs *regs, + enum ptrace_syscall_dir dir, + int *regno) +{ + unsigned long saved_reg; + + /* + * We have some ABI weirdness here in the way that we handle syscall + * exit stops because we indicate whether or not the stop has been + * signalled from syscall entry or syscall exit by clobbering a general + * purpose register (ip/r12 for AArch32, x7 for AArch64) in the tracee + * and restoring its old value after the stop. This means that: + * + * - Any writes by the tracer to this register during the stop are + * ignored/discarded. + * + * - The actual value of the register is not available during the stop, + * so the tracer cannot save it and restore it later. + * + * - Syscall stops behave differently to seccomp and pseudo-step traps + * (the latter do not nobble any registers). + */ + *regno =3D (is_compat_task() ? 12 : 7); + saved_reg =3D regs->regs[*regno]; + regs->regs[*regno] =3D dir; + + return saved_reg; +} + +static __always_inline int arch_ptrace_report_syscall_entry(struct pt_regs= *regs) +{ + unsigned long saved_reg; + int regno, ret; + + saved_reg =3D ptrace_save_reg(regs, PTRACE_SYSCALL_ENTER, ®no); + ret =3D ptrace_report_syscall_entry(regs); + if (ret) + forget_syscall(regs); + regs->regs[regno] =3D saved_reg; + + return ret; +} + +#define arch_ptrace_report_syscall_entry arch_ptrace_report_syscall_entry + +static __always_inline void arch_ptrace_report_syscall_exit(struct pt_regs= *regs, + int step) +{ + unsigned long saved_reg; + int regno; + + saved_reg =3D ptrace_save_reg(regs, PTRACE_SYSCALL_EXIT, ®no); + if (!step) { + ptrace_report_syscall_exit(regs, 0); + regs->regs[regno] =3D saved_reg; + } else { + regs->regs[regno] =3D saved_reg; + + /* + * Signal a pseudo-step exception since we are stepping but + * tracer modifications to the registers may have rewound the + * state machine. + */ + ptrace_report_syscall_exit(regs, 1); + } +} + +#define arch_ptrace_report_syscall_exit arch_ptrace_report_syscall_exit + #endif /* _ASM_ARM64_ENTRY_COMMON_H */ diff --git a/arch/arm64/include/asm/syscall.h b/arch/arm64/include/asm/sysc= all.h index dea392c081ca..240d45735cc5 100644 --- a/arch/arm64/include/asm/syscall.h +++ b/arch/arm64/include/asm/syscall.h @@ -9,6 +9,9 @@ #include #include =20 +#include +#include + typedef long (*syscall_fn_t)(const struct pt_regs *regs); =20 extern const syscall_fn_t sys_call_table[]; @@ -120,7 +123,19 @@ static inline int syscall_get_arch(struct task_struct = *task) return AUDIT_ARCH_AARCH64; } =20 -int syscall_trace_enter(struct pt_regs *regs, unsigned long flags); -void syscall_exit_to_user_mode_work(struct pt_regs *regs); +static inline bool arch_syscall_is_vdso_sigreturn(struct pt_regs *regs) +{ + unsigned long sigtramp; + +#ifdef CONFIG_COMPAT + if (is_compat_task()) { + unsigned long sigpage =3D (unsigned long)current->mm->context.sigpage; + + return regs->pc >=3D sigpage && regs->pc < (sigpage + PAGE_SIZE); + } +#endif + sigtramp =3D (unsigned long)VDSO_SYMBOL(current->mm->context.vdso, sigtra= mp); + return regs->pc =3D=3D (sigtramp + 8); +} =20 #endif /* __ASM_SYSCALL_H */ diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/= thread_info.h index 4ae83cb620bb..f89a15dc6ad5 100644 --- a/arch/arm64/include/asm/thread_info.h +++ b/arch/arm64/include/asm/thread_info.h @@ -43,6 +43,7 @@ struct thread_info { void *scs_sp; #endif u32 cpu; + unsigned long syscall_work; /* SYSCALL_WORK_ flags */ }; =20 #define thread_saved_pc(tsk) \ @@ -65,11 +66,6 @@ void arch_setup_new_exec(void); #define TIF_UPROBE 5 /* uprobe breakpoint or singlestep */ #define TIF_MTE_ASYNC_FAULT 6 /* MTE Asynchronous Tag Check Fault */ #define TIF_NOTIFY_SIGNAL 7 /* signal notifications exist */ -#define TIF_SYSCALL_TRACE 8 /* syscall trace active */ -#define TIF_SYSCALL_AUDIT 9 /* syscall auditing */ -#define TIF_SYSCALL_TRACEPOINT 10 /* syscall tracepoint for ftrace */ -#define TIF_SECCOMP 11 /* syscall secure computing */ -#define TIF_SYSCALL_EMU 12 /* syscall emulation active */ #define TIF_PATCH_PENDING 13 /* pending live patching update */ #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_FREEZE 19 @@ -91,27 +87,14 @@ void arch_setup_new_exec(void); #define _TIF_NEED_RESCHED_LAZY (1 << TIF_NEED_RESCHED_LAZY) #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE) -#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) -#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) -#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) -#define _TIF_SECCOMP (1 << TIF_SECCOMP) -#define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU) #define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING) #define _TIF_UPROBE (1 << TIF_UPROBE) -#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) #define _TIF_32BIT (1 << TIF_32BIT) #define _TIF_SVE (1 << TIF_SVE) #define _TIF_MTE_ASYNC_FAULT (1 << TIF_MTE_ASYNC_FAULT) #define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) #define _TIF_TSC_SIGSEGV (1 << TIF_TSC_SIGSEGV) =20 -#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \ - _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | \ - _TIF_SYSCALL_EMU) - -#define _TIF_SYSCALL_EXIT_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \ - _TIF_SYSCALL_TRACEPOINT) - #ifdef CONFIG_SHADOW_CALL_STACK #define INIT_SCS \ .scs_base =3D init_shadow_call_stack, \ diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-m= onitors.c index 29307642f4c9..e67643a70405 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c @@ -385,11 +385,18 @@ void user_enable_single_step(struct task_struct *task) =20 if (!test_and_set_ti_thread_flag(ti, TIF_SINGLESTEP)) set_regs_spsr_ss(task_pt_regs(task)); + + /* + * Ensure that a trap is triggered once stepping out of a system + * call prior to executing any user instruction. + */ + set_task_syscall_work(task, SYSCALL_EXIT_TRAP); } NOKPROBE_SYMBOL(user_enable_single_step); =20 void user_disable_single_step(struct task_struct *task) { clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); + clear_task_syscall_work(task, SYSCALL_EXIT_TRAP); } NOKPROBE_SYMBOL(user_disable_single_step); diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-com= mon.c index 3625797e9ee8..b7ac88bb946c 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -64,6 +64,12 @@ static void noinstr exit_to_kernel_mode(struct pt_regs *= regs, * instrumentable code, or any code which may trigger an exception. */ static __always_inline void arm64_enter_from_user_mode(struct pt_regs *reg= s) +{ + irqentry_enter_from_user_mode(regs); + mte_disable_tco_entry(current); +} + +static __always_inline void arm64_syscall_enter_from_user_mode(struct pt_r= egs *regs) { enter_from_user_mode(regs); mte_disable_tco_entry(current); @@ -78,7 +84,16 @@ static __always_inline void arm64_enter_from_user_mode(s= truct pt_regs *regs) static __always_inline void arm64_exit_to_user_mode(struct pt_regs *regs) { local_irq_disable(); - exit_to_user_mode_prepare_legacy(regs); + irqentry_exit_to_user_mode_prepare(regs); + local_daif_mask(); + mte_check_tfsr_exit(); + exit_to_user_mode(); +} + +static __always_inline void arm64_syscall_exit_to_user_mode(struct pt_regs= *regs) +{ + local_irq_disable(); + syscall_exit_to_user_mode_prepare(regs); local_daif_mask(); mte_check_tfsr_exit(); exit_to_user_mode(); @@ -717,12 +732,12 @@ static void noinstr el0_brk64(struct pt_regs *regs, u= nsigned long esr) =20 static void noinstr el0_svc(struct pt_regs *regs) { - arm64_enter_from_user_mode(regs); + arm64_syscall_enter_from_user_mode(regs); cortex_a76_erratum_1463225_svc_handler(); fpsimd_syscall_enter(); local_daif_restore(DAIF_PROCCTX); do_el0_svc(regs); - arm64_exit_to_user_mode(regs); + arm64_syscall_exit_to_user_mode(regs); fpsimd_syscall_exit(); } =20 @@ -869,11 +884,11 @@ static void noinstr el0_cp15(struct pt_regs *regs, un= signed long esr) =20 static void noinstr el0_svc_compat(struct pt_regs *regs) { - arm64_enter_from_user_mode(regs); + arm64_syscall_enter_from_user_mode(regs); cortex_a76_erratum_1463225_svc_handler(); local_daif_restore(DAIF_PROCCTX); do_el0_svc_compat(regs); - arm64_exit_to_user_mode(regs); + arm64_syscall_exit_to_user_mode(regs); } =20 static void noinstr el0_bkpt32(struct pt_regs *regs, unsigned long esr) diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 766de3584cff..9acc314bc376 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -8,7 +8,6 @@ * Copyright (C) 2012 ARM Ltd. */ =20 -#include #include #include #include @@ -18,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -28,7 +26,6 @@ #include #include #include -#include =20 #include #include @@ -38,13 +35,9 @@ #include #include #include -#include #include #include =20 -#define CREATE_TRACE_POINTS -#include - struct pt_regs_offset { const char *name; int offset; @@ -2339,153 +2332,6 @@ long arch_ptrace(struct task_struct *child, long re= quest, return ptrace_request(child, request, addr, data); } =20 -enum ptrace_syscall_dir { - PTRACE_SYSCALL_ENTER =3D 0, - PTRACE_SYSCALL_EXIT, -}; - -static __always_inline unsigned long ptrace_save_reg(struct pt_regs *regs, - enum ptrace_syscall_dir dir, - int *regno) -{ - unsigned long saved_reg; - - /* - * We have some ABI weirdness here in the way that we handle syscall - * exit stops because we indicate whether or not the stop has been - * signalled from syscall entry or syscall exit by clobbering a general - * purpose register (ip/r12 for AArch32, x7 for AArch64) in the tracee - * and restoring its old value after the stop. This means that: - * - * - Any writes by the tracer to this register during the stop are - * ignored/discarded. - * - * - The actual value of the register is not available during the stop, - * so the tracer cannot save it and restore it later. - * - * - Syscall stops behave differently to seccomp and pseudo-step traps - * (the latter do not nobble any registers). - */ - *regno =3D (is_compat_task() ? 12 : 7); - saved_reg =3D regs->regs[*regno]; - regs->regs[*regno] =3D dir; - - return saved_reg; -} - -static int report_syscall_entry(struct pt_regs *regs) -{ - unsigned long saved_reg; - int regno, ret; - - saved_reg =3D ptrace_save_reg(regs, PTRACE_SYSCALL_ENTER, ®no); - ret =3D ptrace_report_syscall_entry(regs); - if (ret) - forget_syscall(regs); - regs->regs[regno] =3D saved_reg; - - return ret; -} - -static void report_syscall_exit(struct pt_regs *regs) -{ - unsigned long saved_reg; - int regno; - - saved_reg =3D ptrace_save_reg(regs, PTRACE_SYSCALL_EXIT, ®no); - if (!test_thread_flag(TIF_SINGLESTEP)) { - ptrace_report_syscall_exit(regs, 0); - regs->regs[regno] =3D saved_reg; - } else { - regs->regs[regno] =3D saved_reg; - - /* - * Signal a pseudo-step exception since we are stepping but - * tracer modifications to the registers may have rewound the - * state machine. - */ - ptrace_report_syscall_exit(regs, 1); - } -} - -static inline void syscall_enter_audit(struct pt_regs *regs, long syscall) -{ - if (unlikely(audit_context())) { - unsigned long args[6]; - - syscall_get_arguments(current, regs, args); - audit_syscall_entry(syscall, args[0], args[1], args[2], args[3]); - } -} - -int syscall_trace_enter(struct pt_regs *regs, unsigned long flags) -{ - long syscall; - int ret; - - if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) { - ret =3D report_syscall_entry(regs); - if (ret || (flags & _TIF_SYSCALL_EMU)) - return NO_SYSCALL; - } - - /* Do the secure computing after ptrace; failures should be fast. */ - if (flags & _TIF_SECCOMP) { - ret =3D __secure_computing(); - if (ret =3D=3D -1) - return NO_SYSCALL; - } - - /* Either of the above might have changed the syscall number */ - syscall =3D syscall_get_nr(current, regs); - - if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) { - trace_sys_enter(regs, syscall); - - /* - * Probes or BPF hooks in the tracepoint may have changed the - * system call number as well. - */ - syscall =3D syscall_get_nr(current, regs); - } - - syscall_enter_audit(regs, syscall); - - return ret ? : syscall; -} - -static inline bool report_single_step(unsigned long flags) -{ - if (flags & _TIF_SYSCALL_EMU) - return false; - - return flags & _TIF_SINGLESTEP; -} - -static void syscall_exit_work(struct pt_regs *regs, unsigned long flags) -{ - bool step; - - audit_syscall_exit(regs); - - if (flags & _TIF_SYSCALL_TRACEPOINT) - trace_sys_exit(regs, syscall_get_return_value(current, regs)); - - step =3D report_single_step(flags); - if (step || flags & _TIF_SYSCALL_TRACE) - report_syscall_exit(regs); -} - -void syscall_exit_to_user_mode_work(struct pt_regs *regs) -{ - unsigned long flags =3D read_thread_flags(); - - rseq_syscall(regs); - - if (unlikely(flags & _TIF_SYSCALL_EXIT_WORK) || flags & _TIF_SINGLESTEP) - syscall_exit_work(regs, flags); -} - /* * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a. * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which = is diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 08ffc5a5aea4..7ca30ee41e7a 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -8,8 +8,8 @@ =20 #include #include +#include #include -#include #include #include #include diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c index ec478fc37a9f..77d00a5cf0e9 100644 --- a/arch/arm64/kernel/syscall.c +++ b/arch/arm64/kernel/syscall.c @@ -2,6 +2,7 @@ =20 #include #include +#include #include #include #include @@ -68,6 +69,7 @@ static void invoke_syscall(struct pt_regs *regs, unsigned= int scno, static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, const syscall_fn_t syscall_table[]) { + unsigned long work =3D READ_ONCE(current_thread_info()->syscall_work); unsigned long flags =3D read_thread_flags(); =20 regs->orig_x0 =3D regs->regs[0]; @@ -101,7 +103,7 @@ static void el0_svc_common(struct pt_regs *regs, int sc= no, int sc_nr, return; } =20 - if (unlikely(flags & _TIF_SYSCALL_WORK)) { + if (unlikely(work & SYSCALL_WORK_ENTER)) { /* * The de-facto standard way to skip a system call using ptrace * is to set the system call to -1 (NO_SYSCALL) and set x0 to a @@ -119,7 +121,7 @@ static void el0_svc_common(struct pt_regs *regs, int sc= no, int sc_nr, */ if (scno =3D=3D NO_SYSCALL) syscall_set_return_value(current, regs, -ENOSYS, 0); - scno =3D syscall_trace_enter(regs, flags); + scno =3D syscall_trace_enter(regs, work); if (scno =3D=3D NO_SYSCALL) goto trace_exit; } diff --git a/include/linux/irq-entry-common.h b/include/linux/irq-entry-com= mon.h index d26d1b1bcbfb..6519b4a30dc1 100644 --- a/include/linux/irq-entry-common.h +++ b/include/linux/irq-entry-common.h @@ -236,14 +236,6 @@ static __always_inline void __exit_to_user_mode_valida= te(void) lockdep_sys_exit(); } =20 -/* Temporary workaround to keep ARM64 alive */ -static __always_inline void exit_to_user_mode_prepare_legacy(struct pt_reg= s *regs) -{ - __exit_to_user_mode_prepare(regs); - rseq_exit_to_user_mode_legacy(); - __exit_to_user_mode_validate(); -} - /** * syscall_exit_to_user_mode_prepare - call exit_to_user_mode_loop() if re= quired * @regs: Pointer to pt_regs on entry stack diff --git a/include/linux/rseq_entry.h b/include/linux/rseq_entry.h index c6831c93cd6e..e9c4108ac514 100644 --- a/include/linux/rseq_entry.h +++ b/include/linux/rseq_entry.h @@ -743,24 +743,6 @@ static __always_inline void rseq_irqentry_exit_to_user= _mode(void) ev->events =3D 0; } =20 -/* Required to keep ARM64 working */ -static __always_inline void rseq_exit_to_user_mode_legacy(void) -{ - struct rseq_event *ev =3D ¤t->rseq.event; - - rseq_stat_inc(rseq_stats.exit); - - if (static_branch_unlikely(&rseq_debug_enabled)) - WARN_ON_ONCE(ev->sched_switch); - - /* - * Ensure that event (especially user_irq) is cleared when the - * interrupt did not result in a schedule and therefore the - * rseq processing did not clear it. - */ - ev->events =3D 0; -} - void __rseq_debug_syscall_return(struct pt_regs *regs); =20 static __always_inline void rseq_debug_syscall_return(struct pt_regs *regs) --=20 2.34.1 From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout02.his.huawei.com (canpmsgout02.his.huawei.com [113.46.200.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44AC239E16B; Tue, 17 Mar 2026 08:20:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.217 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735626; cv=none; b=Dctnmg0mgnvtWZvnigKRY/QkiWaM4Vej8sHAUZaDFaXzyMYh1z/GMcKZwz0vPoHF9uD64BrtKgui++AQdZn9ogGfZSeMB4Kqy14x94UnFzrBLGdnBfc4OyIPSxer1VLsP+HxZ2AQ2Dh1Op1GWUdaeW1toYOIzKdFCoR5yNV77Kk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735626; c=relaxed/simple; bh=+u6IynmtBccKp672pOG1061R64NH7rAvAaMzjVYceog=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) After converting arm64 to Generic Entry framework, the compiler no longer inlines el0_svc_common() into its caller do_el0_svc(). This introduces a small but measurable overhead in the critical system call path. Manually forcing el0_svc_common() to be inlined restores the performance. Benchmarking with perf bench syscall basic on a Kunpeng 920 platform (based on v6.19-rc1) shows a ~1% performance uplift. Inlining this function reduces function prologue/epilogue overhead and allows for better compiler optimization in the hot system call dispatch path. | Metric | W/O this patch | With this patch | Change | | ---------- | -------------- | --------------- | --------- | | Total time | 2.195 [sec] | 2.171 [sec] | =E2=86=931.1% | | usecs/op | 0.219575 | 0.217192 | =E2=86=931.1% | | ops/sec | 4,554,260 | 4,604,225 | =E2=86=911.1% | Reviewed-by: Kevin Brodsky Signed-off-by: Jinjie Ruan Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/kernel/syscall.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c index 77d00a5cf0e9..6fcd97c46716 100644 --- a/arch/arm64/kernel/syscall.c +++ b/arch/arm64/kernel/syscall.c @@ -66,8 +66,8 @@ static void invoke_syscall(struct pt_regs *regs, unsigned= int scno, choose_random_kstack_offset(get_random_u16()); } =20 -static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, - const syscall_fn_t syscall_table[]) +static __always_inline void el0_svc_common(struct pt_regs *regs, int scno,= int sc_nr, + const syscall_fn_t syscall_table[]) { unsigned long work =3D READ_ONCE(current_thread_info()->syscall_work); unsigned long flags =3D read_thread_flags(); --=20 2.34.1 From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com [113.46.200.222]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB22E3A0E86; Tue, 17 Mar 2026 08:20:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.222 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735635; cv=none; b=XI203veELO+smmq1tUKj0HY31DIEDJgAfUlQwzljh25uUPtpmGvQpRsx0w9fIZj9Kyjsq2U1HPZcQ7RBZcTQksFCUcG8VMFoJbRCi2LJCFuKVU1FDP22PMtblrOWLNJcsWlVwGAKRLl5sgOh+AVPWRsZKOZ4u7mWFMSCenWAYq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735635; c=relaxed/simple; bh=BGp7zk8B2t20hYTiZIqVxD3DRBS1B689lkiVbeJS+zg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UIqkwf/colsBgWsPmB0vAgQ7xAoqEfBdo1GigPSQ+i4RIfoC00ewRSqKu16Pg4P93K4cDZhDdrbPdxtxZUYeM06uITiOXhvSchMs/UjMYQ1v/O/YpK8HzSANGvoiCJD4V9G/9nw67hIE91gpCr5+xnkmqdME5ypvZhW0MTWSz4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=BnSm81uM; arc=none smtp.client-ip=113.46.200.222 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="BnSm81uM" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=oOV2eb8tJvG534b50oNWBHLwq8WVhk7Xz2uHfrw+ZgA=; b=BnSm81uMsReEk2FqmcZXl6xKVVwBVaj1Vzway7Btg3BIolAWQKuI5qNAR+Quvj3mCWWEN3Npx oQwJ+JjOIFsnQ8U8mV8x5U+9Ig5rvCX0EV5VQKNoD8ogPK3MTGwIwshaabGvTBdGQWhiqU1sw4v OUrvC4wA6WJn8jWi1T1ZOz4= Received: from mail.maildlp.com (unknown [172.19.163.214]) by canpmsgout07.his.huawei.com (SkyGuard) with ESMTPS id 4fZlBk5xgwzLlrZ; Tue, 17 Mar 2026 16:15:26 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id A0FEF40561; Tue, 17 Mar 2026 16:20:25 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 17 Mar 2026 16:20:23 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 11/14] s390: Rename TIF_SINGLE_STEP to TIF_SINGLESTEP Date: Tue, 17 Mar 2026 16:20:17 +0800 Message-ID: <20260317082020.737779-12-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Rename TIF_SINGLE_STEP to TIF_SINGLESTEP to align with the naming convention used by arm64, x86, and other architectures. By aligning the name, TIF_SINGLESTEP can be consolidated into the generic TIF bits definitions, reducing architectural divergence and simplifying cross-architecture entry/exit logic. No functional changes intended. Acked-by: Heiko Carstens Signed-off-by: Jinjie Ruan Reviewed-by: Kevin Brodsky Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/s390/include/asm/thread_info.h | 4 ++-- arch/s390/kernel/process.c | 2 +- arch/s390/kernel/ptrace.c | 20 ++++++++++---------- arch/s390/kernel/signal.c | 6 +++--- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/th= read_info.h index 6a548a819400..1bcd42614e41 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -69,7 +69,7 @@ void arch_setup_new_exec(void); #define TIF_GUARDED_STORAGE 17 /* load guarded storage control block */ #define TIF_ISOLATE_BP_GUEST 18 /* Run KVM guests with isolated BP */ #define TIF_PER_TRAP 19 /* Need to handle PER trap on exit to usermode */ -#define TIF_SINGLE_STEP 21 /* This task is single stepped */ +#define TIF_SINGLESTEP 21 /* This task is single stepped */ #define TIF_BLOCK_STEP 22 /* This task is block stepped */ #define TIF_UPROBE_SINGLESTEP 23 /* This task is uprobe single stepped */ =20 @@ -77,7 +77,7 @@ void arch_setup_new_exec(void); #define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE) #define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST) #define _TIF_PER_TRAP BIT(TIF_PER_TRAP) -#define _TIF_SINGLE_STEP BIT(TIF_SINGLE_STEP) +#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) #define _TIF_BLOCK_STEP BIT(TIF_BLOCK_STEP) #define _TIF_UPROBE_SINGLESTEP BIT(TIF_UPROBE_SINGLESTEP) =20 diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c index 0df95dcb2101..3accc0c064a0 100644 --- a/arch/s390/kernel/process.c +++ b/arch/s390/kernel/process.c @@ -122,7 +122,7 @@ int copy_thread(struct task_struct *p, const struct ker= nel_clone_args *args) /* Don't copy debug registers */ memset(&p->thread.per_user, 0, sizeof(p->thread.per_user)); memset(&p->thread.per_event, 0, sizeof(p->thread.per_event)); - clear_tsk_thread_flag(p, TIF_SINGLE_STEP); + clear_tsk_thread_flag(p, TIF_SINGLESTEP); p->thread.per_flags =3D 0; /* Initialize per thread user and system timer values */ p->thread.user_timer =3D 0; diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c index 125ca4c4e30c..d2cf91f4ac3f 100644 --- a/arch/s390/kernel/ptrace.c +++ b/arch/s390/kernel/ptrace.c @@ -90,8 +90,8 @@ void update_cr_regs(struct task_struct *task) new.start.val =3D thread->per_user.start; new.end.val =3D thread->per_user.end; =20 - /* merge TIF_SINGLE_STEP into user specified PER registers. */ - if (test_tsk_thread_flag(task, TIF_SINGLE_STEP) || + /* merge TIF_SINGLESTEP into user specified PER registers. */ + if (test_tsk_thread_flag(task, TIF_SINGLESTEP) || test_tsk_thread_flag(task, TIF_UPROBE_SINGLESTEP)) { if (test_tsk_thread_flag(task, TIF_BLOCK_STEP)) new.control.val |=3D PER_EVENT_BRANCH; @@ -119,18 +119,18 @@ void update_cr_regs(struct task_struct *task) void user_enable_single_step(struct task_struct *task) { clear_tsk_thread_flag(task, TIF_BLOCK_STEP); - set_tsk_thread_flag(task, TIF_SINGLE_STEP); + set_tsk_thread_flag(task, TIF_SINGLESTEP); } =20 void user_disable_single_step(struct task_struct *task) { clear_tsk_thread_flag(task, TIF_BLOCK_STEP); - clear_tsk_thread_flag(task, TIF_SINGLE_STEP); + clear_tsk_thread_flag(task, TIF_SINGLESTEP); } =20 void user_enable_block_step(struct task_struct *task) { - set_tsk_thread_flag(task, TIF_SINGLE_STEP); + set_tsk_thread_flag(task, TIF_SINGLESTEP); set_tsk_thread_flag(task, TIF_BLOCK_STEP); } =20 @@ -143,7 +143,7 @@ void ptrace_disable(struct task_struct *task) { memset(&task->thread.per_user, 0, sizeof(task->thread.per_user)); memset(&task->thread.per_event, 0, sizeof(task->thread.per_event)); - clear_tsk_thread_flag(task, TIF_SINGLE_STEP); + clear_tsk_thread_flag(task, TIF_SINGLESTEP); clear_tsk_thread_flag(task, TIF_PER_TRAP); task->thread.per_flags =3D 0; } @@ -155,19 +155,19 @@ static inline unsigned long __peek_user_per(struct ta= sk_struct *child, { if (addr =3D=3D offsetof(struct per_struct_kernel, cr9)) /* Control bits of the active per set. */ - return test_thread_flag(TIF_SINGLE_STEP) ? + return test_thread_flag(TIF_SINGLESTEP) ? PER_EVENT_IFETCH : child->thread.per_user.control; else if (addr =3D=3D offsetof(struct per_struct_kernel, cr10)) /* Start address of the active per set. */ - return test_thread_flag(TIF_SINGLE_STEP) ? + return test_thread_flag(TIF_SINGLESTEP) ? 0 : child->thread.per_user.start; else if (addr =3D=3D offsetof(struct per_struct_kernel, cr11)) /* End address of the active per set. */ - return test_thread_flag(TIF_SINGLE_STEP) ? + return test_thread_flag(TIF_SINGLESTEP) ? -1UL : child->thread.per_user.end; else if (addr =3D=3D offsetof(struct per_struct_kernel, bits)) /* Single-step bit. */ - return test_thread_flag(TIF_SINGLE_STEP) ? + return test_thread_flag(TIF_SINGLESTEP) ? (1UL << (BITS_PER_LONG - 1)) : 0; else if (addr =3D=3D offsetof(struct per_struct_kernel, starting_addr)) /* Start address of the user specified per set. */ diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c index 4874de5edea0..83f7650f2032 100644 --- a/arch/s390/kernel/signal.c +++ b/arch/s390/kernel/signal.c @@ -423,7 +423,7 @@ static void handle_signal(struct ksignal *ksig, sigset_= t *oldset, else ret =3D setup_frame(ksig->sig, &ksig->ka, oldset, regs); =20 - signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLE_STEP)); + signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP)); } =20 /* @@ -491,7 +491,7 @@ void arch_do_signal_or_restart(struct pt_regs *regs) regs->gprs[2] =3D regs->orig_gpr2; current->restart_block.arch_data =3D regs->psw.addr; regs->psw.addr =3D VDSO_SYMBOL(current, restart_syscall); - if (test_thread_flag(TIF_SINGLE_STEP)) + if (test_thread_flag(TIF_SINGLESTEP)) clear_thread_flag(TIF_PER_TRAP); break; case -ERESTARTNOHAND: @@ -499,7 +499,7 @@ void arch_do_signal_or_restart(struct pt_regs *regs) case -ERESTARTNOINTR: regs->gprs[2] =3D regs->orig_gpr2; regs->psw.addr =3D __rewind_psw(regs->psw, regs->int_code >> 16); - if (test_thread_flag(TIF_SINGLE_STEP)) + if (test_thread_flag(TIF_SINGLESTEP)) clear_thread_flag(TIF_PER_TRAP); break; } --=20 2.34.1 From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout06.his.huawei.com (canpmsgout06.his.huawei.com [113.46.200.221]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B88F39FCD1; Tue, 17 Mar 2026 08:20:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.221 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735632; cv=none; b=cd0Jq0M827SvNmc6Wb0WLpFX2ziRUZHBt+4Va4pQVRwjPvofnynIPXkHb3dcyr+c6z9Gs80nPQimR/JDEo6Zp2diZlGYtSUf/+i6qDb+aq9Eb2YK3aUrqvrdfzEw6EJLeTA6dEWc5uVeJad4ZjnIckgMhoQCdyWOLprzUVCo0vI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773735632; c=relaxed/simple; bh=YKxmf/BhHq/A+Q52u2poJYCuMFCK4A8AvkUx6sYDEMc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Kami6HuvtHQcqd2zcvcW2tf2B5YID4kNfJes44sAcqMx552gNqwUpww8l+b+FvK1UDHuya5xYxdjcXUOM8gr12vnss++dyRvNc0n0iA2ijBZDqIETgLlILHpahDMtj3sq8/Fkizw1gAFYql1a+ctwjYb59mj6nW9sv8y7wtibIE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=1cJ7cBxD; arc=none smtp.client-ip=113.46.200.221 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="1cJ7cBxD" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=Eag8zPhD7u5fRza4jXSIatUtv9E7ORwKTXXdLDDUNHs=; b=1cJ7cBxD6pB9GrNpH5o9q9dR4XFfSvFxNaU4gsi3/u+ezynBjCqJYa+Ynw3qZtGRPjOnujOh7 fX85D6iinj9qtvWWlUw7xrutFxCUAV/1ttij6BdeKIno2VGPTSTey7s3VO+6C51bvU5Bp/4uOmC 6VuaMJxpnn4uxyWHGyGGxC4= Received: from mail.maildlp.com (unknown [172.19.162.223]) by canpmsgout06.his.huawei.com (SkyGuard) with ESMTPS id 4fZlBn4hn4zRhR0; Tue, 17 Mar 2026 16:15:29 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id BDDC940561; Tue, 17 Mar 2026 16:20:27 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 17 Mar 2026 16:20:25 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 12/14] asm-generic: Move TIF_SINGLESTEP to generic TIF bits Date: Tue, 17 Mar 2026 16:20:18 +0800 Message-ID: <20260317082020.737779-13-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Currently, x86, ARM64, s390, and LoongArch all define and use TIF_SINGLESTEP to track single-stepping state. Since this flag is shared across multiple major architectures and serves a common purpose in the generic entry/exit paths, move TIF_SINGLESTEP into the generic Thread Information Flags (TIF) infrastructure. This consolidation reduces architecture-specific boilerplate code and ensures consistency for generic features that rely on single-step state tracking. Cc: Thomas Gleixner Acked-by: Heiko Carstens # s390 Signed-off-by: Jinjie Ruan Reviewed-by: Kevin Brodsky Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/loongarch/include/asm/thread_info.h | 11 +++++------ arch/s390/include/asm/thread_info.h | 7 +++---- arch/x86/include/asm/thread_info.h | 6 ++---- include/asm-generic/thread_info_tif.h | 5 +++++ 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/loongarch/include/asm/thread_info.h b/arch/loongarch/incl= ude/asm/thread_info.h index 4d7117fcdc78..a2ec87f18e1d 100644 --- a/arch/loongarch/include/asm/thread_info.h +++ b/arch/loongarch/include/asm/thread_info.h @@ -70,6 +70,7 @@ register unsigned long current_stack_pointer __asm__("$sp= "); */ #define HAVE_TIF_NEED_RESCHED_LAZY #define HAVE_TIF_RESTORE_SIGMASK +#define HAVE_TIF_SINGLESTEP =20 #include =20 @@ -82,11 +83,10 @@ register unsigned long current_stack_pointer __asm__("$= sp"); #define TIF_32BIT_REGS 21 /* 32-bit general purpose registers */ #define TIF_32BIT_ADDR 22 /* 32-bit address space */ #define TIF_LOAD_WATCH 23 /* If set, load watch registers */ -#define TIF_SINGLESTEP 24 /* Single Step */ -#define TIF_LSX_CTX_LIVE 25 /* LSX context must be preserved */ -#define TIF_LASX_CTX_LIVE 26 /* LASX context must be preserved */ -#define TIF_USEDLBT 27 /* LBT was used by this task this quantum (SMP) */ -#define TIF_LBT_CTX_LIVE 28 /* LBT context must be preserved */ +#define TIF_LSX_CTX_LIVE 24 /* LSX context must be preserved */ +#define TIF_LASX_CTX_LIVE 25 /* LASX context must be preserved */ +#define TIF_USEDLBT 26 /* LBT was used by this task this quantum (SMP) */ +#define TIF_LBT_CTX_LIVE 27 /* LBT context must be preserved */ =20 #define _TIF_NOHZ BIT(TIF_NOHZ) #define _TIF_USEDFPU BIT(TIF_USEDFPU) @@ -96,7 +96,6 @@ register unsigned long current_stack_pointer __asm__("$sp= "); #define _TIF_32BIT_REGS BIT(TIF_32BIT_REGS) #define _TIF_32BIT_ADDR BIT(TIF_32BIT_ADDR) #define _TIF_LOAD_WATCH BIT(TIF_LOAD_WATCH) -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) #define _TIF_LSX_CTX_LIVE BIT(TIF_LSX_CTX_LIVE) #define _TIF_LASX_CTX_LIVE BIT(TIF_LASX_CTX_LIVE) #define _TIF_USEDLBT BIT(TIF_USEDLBT) diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/th= read_info.h index 1bcd42614e41..95be5258a422 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -61,6 +61,7 @@ void arch_setup_new_exec(void); */ #define HAVE_TIF_NEED_RESCHED_LAZY #define HAVE_TIF_RESTORE_SIGMASK +#define HAVE_TIF_SINGLESTEP =20 #include =20 @@ -69,15 +70,13 @@ void arch_setup_new_exec(void); #define TIF_GUARDED_STORAGE 17 /* load guarded storage control block */ #define TIF_ISOLATE_BP_GUEST 18 /* Run KVM guests with isolated BP */ #define TIF_PER_TRAP 19 /* Need to handle PER trap on exit to usermode */ -#define TIF_SINGLESTEP 21 /* This task is single stepped */ -#define TIF_BLOCK_STEP 22 /* This task is block stepped */ -#define TIF_UPROBE_SINGLESTEP 23 /* This task is uprobe single stepped */ +#define TIF_BLOCK_STEP 20 /* This task is block stepped */ +#define TIF_UPROBE_SINGLESTEP 21 /* This task is uprobe single stepped */ =20 #define _TIF_ASCE_PRIMARY BIT(TIF_ASCE_PRIMARY) #define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE) #define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST) #define _TIF_PER_TRAP BIT(TIF_PER_TRAP) -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) #define _TIF_BLOCK_STEP BIT(TIF_BLOCK_STEP) #define _TIF_UPROBE_SINGLESTEP BIT(TIF_UPROBE_SINGLESTEP) =20 diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thre= ad_info.h index 0067684afb5b..f59072ba1473 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -98,9 +98,8 @@ struct thread_info { #define TIF_IO_BITMAP 22 /* uses I/O bitmap */ #define TIF_SPEC_FORCE_UPDATE 23 /* Force speculation MSR update in contex= t switch */ #define TIF_FORCED_TF 24 /* true if TF in eflags artificially */ -#define TIF_SINGLESTEP 25 /* reenable singlestep on user return*/ -#define TIF_BLOCKSTEP 26 /* set when we want DEBUGCTLMSR_BTF */ -#define TIF_ADDR32 27 /* 32-bit address space on 64 bits */ +#define TIF_BLOCKSTEP 25 /* set when we want DEBUGCTLMSR_BTF */ +#define TIF_ADDR32 26 /* 32-bit address space on 64 bits */ =20 #define _TIF_SSBD BIT(TIF_SSBD) #define _TIF_SPEC_IB BIT(TIF_SPEC_IB) @@ -112,7 +111,6 @@ struct thread_info { #define _TIF_SPEC_FORCE_UPDATE BIT(TIF_SPEC_FORCE_UPDATE) #define _TIF_FORCED_TF BIT(TIF_FORCED_TF) #define _TIF_BLOCKSTEP BIT(TIF_BLOCKSTEP) -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) #define _TIF_ADDR32 BIT(TIF_ADDR32) =20 /* flags to check in __switch_to() */ diff --git a/include/asm-generic/thread_info_tif.h b/include/asm-generic/th= read_info_tif.h index da1610a78f92..b277fe06aee3 100644 --- a/include/asm-generic/thread_info_tif.h +++ b/include/asm-generic/thread_info_tif.h @@ -48,4 +48,9 @@ #define TIF_RSEQ 11 // Run RSEQ fast path #define _TIF_RSEQ BIT(TIF_RSEQ) =20 +#ifdef HAVE_TIF_SINGLESTEP +#define TIF_SINGLESTEP 12 /* reenable singlestep on user return*/ +#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) +#endif + #endif /* _ASM_GENERIC_THREAD_INFO_TIF_H_ */ --=20 2.34.1 From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout05.his.huawei.com (canpmsgout05.his.huawei.com [113.46.200.220]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFF6339B4AF; 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Tue, 17 Mar 2026 16:20:27 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 13/14] arm64: Use generic TIF bits for common thread flags Date: Tue, 17 Mar 2026 16:20:19 +0800 Message-ID: <20260317082020.737779-14-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Use the generic TIF bits defined in for standard thread flags (TIF_SIGPENDING, TIF_NEED_RESCHED, TIF_NOTIFY_RESUME, TIF_RESTORE_SIGMASK, TIF_SINGLESTEP, etc.) instead of defining them locally. Arm64-specific bits (TIF_FOREIGN_FPSTATE, TIF_MTE_ASYNC_FAULT, TIF_SVE, TIF_SSBD, etc.) are renumbered to start at bit 16 to avoid conflicts. This enables RSEQ optimizations which require CONFIG_HAVE_GENERIC_TIF_BITS combined with the generic entry infrastructure (already used by arm64). Cc: Thomas Gleixner Signed-off-by: Jinjie Ruan Reviewed-by: Kevin Brodsky Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun --- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/thread_info.h | 62 ++++++++++++---------------- 2 files changed, 28 insertions(+), 35 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 96fef01598be..33cf901fb1a0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -224,6 +224,7 @@ config ARM64 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI select HAVE_BUILDTIME_MCOUNT_SORT select HAVE_EFFICIENT_UNALIGNED_ACCESS + select HAVE_GENERIC_TIF_BITS select HAVE_GUP_FAST select HAVE_FTRACE_GRAPH_FUNC select HAVE_FUNCTION_TRACER diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/= thread_info.h index f89a15dc6ad5..be1a0651cfe2 100644 --- a/arch/arm64/include/asm/thread_info.h +++ b/arch/arm64/include/asm/thread_info.h @@ -58,42 +58,34 @@ void arch_setup_new_exec(void); =20 #endif =20 -#define TIF_SIGPENDING 0 /* signal pending */ -#define TIF_NEED_RESCHED 1 /* rescheduling necessary */ -#define TIF_NEED_RESCHED_LAZY 2 /* Lazy rescheduling needed */ -#define TIF_NOTIFY_RESUME 3 /* callback before returning to user */ -#define TIF_FOREIGN_FPSTATE 4 /* CPU's FP state is not current's */ -#define TIF_UPROBE 5 /* uprobe breakpoint or singlestep */ -#define TIF_MTE_ASYNC_FAULT 6 /* MTE Asynchronous Tag Check Fault */ -#define TIF_NOTIFY_SIGNAL 7 /* signal notifications exist */ -#define TIF_PATCH_PENDING 13 /* pending live patching update */ -#define TIF_MEMDIE 18 /* is terminating due to OOM killer */ -#define TIF_FREEZE 19 -#define TIF_RESTORE_SIGMASK 20 -#define TIF_SINGLESTEP 21 -#define TIF_32BIT 22 /* 32bit process */ -#define TIF_SVE 23 /* Scalable Vector Extension in use */ -#define TIF_SVE_VL_INHERIT 24 /* Inherit SVE vl_onexec across exec */ -#define TIF_SSBD 25 /* Wants SSB mitigation */ -#define TIF_TAGGED_ADDR 26 /* Allow tagged user addresses */ -#define TIF_SME 27 /* SME in use */ -#define TIF_SME_VL_INHERIT 28 /* Inherit SME vl_onexec across exec */ -#define TIF_KERNEL_FPSTATE 29 /* Task is in a kernel mode FPSIMD section */ -#define TIF_TSC_SIGSEGV 30 /* SIGSEGV on counter-timer access */ -#define TIF_LAZY_MMU_PENDING 31 /* Ops pending for lazy mmu mode exit */ +/* + * Tell the generic TIF infrastructure which bits arm64 supports + */ +#define HAVE_TIF_NEED_RESCHED_LAZY +#define HAVE_TIF_RESTORE_SIGMASK +#define HAVE_TIF_SINGLESTEP + +#include + +#define TIF_FOREIGN_FPSTATE 16 /* CPU's FP state is not current's */ +#define TIF_MTE_ASYNC_FAULT 17 /* MTE Asynchronous Tag Check Fault */ +#define TIF_FREEZE 18 +#define TIF_32BIT 19 /* 32bit process */ +#define TIF_SVE 20 /* Scalable Vector Extension in use */ +#define TIF_SVE_VL_INHERIT 21 /* Inherit SVE vl_onexec across exec */ +#define TIF_SSBD 22 /* Wants SSB mitigation */ +#define TIF_TAGGED_ADDR 23 /* Allow tagged user addresses */ +#define TIF_SME 24 /* SME in use */ +#define TIF_SME_VL_INHERIT 25 /* Inherit SME vl_onexec across exec */ +#define TIF_KERNEL_FPSTATE 26 /* Task is in a kernel mode FPSIMD section */ +#define TIF_TSC_SIGSEGV 27 /* SIGSEGV on counter-timer access */ +#define TIF_LAZY_MMU_PENDING 28 /* Ops pending for lazy mmu mode exit */ =20 -#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) -#define _TIF_NEED_RESCHED_LAZY (1 << TIF_NEED_RESCHED_LAZY) -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) -#define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE) -#define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING) -#define _TIF_UPROBE (1 << TIF_UPROBE) -#define _TIF_32BIT (1 << TIF_32BIT) -#define _TIF_SVE (1 << TIF_SVE) -#define _TIF_MTE_ASYNC_FAULT (1 << TIF_MTE_ASYNC_FAULT) -#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) -#define _TIF_TSC_SIGSEGV (1 << TIF_TSC_SIGSEGV) +#define _TIF_FOREIGN_FPSTATE BIT(TIF_FOREIGN_FPSTATE) +#define _TIF_32BIT BIT(TIF_32BIT) +#define _TIF_SVE BIT(TIF_SVE) +#define _TIF_MTE_ASYNC_FAULT BIT(TIF_MTE_ASYNC_FAULT) +#define _TIF_TSC_SIGSEGV BIT(TIF_TSC_SIGSEGV) =20 #ifdef CONFIG_SHADOW_CALL_STACK #define INIT_SCS \ --=20 2.34.1 From nobody Tue Apr 7 01:03:54 2026 Received: from canpmsgout09.his.huawei.com (canpmsgout09.his.huawei.com [113.46.200.224]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F397239B4BF; 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Tue, 17 Mar 2026 16:20:29 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v13 RESEND 14/14] selftests: sud_test: Support aarch64 Date: Tue, 17 Mar 2026 16:20:20 +0800 Message-ID: <20260317082020.737779-15-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317082020.737779-1-ruanjinjie@huawei.com> References: <20260317082020.737779-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" From: kemal Support aarch64 to test "Syscall User Dispatch" with sud_test selftest testcase. Signed-off-by: kemal Reviewed-by: Yeoreum Yun --- tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c | 2 +- tools/testing/selftests/syscall_user_dispatch/sud_test.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c = b/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c index 073a03702ff5..6059abe75cb3 100644 --- a/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c +++ b/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c @@ -41,7 +41,7 @@ * out of the box, but don't enable them until they support syscall user * dispatch. */ -#if defined(__x86_64__) || defined(__i386__) +#if defined(__x86_64__) || defined(__i386__) || defined(__aarch64__) #define TEST_BLOCKED_RETURN #endif =20 diff --git a/tools/testing/selftests/syscall_user_dispatch/sud_test.c b/too= ls/testing/selftests/syscall_user_dispatch/sud_test.c index b855c6000287..3ffea2f4a66d 100644 --- a/tools/testing/selftests/syscall_user_dispatch/sud_test.c +++ b/tools/testing/selftests/syscall_user_dispatch/sud_test.c @@ -192,6 +192,10 @@ static void handle_sigsys(int sig, siginfo_t *info, vo= id *ucontext) ((ucontext_t *)ucontext)->uc_mcontext.__gregs[REG_A0] =3D ((ucontext_t *)ucontext)->uc_mcontext.__gregs[REG_A7]; #endif +#ifdef __aarch64__ + ((ucontext_t *)ucontext)->uc_mcontext.regs[0] =3D (unsigned int) + ((ucontext_t *)ucontext)->uc_mcontext.regs[8]; +#endif } =20 int setup_sigsys_handler(void) --=20 2.34.1