From nobody Tue Apr 7 02:55:52 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51E822D9796 for ; Tue, 17 Mar 2026 03:26:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773718008; cv=none; b=my3DXXf1Kq3MsLxPpEoWWoKCILKpnmXZwBHNlYwhsbRZ/hymgytI7LVE+iPmcyqoBN+M5u3p2eEaSjOjEjRleuumpxW3dn60ls70zO8C06GWcthiArCkN2FwCNvcXzx+E1y7hAbCj1e2DjesGYgjfQw5KZWOA3VR5yc9fn8cz10= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773718008; c=relaxed/simple; bh=HKFOu1fNblOcn/HFOdu48EyT+lBa2UuOd8Ya8wh5870=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sbrYM3aTIujV/QbJMX1wxq/n3afEA7Ne6HZiHnYqirFPhlgSv4q4z0LXJZ7DrExlBTJoK3j4Cz+0Igrm1Xt6vTthCKK+AW1wNu3Sgs1CCz1+4RVigsexZe6Gau9vGlbntuAnbK8ZfI8ctDU2RhjwPyCOGvYDGg0aHE6HAdXmbGw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=AAAnisiF; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=McacIj1p; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="AAAnisiF"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="McacIj1p" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62H293kq3124560 for ; Tue, 17 Mar 2026 03:26:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=g0+lG/T+afF 4ySmlryIDom0iKLYnuD7FP3qAhyNGYbE=; b=AAAnisiFj2zY5YrL3HKPnJJK/N7 2vH3oBAanY0B6iBl5Mnj4rU09pWMdtesDNyGNJhoDPO/e+rGpbw3+XuTPqJXm3Xk DxNmIftP3Cp2ngm38HzQ3Cc9pwvhNjfApjmhjlYX2370JKxdCYVJpnrkjDkMXkpQ vAUE5NSQYv2T54IIPAvcQyhlkigNXgDcv1reDZm/ypAFIKowlHqTpNnnp0LODkkQ 9wncZ/e9bjv80VZolW8G0bPOmRKLPZlDixYHZ0uZd0Y1GcyOnHw+uBkpZZEWIp3N L3HL/oKI3XSUuEfoX7HEtAl6zTUWcezLMUtoOa0HzI+XF3bGhhJqQ9CFSog== Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cxfsmk8xa-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Mar 2026 03:26:46 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-2bda35eab74so204523eec.0 for ; Mon, 16 Mar 2026 20:26:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773718006; x=1774322806; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g0+lG/T+afF4ySmlryIDom0iKLYnuD7FP3qAhyNGYbE=; b=McacIj1pE6quuTF18MXplcbQnm3olLiEISiGNZYdoJBWupkESrQZZctvrAqeqFxqzk hK1+Mz2NDMHu/b7pzlStDFyH3YZmTsSZv5oC2szAFo4qF9YXGfXHujxxVC/hUYNri0u4 KOm6hoNLVCRfO/BGFItTrn93QRHFAzxDgjmlpmz5pU3XK0JjWsyyhxTkaKsBa1gL0wSW hpwZeelwGrAdDrUV53SFgQCm9/VANHI4MwsYpCuOhcKTTPBZ4cR+X/corvih2eaIvnFS InJVw/spjxIIluUxHedk67PBIobYE1LJjiqNsbWChSWFsNY570zqaAeUKS1+EiL0KKko 6rkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773718006; x=1774322806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=g0+lG/T+afF4ySmlryIDom0iKLYnuD7FP3qAhyNGYbE=; b=cd9+/UleyFEoES0s9873IDVlCl1Vt41ckYPlCbEDCpqaTySKNCQxfGUgLwsDYJnqFo 8/ne7v6WNZ3KaH0oA4TfAlkw2ECJK9Wm4R3qgc3QSSGYu8HEet4YIAH1cMgQVpynh+0m 5xdEEuefNmj5/Qf61X/kIiu/LO7aOIXOv6ESI00ep8V3vw/4ERgwqIadadFaA7KK7ZUq xVqaemZjcRKfIrkjccjMY7Hsun5RB9bCiXDQGMp6VX1CYfd4hA6hawu0Zob+pAIrAw1m YW2Yg5sU46LkFAKTHGqy0qGXEhjrLvMS0hhGPQmCzRaOFsM6yKsIC9JQ7yh+4tbJpe2B gP0A== X-Forwarded-Encrypted: i=1; AJvYcCVS/gVLbLvJAipn/KWjO/L7nkPWVtoFMfPH7YyrjHl3RliwlVx/u7qIIVYRtnP4xCmvAxpKH9nuHjdembI=@vger.kernel.org X-Gm-Message-State: AOJu0YyTQ1030RXY3neKwX3412DnJnnCZ40F2WatQuUbis55f6kjicgl ROGQNFZkX12o1jVlZmVj7WBSDfu+5VlCupFbAbsrP3ilhoJaqK4i9bLx4jA2DElCqC08ZrMctGM UdGB5dj8JGxbQ2BEFodNLyuJPRGgR3PN72vVaJ3lchlFYX7HmodfxBlZL+P/mkI7zj3s= X-Gm-Gg: ATEYQzwJXuh4TGBq6LBsXSiHSuU6WUykauInpB8N3tji5cHp9Sou9uCGZVs7q+kKtna nW2cBQG1Dm/NXOMl0Cd/3oqe27Tndcp5xsLozndD83Tg0UO5St5e6tuyQyQApCoSeaA4WcX+j3q +jsfKIoOe5rurkZ2MwNPatc+P9GhEKTe4u5+zwYno+M/Bw9E2zAcAG/o74NpHk/Hql+BVtVITpH N4IVy6EPYlfa1dFrWpVwZf0kDk3314I4gGLpUSlBEcEF4T9yCs7uCVOYtIwzqohC/EQiJb5pSpl RngKQIu4AoxKtiBPUo027ogX3b8QDi72hDbi5I8YmrzNfygQkQLoLRycnjMmthPCIiQgy884np7 NEqYbchlU2UO10Rp1DcuCouWtXnjslwmp3/dZvO58iaaoHFvheRRrdKbuZRFNNYkg0PBc0O9154 Hg X-Received: by 2002:a05:7301:1001:b0:2be:b02b:1b3f with SMTP id 5a478bee46e88-2c0d51f2448mr704166eec.13.1773718005839; Mon, 16 Mar 2026 20:26:45 -0700 (PDT) X-Received: by 2002:a05:7301:1001:b0:2be:b02b:1b3f with SMTP id 5a478bee46e88-2c0d51f2448mr704157eec.13.1773718005213; Mon, 16 Mar 2026 20:26:45 -0700 (PDT) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2beab3ef844sm17445895eec.15.2026.03.16.20.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 20:26:44 -0700 (PDT) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, konrad.dybcio@oss.qualcomm.com, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, Rob Herring Subject: [PATCH v12 1/7] dt-bindings: arm: Add support for Qualcomm TGU trace Date: Mon, 16 Mar 2026 20:26:33 -0700 Message-Id: <20260317032639.2393221-2-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260317032639.2393221-1-songwei.chai@oss.qualcomm.com> References: <20260317032639.2393221-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE3MDAyNyBTYWx0ZWRfX5brjLLgH2g3N CWvSDTxwGntu72R2jL0zpg6XirIX/SwAEojgZxN08+QNsGLdeuizox1ybaOH6DBuKoAMVKl8x2v lVRwkt6vygkiDE1xh5umtGnQeWAErDbnxVK+to6JuwaFXRiHLvI/Z0u4IssjJiL79nkGwRXQZ3h MObomHW/O7aK8GyJXTqJKiSLmUxzWBhLhQjWisKmQw2cyqZx256lKUjk8Hwr52NZc/anXkEnNo9 SfWxrEzd7cTUqIGy/5Ju5VTTGTjwxThrczqecc7GN5ErkE829hk1rutznF1fQSTbJDxdWZDHMn5 EB5dHGMYk0F8QYIdXCG0HSyM0lwSo8ZVGJZdEKzn/zIWGH58R6Za4PpE0K+73yAgirbkSUM2GAk AnkXJI5o2FFNvbgk01NTiE6r2CXHrC63+RSeeou2sGUDwF+T92p4N7eH63zvnOKEd/clmR2V3UM tnrNd/DO1dWY3FHdRqQ== X-Proofpoint-GUID: x_yVa6yJgBofXxgH-zH053VaAee-QwTW X-Authority-Analysis: v=2.4 cv=V/hwEOni c=1 sm=1 tr=0 ts=69b8c9f6 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=N3VNWiZ0WD7Ir0aJMQYA:9 a=bBxd6f-gb0O0v-kibOvt:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: x_yVa6yJgBofXxgH-zH053VaAee-QwTW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_01,2026-03-16_06,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 clxscore=1015 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603170027 Content-Type: text/plain; charset="utf-8" The Trigger Generation Unit (TGU) is designed to detect patterns or sequences within a specific region of the System on Chip (SoC). Once configured and activated, it monitors sense inputs and can detect a pre-programmed state or sequence across clock cycles, subsequently producing a trigger. TGU configuration space offset table x-------------------------x | | | | | | Step configuration | | space layout | coresight management | x-------------x | registers | |---> | | | | | | reserve | | | | | | |-------------------------| | |-------------| | | | | priority[3] | | step[7] |<-- | |-------------| |-------------------------| | | | priority[2] | | | | | |-------------| | ... | |Steps region | | priority[1] | | | | | |-------------| |-------------------------| | | | priority[0] | | |<-- | |-------------| | step[0] |--------------------> | | |-------------------------| | condition | | | | | | control and status | x-------------x | space | | | x-------------------------x |Timer/Counter| | | x-------------x TGU Configuration in Hardware The TGU provides a step region for user configuration, similar to a flow chart. Each step region consists of three register clusters: 1.Priority Region: Sets the required signals with priority. 2.Condition Region: Defines specific requirements (e.g., signal A reaches three times) and the subsequent action once the requirement is met. 3.Timer/Counter (Optional): Provides timing or counting functionality. Add a new tgu.yaml file to describe the bindings required to define the TGU in the device trees. Reviewed-by: Rob Herring (Arm) Signed-off-by: Songwei Chai --- .../devicetree/bindings/arm/qcom,tgu.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,tgu.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,tgu.yaml b/Document= ation/devicetree/bindings/arm/qcom,tgu.yaml new file mode 100644 index 000000000000..76440f2497b9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,tgu.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,tgu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trigger Generation Unit - TGU + +description: | + The Trigger Generation Unit (TGU) is a Data Engine which can be utilized + to sense a plurality of signals and create a trigger into the CTI or + generate interrupts to processors. The TGU is like the trigger circuit + of a Logic Analyzer. The corresponding trigger logic can be realized by + configuring the conditions for each step after sensing the signal. + Once setup and enabled, it will observe sense inputs and based upon + the activity of those inputs, even over clock cycles, may detect a + preprogrammed state/sequence and then produce a trigger or interrupt. + + The primary use case of the TGU is to detect patterns or sequences on a + given set of signals within some region to identify the issue in time + once there is abnormal behavior in the subsystem. + +maintainers: + - Mao Jinlong + - Songwei Chai + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,tgu + required: + - compatible + +properties: + compatible: + items: + - const: qcom,tgu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + tgu@10b0e000 { + compatible =3D "qcom,tgu", "arm,primecell"; + reg =3D <0x10b0e000 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + }; +... --=20 2.34.1