From nobody Tue Apr 7 01:14:23 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC7F93A6B6E for ; Tue, 17 Mar 2026 10:24:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743075; cv=none; b=DIdDDqe1+gOC7OINI34SRGN5upn4oJMgVDIWrofu2IjAvK9ENDBhVKrqIeNuuHI5qTqgv8ddH+YUZm621m+9SFI/x+mupptmf0reBZIW8OHdKIgRAvmmMsOh73XVFegvtniVIFVmWEMeaTiiAdO86+/M/LFxcT7h8isvGp5P9Rw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743075; c=relaxed/simple; bh=GHZmXM5aeYs2tOJlVhdumoaqbQGSKeO1/pZkzO0/kP8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZynDqWBPLfpR06seIDjYCgEX6m9ARmzIi4k6ZxBL0yrywC66pitqKm6Lfz1ys8b8qYcARsAuvLEMAG0IX6Usxw6jUwnw2r1glRN7Q9qYvqPJE0j3E7WcqAno5igv1ItTDaWYjGUq2yNSseX0+zxbBjDnA41cddljbEzS6ukZZwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=vo3ID7tL; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="vo3ID7tL" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 6941DC55055; Tue, 17 Mar 2026 10:24:56 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6E7D95FC9A; Tue, 17 Mar 2026 10:24:32 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 550AD10450458; Tue, 17 Mar 2026 11:24:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743071; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Ec0kbPx+edwoqApwKlNsfKYC2JUdHu2CV9kwwUFOJtw=; b=vo3ID7tL65bSVLiFSYDKEvzPrXAoJKJjNr1TWvmprROuC5UJz9uGirrLnMI7lXSyU+m4/i vY3GCXYKvH49YF85+BVBaXI2AxEn0tuexxwUuiywySv5/MHfJel4X0+4+Jq/ZpkrM9b4pF LbwNuGC3xTizmoiVfSWuQK0E0uiO4/4QenN1VqDvqVf1rEFAvFMJV7UL/i10LPCL+EivZY w454Ah5DUgdn+bScI8N/XSzSS6FTU68+wPpSeio2oV3/COjZJcYc1+xYt2+MekhWm4e8Fa MDGP/K2RJhAPDl6WZzadEXm9bJSoqY+46mSrYbF5KKJNeVJNR4Zv+HvIa6PE2g== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:14 +0100 Subject: [PATCH v3 11/27] mtd: spi-nor: swp: Rename a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-11-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 "mask" is not very descriptive when we already manipulate two masks, and soon will manipulate three. Rename it "bp_mask" to align with the existing "tb_mask" and soon "cmp_mask". Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index af6e577d9b42..66f85826ba0d 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -57,9 +57,9 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, const u8 *sr, loff_ u64 *len) { u64 min_prot_len; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 bp, val =3D sr[0] & mask; + u8 bp, val =3D sr[0] & bp_mask; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -160,7 +160,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1] =3D {}, status_new[1] =3D {}; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; loff_t lock_len; @@ -199,7 +199,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) lock_len =3D ofs + len; =20 if (lock_len =3D=3D nor->params->size) { - val =3D mask; + val =3D bp_mask; } else { min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; @@ -208,15 +208,15 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) val =3D (val & ~SR_BP3) | SR_BP3_BIT6; =20 - if (val & ~mask) + if (val & ~bp_mask) return -EINVAL; =20 /* Don't "lock" with no region! */ - if (!(val & mask)) + if (!(val & bp_mask)) return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; =20 /* * Disallow further writes if WP# pin is neither left floating nor @@ -234,7 +234,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) return 0; =20 /* Only modify protection if it will not unlock other areas */ - if ((status_new[0] & mask) < (status_old[0] & mask)) + if ((status_new[0] & bp_mask) < (status_old[0] & bp_mask)) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); @@ -250,7 +250,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1], status_new[1]; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; loff_t lock_len; @@ -306,11 +306,11 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) val =3D (val & ~SR_BP3) | SR_BP3_BIT6; =20 /* Some power-of-two sizes may not be supported */ - if (val & ~mask) + if (val & ~bp_mask) return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; =20 /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) @@ -324,7 +324,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) return 0; =20 /* Only modify protection if it will not lock other areas */ - if ((status_new[0] & mask) > (status_old[0] & mask)) + if ((status_new[0] & bp_mask) > (status_old[0] & bp_mask)) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); --=20 2.51.1