From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B92139FCAE; Tue, 17 Mar 2026 10:24:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743058; cv=none; b=Clf+T168I0C45Hg7LPARfxwtdKswvVISceHgYF9m/7jRVw2FZTHbl8cnPMaIbFHHMvgcvH2xauvmD9c1LfhxOH03nF4g9SHr5dOgPt36X3dbqnUyGhaIodaYjjNbLt9ixOJDZBgvNX5Fx2gxXy04vKlTNIDCr+OgsW4x/Ht3dV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743058; c=relaxed/simple; bh=fatzP569vqfw/xyBsas/+0N3B+R17VOm20tc23xiw4M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D1jGsGNT0/wD/xcMuO00HTd2UC1wuhHJA42UVKSRPHneTtwu2k655wICv3vhiXE/Gb9YfITwaiT6a0K88cIxZlXKB2OCPtSFoy30WKTi3LbAgQ8qMmUDAuLa9f2BMgaatzOjfRyr9wmiBtTZ3PlDnRfLFaYPyBn0q8O2Fb+LlLQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=bTUhlRmE; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="bTUhlRmE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 798874E42629; Tue, 17 Mar 2026 10:24:15 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 4E4995FC9A; Tue, 17 Mar 2026 10:24:15 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 38142104503AE; Tue, 17 Mar 2026 11:24:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743054; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=7UGHB4CnkC5yHvpQ1KlMte4F9RtOgCrxhLW069LNgLo=; b=bTUhlRmEA9eD/lL9k3ctzWWtTzNEBpFO4+LerBE3plx/WSl26GYBjk8WtQ1sDmKIzitWxv 0UNC8aPSjfBfoG7eFmdoLjVOskYR1SfufuS8r8/DGfw+0Sd6JyvDzVe47ZzZtgcmg2J4tU 82bhV2oxGWcgRPFwY5U2Vyfj3KVNeZxOO1yCjIHWRMxlbde90QhqOvG1WdFAbAPRWRElww WNCf2rzUCJk2K776cjVpuq34dWhyrc+HN0qbe3moZKW700cJmMlM2hr0jfqn65BnwPfkZs dhmYrVhfDP+6O4G+3+xsAgZEaBXfCigr/oKTJy0U/SjRhpfffkn51LgTpEnzTg== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:04 +0100 Subject: [PATCH v3 01/27] mtd: spi-nor: Drop duplicate Kconfig dependency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-1-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 I do not think the MTD dependency is needed twice. This is likely a duplicate coming from a former rebase when the spi-nor core got cleaned up a while ago. Remove the extra line. Fixes: b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c") Signed-off-by: Miquel Raynal Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index 24cd25de2b8b..fd05a24d64a9 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig MTD_SPI_NOR tristate "SPI NOR device support" - depends on MTD depends on MTD && SPI_MASTER select SPI_MEM help --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BCE83A5443 for ; Tue, 17 Mar 2026 10:24:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743059; cv=none; b=gBsU0HplKwus+m+bofUD87gphicIUi/ma1zt81GiAiREhBUYp4j9ttaEvLdoDKgW5SPeLrH92cyww3JESW4kl/7VBkQTXL5iWRwEXfMAjz6cpExW3RuU/eA9phv/ILosPum6muFRk9lzwJUz7yV+CAOE6kUZW7ef4cnoJ4w470Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743059; c=relaxed/simple; bh=pDZb0epMDwk6MJdaiEIqcDJe8cxs9bBHkhWkqeoeHyE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PPO1abJFElQzu2t1LkbhXC6bDxxtFPFjtFWTyrk2GodaZD+C/ZiqAIoGy9a2wGjDjzrCzqqv9fh16RcP8wAcZtB5n8V3LVEDfWsPtVW5lWlFNkC8CkxvEIqSlqxczgEDklnWpSYNUnNix/95LZDAL7qoR0HMwonnt4D+7wfwxio= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=REG75wJr; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="REG75wJr" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 57F7E1A2E5D; Tue, 17 Mar 2026 10:24:17 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2865C5FC9A; Tue, 17 Mar 2026 10:24:17 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C7B071045044E; Tue, 17 Mar 2026 11:24:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743056; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=stZFrqO/Xzy7EKE+3DmnORMCs6+d8LeG2HLgrVddfK8=; b=REG75wJrdnrSUys1HmGfgvjtUIaQ6yoQ2IVEN4Gc6xbRsqOBDltE+bKOz6Jpwa5bRs7yb5 Sabt2T1OeR3MJ60Muo54fBvsoWvkqIe8vE9M3T6q9cplXbTd2D4gV7IhR/sy4TwCyMdHBv BzzJ11Es8Xi+6pwqEYMzjCIrJT4RuCV9S6PgRON04eCdsr38spvdId6KBA54zTPQMXHDzz Rh7bs8PApT6np//vDxKrhaPWFVQAZs+bnPOBNdePmFlJ41TvbXEbAL1md7uXxmV+5qOQaH xhh14SGnMfDnfoXt03ZBRHVgmATkNYeHoNoHG/ldAALVCa4k40PxWgoSiPyn6g== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:05 +0100 Subject: [PATCH v3 02/27] mtd: spi-nor: debugfs: Fix the flags list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-2-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 As mentioned above the spi_nor_option_flags enumeration in core.h, this list should be kept in sync with the one in the core. Add the missing flag. Fixes: 6a42bc97ccda ("mtd: spi-nor: core: Allow specifying the byte order i= n Octal DTR mode") Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index fa6956144d2e..d700e0b27182 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -28,6 +28,7 @@ static const char *const snor_f_names[] =3D { SNOR_F_NAME(RWW), SNOR_F_NAME(ECC), SNOR_F_NAME(NO_WP), + SNOR_F_NAME(SWAP16), }; #undef SNOR_F_NAME =20 --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26EEF3A3E97 for ; Tue, 17 Mar 2026 10:24:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743061; cv=none; b=Y0rh8Acz+K3k4ir5SNvIl9g+FW5TVejAoep6j+d/i3mJmcskIYFmkSja0vrdSAuZEbtpJEd39M12OCymcO3qgI2LiLiPjxz3wEePOqg7dFdVR4Yl/RhW4MTtdaok/KGoVZ7QAJxuejOKGEb/kcuMeydnTdaTauYOb0V6EHB76NA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743061; c=relaxed/simple; bh=PGW28jxV6NLfJchRFgJZv966a2uFw+0TVJ+29FoFq50=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YVjA5F3ZkjIdNRbUneDx9ZxuSsOKLdeAEhGnJb0Mqr9mgITTca7FJAyaJ4afcz4fmtmvqXvpbRrRrNao7uqHoa45KFqfsdgruP1WPRPB2TYlv9Ln5A075FetoQKOUZEXxfI56itm6Y4mNO9utACc51bauPgOHJfHSs1rraydTWU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=S1perSMX; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="S1perSMX" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id DB10F4E42629; Tue, 17 Mar 2026 10:24:18 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B1EAB5FC9A; Tue, 17 Mar 2026 10:24:18 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9038C104503A6; Tue, 17 Mar 2026 11:24:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743057; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=oH2f1X8ubdaJfjO8jMVN/SnoqiCo9otBh9JA0zOAQYE=; b=S1perSMXvgTj9BcAX/5aMWvU0brGtGre/OKB/h3uYO1cwci2caT1nEPs2uu6P1FTRDE9jN FTVz6ARqrxbDFf+MJbnLC+h6HBKaJddf7n5wFtF+JFsTo+JYuykClwrpEBH47LkDXrtqJc F3FwaDmveGaR2lOS0VsdgSxhkU3K2yxdyEjAAA69SuNRlNrYv7BscK76KsRoTYv38Lda5f lPS0P0n8pGCIIvL9bywv0WVzzVfyRl0R7ob3lOanM7dA1V3pG75LXkhdXENgMX3P2zCg0Z DdpcnaEYZQgwkYtvYssogg9uwyNPOiD8rn9BNCMepT1rYOmGnG5ElAW50v9YXw== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:06 +0100 Subject: [PATCH v3 03/27] mtd: spi-nor: swp: Improve locking user experience Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-3-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal , stable@kernel.org X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In the case of the first block being locked (or the few first blocks), if the user want to fully unlock the device it has two possibilities: - either it asks to unlock the entire device, and this works; - or it asks to unlock just the block(s) that are currently locked, which fails. It fails because the conditions "can_be_top" and "can_be_bottom" are true. Indeed, in this case, we unlock everything, so the TB bit does not matter. However in the current implementation, use_top would be true (as this is the favourite option) and lock_len, which in practice should be reduced down to 0, is set to "nor->params->size - (ofs + len)" which is a positive number. This is wrong. An easy way is to simply add an extra condition. In the unlock() path, if we can achieve the same result from both sides, it means we unlock everything and lock_len must simply be 0. A comment is added to clarify that logic. Fixes: 3dd8012a8eeb ("mtd: spi-nor: add TB (Top/Bottom) protect support") Cc: stable@kernel.org Signed-off-by: Miquel Raynal Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/swp.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 9b07f83aeac7..1d50db1ef1a0 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -280,8 +280,15 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff= _t ofs, u64 len) /* Prefer top, if both are valid */ use_top =3D can_be_top; =20 - /* lock_len: length of region that should remain locked */ - if (use_top) + /* + * lock_len: length of region that should remain locked. + * + * When can_be_top and can_be_bottom booleans are true, both adjacent + * regions are unlocked, thus the entire flash can be unlocked. + */ + if (can_be_top && can_be_bottom) + lock_len =3D 0; + else if (use_top) lock_len =3D nor->params->size - (ofs + len); else lock_len =3D ofs; --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0214C3A5E9E for ; Tue, 17 Mar 2026 10:24:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743063; cv=none; b=MizlvnMCjIPX+68s1jPFl9Jif21ODmqr+0pHrVWpWB1sZDUYakllc5NJTSiFvM/CdEWLTT0YwmtlNpeCoojEy/+pdNW2RXR56vKItqVGAOMyqeRHdrFHeO/j1AWL5gmtGLobOMNs3UNuQ0vG9iipqTWqVQ4F3MxSiP/d2OGHz+A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743063; c=relaxed/simple; bh=fzE7Kbk6Kb/cBeCT1q00i3uy0oSMCu925oa9vdXVJ6o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lkAbZ0BjYS17FpiizM2UYxj/Sz8cmqVyX6skr8LxDLzctFmKI9aR17DKzpoMAWHyQOp49OjhPjP8hF78IUsA2lVQMFJ3wy62m2vDtdAT4WU2SoZ05hhz88du+uqSTqkL6Hgi8VCO862xhf01Gal/clAj5thOb9GtGE5NF5M+194= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=oAP6OoM4; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="oAP6OoM4" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id A66171A2E5D; Tue, 17 Mar 2026 10:24:20 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 795585FC9A; Tue, 17 Mar 2026 10:24:20 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4310C104503AE; Tue, 17 Mar 2026 11:24:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743059; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=hXc+5kjs1EF92jBqcrTSRSedlWRYjsDeVRr6sDpavVg=; b=oAP6OoM4wnXZe8QPqP/R2D2+8ULChbXgKjwQLTh4fQQSGl4WPp9glOl3sYE3wNmf4CDOHV FU6oITksTfbjkV3bqST9cM55oo/EqYrk8A73RYUyg+c1cTT+Xkm4gWfLkk3mNq3Gd6RCv6 a0xuZ5bZCU5cBQw+9xc96f5NI7/kWt7UslhCD+0pxSMR8LSVfKut3KZw01FqAn28nVVvyX nysT5QgOgGXfqgYO3z5O9fOmEd229MylexMywTwvNjEt9QuxYARXsLFMvx8DmoQEbCK74g Y2RuINDi1BEV5NDe3d7KP+Np2FFLsdCoXeT3ReThrte7sIFJb6FgF8PY4A+L0A== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:07 +0100 Subject: [PATCH v3 04/27] mtd: spi-nor: Improve opcodes documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-4-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 There are two status registers, named 1 and 2. The current wording is misleading as "1" may refer to the status register ID as well as the number of bytes required (which, in this case can be 1 or 2). Clarify the comments by aligning them on the same pattern: "{read,write} status {1,2} register" Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- include/linux/mtd/spi-nor.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index cdcfe0fd2e7d..90a0cf583512 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -21,8 +21,8 @@ /* Flash opcodes. */ #define SPINOR_OP_WRDI 0x04 /* Write disable */ #define SPINOR_OP_WREN 0x06 /* Write enable */ -#define SPINOR_OP_RDSR 0x05 /* Read status register */ -#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ +#define SPINOR_OP_RDSR 0x05 /* Read status register 1 */ +#define SPINOR_OP_WRSR 0x01 /* Write status register 1 */ #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACB4C3A6EE0 for ; Tue, 17 Mar 2026 10:24:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743064; cv=none; b=QJeBZKcOr/3UN2faUJi44k02RqcbY1b/5a1OjWqjnwy5f5e/+XnmMCJoJ/Qdq6nH4c6vl31INqpkjiq0IDv7350qXGut5lisgyK6Zy2NUJrmzKFpvU+xLFrK7JNd028A2sEMfmqOF9XGmyQUIrUvib09uZLKGKVUVaxoCS4BZ4s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743064; c=relaxed/simple; bh=0srJ1s65smP4KOpLWZGyK+ITZa7dJa5sLpiyMQk/z9I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k3lBgpipHE/gPwcmlog5X+4G5p5DDoSoA96a0ptNiXKn0y0JROOF4JGRLQSuF05VdDbjFXcndhCkvj22EzlMrBiokw/dClFgu5L3ClqTDmxdqOp/KLaNxZPKBm6rPVK8X4NniA66C6Znu2ANcijccRgggxGA3hR43oLFkpCCMeM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=VON7bPAE; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="VON7bPAE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 69EA71A2D73; Tue, 17 Mar 2026 10:24:22 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 3A1985FC9A; Tue, 17 Mar 2026 10:24:22 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F0B8B10450450; Tue, 17 Mar 2026 11:24:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743061; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=rre/i4KjHYI+91ZaQYrTCZUTDkibP+vKxwiQw3sQxfU=; b=VON7bPAEZCIpQWCqqGVDft9kNNyuw0K+FEtWRCGExdnb2KMEz9Fhy+WRbzUGOWlfhsnY9h T1OzS1kdjRaF7vOMib39VJFmDyQ100bxLs3WzAFpSGu044GehE/riOK0Jg3xfVKId829nj elf1LUWuOZyXHXM+ZNCa0ILA1zO6FIYeWXWhvGrBcPeslMhV3F6aiXcvvDa403+oeXHHEa sWTTqGQldbwUq2Kzu1hmeSKZTBfSymFHJIiY7dU+rp4FBNvEu0za0PPiYq7v/+x/6rJA9f U3ERQbLC5MVZdccmm7hDWUAN2D8lYapE+x32fQ+L0GZQNYVcxgjCtDHx0WjeUQ== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:08 +0100 Subject: [PATCH v3 05/27] mtd: spi-nor: debugfs: Align variable access with the rest of the file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-5-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The "params" variable is used everywhere else, align this particular line of the file to use "params" directly rather than the "nor" pointer. Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index d700e0b27182..69830ad43990 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -139,7 +139,7 @@ static int spi_nor_params_show(struct seq_file *s, void= *data) =20 if (!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { string_get_size(params->size, 1, STRING_UNITS_2, buf, sizeof(buf)); - seq_printf(s, " %02x (%s)\n", nor->params->die_erase_opcode, buf); + seq_printf(s, " %02x (%s)\n", params->die_erase_opcode, buf); } =20 seq_puts(s, "\nsector map\n"); --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BC163A6F0F; Tue, 17 Mar 2026 10:24:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743066; cv=none; b=oi4yBfZeNW47fBP619hScO7RWKXpVhavyNabBclJJAPU7mkp7jwW2UHIkvAR1SKNF4MNSxe5211ltOpYwK0b8Zuo+ajVDGyl2vIwXStT3596LJCc8RbjI7fdnF7QPJHdleFeIgL9o2ZTYy0N1ycmpxwkyC+YSrGnxczd82Uj4Kc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743066; c=relaxed/simple; bh=1Yo/fOaQdnIL35rS5CVUoPBadwI1OnlcymoKxp3EHp0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=vEXkH1+2w5TwTFswkC/Zy/SxN0x17U8OKSbogtz5kT2wiEJbuoZ7CtDHqaUHRUpqew3g9WpEs7XDE24fka/6Lq9FXBpsS68nsAATajKGlbJzfICr7dV+ObLBMAquk0i2T0uiEb9pLVZxrEbvotxOfc7YM1otDNo3qN3hmzspBHY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=TTJ+RGk6; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="TTJ+RGk6" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 484F81A2E5D; Tue, 17 Mar 2026 10:24:24 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 1E7965FC9A; Tue, 17 Mar 2026 10:24:24 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EAA1910450451; Tue, 17 Mar 2026 11:24:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743063; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=ThROAC3RdaD7Vj2qP5V2r7cJLBpFb3GyBt6p16RAuXc=; b=TTJ+RGk6bpuPH+uFZCufkC05LVPDVqor5WxDpvABfXFw/XpaX02IpkMIoxgysl+E8yQimO 1/4r+HFtGXqY69udyKv3+kBvLfCrYgFKENJDo2KXNKwYEI49j/HtvO7YfneE2E9DsT7oG+ pAQ7v2wctMaFwLT1Iru4/NPOhqyvKX9mQ1X07SypAitxUGqs4BNI8g52MUZQlW9UnbNxvZ phg3sassBtYvpZw1jJT+8j6WbWxRAA2lTtqrgOM/vgnhG5uPgrSvKb6pDoK8qxO1jk+G1o Ibg5LSQh2254UXYCGDLXUMPArmfSEepeVfGoBoIIqqVXOJxevJqaScMj/AksOQ== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:09 +0100 Subject: [PATCH v3 06/27] mtd: spi-nor: debugfs: Enhance output Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-6-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Align the number of dashes to the bigger column width (the title in this case) to make the output more pleasant and aligned with what is done in the "params" file output. Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index 69830ad43990..d0191eb9f879 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -144,7 +144,7 @@ static int spi_nor_params_show(struct seq_file *s, void= *data) =20 seq_puts(s, "\nsector map\n"); seq_puts(s, " region (in hex) | erase mask | overlaid\n"); - seq_puts(s, " ------------------+------------+----------\n"); + seq_puts(s, " ------------------+------------+---------\n"); for (i =3D 0; i < erase_map->n_regions; i++) { u64 start =3D region[i].offset; u64 end =3D start + region[i].size - 1; --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F0AE3A7585 for ; Tue, 17 Mar 2026 10:24:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743068; cv=none; b=nbXZbIXbCb2ej7Urce1BonUEEmECK0oW5gYdPIBIRd0OrO+CiWc5DRahhad27+vpb7c7v7r4fxUifrsEwqG8Da+Sba/cOO90tUjxo8ISi6lCVJ1Dj3wKu8ODcfSFgou1DXS4pFp/zJee3gDzvU2in1jSItBge4KDHLb9IKJr7B4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743068; c=relaxed/simple; bh=m8EezPdj5/zLpTZs6LAb34kiI2GknFW1YMmMypIYx5U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DivnCs41cswigrQ0VUutrwufRTRCeVfUMYCxcuZ7gqoBFUqqIUwa5uyEKXkEOJVIupQYHyxipAQ2BeObA+gaB19xNjKSaXwTxCz+fe1wD1hrdVIJVPLatH2JvLgUU/izHKA1GhaeITPUdCxxo3tM8N9L3thiPLnGMipUFI2jJew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=oOGaC2i9; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="oOGaC2i9" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id DE8BB4E4263E; Tue, 17 Mar 2026 10:24:25 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id AF1145FC9A; Tue, 17 Mar 2026 10:24:25 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 95C80104503A6; Tue, 17 Mar 2026 11:24:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743064; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=uBSfAslupKiDUjYa9VdOz+tUE+1u7aYrr2OFADafudU=; b=oOGaC2i9lLEU64q+oZ0r2QGoz4idF7IPxDdsm3W4fLhv+7mnI+EUblWRysxMQg/Aqdryyv MlkyUFxKs+avwRfmAaHynkoVoqQxzC9/g3zWQtBP0D9jvYL0rTnWu0K79vhVckeMbRIo2X x/xcd57dsca5KaQirVOm/bv7flu3vbomsgBkWt5r9+Lhkxn9m1Qy8Vpx4gI3f06Uibv5Xn VPIXWqQoAyROOv05XR7Eup+PD5AOdWV9c7R5K5NoRfQLkTPLyNJBzQkjGN5GVj4aVrGHF1 sQJgfU4A++wePdwIQKHBu+/aYaelsdg7Fr5/JL3C6HWxmUiOKQ8TSwQicz2V7g== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:10 +0100 Subject: [PATCH v3 07/27] mtd: spi-nor: swp: Explain the MEMLOCK ioctl implementation behaviour Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-7-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add comments about how these requests are actually handled in the SPI NOR core. Their behaviour was not entirely clear to me at first, and explaining them in plain English sounds the way to go. Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 1d50db1ef1a0..64a917543928 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -346,6 +346,14 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, l= off_t ofs, u64 len) return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]); } =20 +/* + * These ioctls behave according to the following rules: + * ->lock(): Never locks more than what is requested, ie. may lock less + * ->unlock(): Never unlocks more than what is requested, ie. may unlock l= ess + * -is_locked(): Checks if the region is *fully* locked, returns false oth= erwise. + * This feeback may be misleading because users may get an "= unlocked" + * status even though a subpart of the region is effectively= locked. + */ static const struct spi_nor_locking_ops spi_nor_sr_locking_ops =3D { .lock =3D spi_nor_sr_lock, .unlock =3D spi_nor_sr_unlock, --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8210A3A7842; Tue, 17 Mar 2026 10:24:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743070; cv=none; b=K3i0VvEr3hjDQtwUggUXLFrTLZPSlHDLZGICG65yyEDYoGzXLPHuCXP3zVXihyEyCijCt72DuUakJnsO7pA5YpgHHWj4Fb4oDfnKfCLeJY+pa4hB8wi/MD55xf2LtaBxuoUPxsvaUJd8FxkS8eJpS5251JOyIaZAHxDUdGwELDM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743070; c=relaxed/simple; bh=iCfiMsUjEbvsR4lM+7YoHewMae65PTUZGwPNuWcvBuc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=m6XqUQiQbm9YN/WmWtmPOa+G2FJKX1v9dLOyk/vPhqbrG1ATtNSy7a0hioWlKwb9G0Lke6KFpNcNn2d3ZU7MxJmuesV/a0u3q9FxmmNyNI5ZhHZYmx2ak2WFjK8BIPqHpRE/XuiD1S3UIWGKrgGjjmYbHMps3PJGEg7ZGbpi/ec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=aKDR/eCH; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="aKDR/eCH" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 2AABBC5505A; Tue, 17 Mar 2026 10:24:51 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2F2EE5FC9A; Tue, 17 Mar 2026 10:24:27 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 318B010450453; Tue, 17 Mar 2026 11:24:25 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743066; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=KPr75/L7Q2MSPflmaco7Z/uPl6GqRaTpWsWBClHqZT8=; b=aKDR/eCHncmkAJZvKx0YEaEnKk8we87xPMAxoQjzi3jsqrWzgSRr6gJHsTlB9OHfR11Lbp FKMLvOcvxEfeDXSJ7hXtcgyOALT1oC0E4kHkbbzUhFAW7sMfBazUYfI9Z9MYU7MZwJJX7y GCqDOe+BEUTpm5hGuFqDzzTHMcxW8FuIbYEusInoMT5xx68teNGYc0j8hRF/gzTcK5Hbs4 mjCX6NhXvF5Ikkd2/o10xNYgtlTf/Gk+DLopDY+52ERuMLMSy1Non44tmjFhPIFGSoJ5wx 5IcC9GpkN5AsSpqVsZJXHSSJ8p7yoK7ZNfi0PiFnbhoeZ+ZPvgXi9Q9iWBpIfw== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:11 +0100 Subject: [PATCH v3 08/27] mtd: spi-nor: swp: Clarify a comment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-8-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The comment states that some power of two sizes are not supported. This is very device dependent (based on the size), so modulate a bit the sentence to make it more accurate. Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 64a917543928..246f6d5ca8dd 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -303,7 +303,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) val =3D (val & ~SR_BP3) | SR_BP3_BIT6; =20 - /* Some power-of-two sizes are not supported */ + /* Some power-of-two sizes may not be supported */ if (val & ~mask) return -EINVAL; } --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D98E3A7F6F for ; Tue, 17 Mar 2026 10:24:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743071; cv=none; b=DbaqhOgpo4Kz2n+U5DEQR4cOO3mMcQxMQRcYXTPcxWSW5yJHoFlmWN30DZCmxqwGaYsXGQLfMtNfqOWnXbRWs+Lfe6QuU2SMH/XfFgr5zx1oiPvo0kqcoFMcqhAbaQ1LMp5b24Oz2OPXCMAeFXjp/TPkfB+AfVGSx0AmlirN57o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743071; c=relaxed/simple; bh=m/zjBLZFf/xGAvmLJxp3+X4gdRRR5lsHphDGIp4ntMY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ET7rpUJAgtP54LDCsgke4X4KU1J9jozKB4eSJ5oLM3lT9TDqkif3GTu1NX0mgSzG/j1JQ2ic4mv52YUP67Bl69dLh0aSpON2Rxj0AAhoO5RRBpviBcm5Y0IjKdEC4mYKMec7fKK9b9aE+zoAQCamsAATU2iCVFl2NXiRq547eKg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=04n5juGV; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="04n5juGV" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 2DA0D4E425F5; Tue, 17 Mar 2026 10:24:29 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0412F5FC9A; Tue, 17 Mar 2026 10:24:29 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A76EF1045044E; Tue, 17 Mar 2026 11:24:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743068; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=cLbxiL+2EHw7lYTQVAB4LC1S2WgQViU5gpSnkOCqrtA=; b=04n5juGV1pRxsuXPnzqhRJ+6UKjBddrZ48uP3VbrpebKtd5V5Msk0FD1uYWEvOsObVydQu W6tHPnPAizsy4meZKvEB1wE0dWJpXKDYe7MNxJvGgdEilOHl0r3powNu1kw0il0urChIAr teG4PBr2kQU7gL5QnSWceNYUIw0K2svJW7Ig6giLxZHU/mzYJMMW8HPaLzGsxW+cRyHFcT 1F0J/iYVRp6OkCl8w1Z5eox9ekMyq1jqsZHxOFoWbj6/YNcNaV6kk/214ygNz7S0is7NzH FAuTt0Adhe8h7TY/0K/7NSe8onf3PXtgrG1TOJlRJNGoRQ+OpZ9/mtBz0/yNpA== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:12 +0100 Subject: [PATCH v3 09/27] mtd: spi-nor: swp: Use a pointer for SR instead of a single byte Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-9-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 At this stage, the Status Register is most often seen as a single byte. This is subject to change when we will need to read the CMP bit which is located in the Control Register (kind of secondary status register). Both will need to be carried. Change a few prototypes to carry a u8 pointer. This way it also makes it very clear where we access the first register, and where we will access the second. There is no functional change. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 48 ++++++++++++++++++++++++-------------------= ---- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 246f6d5ca8dd..af6e577d9b42 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -53,13 +53,13 @@ static u64 spi_nor_get_min_prot_length_sr(struct spi_no= r *nor) return sector_size; } =20 -static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t= *ofs, +static void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr,= loff_t *ofs, u64 *len) { u64 min_prot_len; u8 mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 bp, val =3D sr & mask; + u8 bp, val =3D sr[0] & mask; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -79,7 +79,7 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, u8 sr, loff_t *ofs, if (*len > nor->params->size) *len =3D nor->params->size; =20 - if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask) + if (nor->flags & SNOR_F_HAS_SR_TB && sr[0] & tb_mask) *ofs =3D 0; else *ofs =3D nor->params->size - *len; @@ -90,7 +90,7 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, u8 sr, loff_t *ofs, * (if @locked is false); false otherwise. */ static bool spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, - u64 len, u8 sr, bool locked) + u64 len, const u8 *sr, bool locked) { loff_t lock_offs, lock_offs_max, offs_max; u64 lock_len; @@ -111,13 +111,13 @@ static bool spi_nor_check_lock_status_sr(struct spi_n= or *nor, loff_t ofs, return (ofs >=3D lock_offs_max) || (offs_max <=3D lock_offs); } =20 -static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len,= u8 sr) +static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len,= const u8 *sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true); } =20 static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, u64 le= n, - u8 sr) + const u8 *sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false); } @@ -158,7 +158,8 @@ static bool spi_nor_is_unlocked_sr(struct spi_nor *nor,= loff_t ofs, u64 len, static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len) { u64 min_prot_len; - int ret, status_old, status_new; + int ret; + u8 status_old[1] =3D {}, status_new[1] =3D {}; u8 mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; @@ -170,7 +171,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) if (ret) return ret; =20 - status_old =3D nor->bouncebuf[0]; + status_old[0] =3D nor->bouncebuf[0]; =20 /* If nothing in our range is unlocked, we don't need to do anything */ if (spi_nor_is_locked_sr(nor, ofs, len, status_old)) @@ -215,7 +216,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) return -EINVAL; } =20 - status_new =3D (status_old & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; =20 /* * Disallow further writes if WP# pin is neither left floating nor @@ -223,20 +224,20 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) * WP# pin hard strapped to GND can be a valid use case. */ if (!(nor->flags & SNOR_F_NO_WP)) - status_new |=3D SR_SRWD; + status_new[0] |=3D SR_SRWD; =20 if (!use_top) - status_new |=3D tb_mask; + status_new[0] |=3D tb_mask; =20 /* Don't bother if they're the same */ - if (status_new =3D=3D status_old) + if (status_new[0] =3D=3D status_old[0]) return 0; =20 /* Only modify protection if it will not unlock other areas */ - if ((status_new & mask) < (status_old & mask)) + if ((status_new[0] & mask) < (status_old[0] & mask)) return -EINVAL; =20 - return spi_nor_write_sr_and_check(nor, status_new); + return spi_nor_write_sr_and_check(nor, status_new[0]); } =20 /* @@ -247,7 +248,8 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { u64 min_prot_len; - int ret, status_old, status_new; + int ret; + u8 status_old[1], status_new[1]; u8 mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; @@ -259,7 +261,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) if (ret) return ret; =20 - status_old =3D nor->bouncebuf[0]; + status_old[0] =3D nor->bouncebuf[0]; =20 /* If nothing in our range is locked, we don't need to do anything */ if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old)) @@ -308,24 +310,24 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) return -EINVAL; } =20 - status_new =3D (status_old & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; =20 /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) - status_new &=3D ~SR_SRWD; + status_new[0] &=3D ~SR_SRWD; =20 if (!use_top) - status_new |=3D tb_mask; + status_new[0] |=3D tb_mask; =20 /* Don't bother if they're the same */ - if (status_new =3D=3D status_old) + if (status_new[0] =3D=3D status_old[0]) return 0; =20 /* Only modify protection if it will not lock other areas */ - if ((status_new & mask) > (status_old & mask)) + if ((status_new[0] & mask) > (status_old[0] & mask)) return -EINVAL; =20 - return spi_nor_write_sr_and_check(nor, status_new); + return spi_nor_write_sr_and_check(nor, status_new[0]); } =20 /* @@ -343,7 +345,7 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, lo= ff_t ofs, u64 len) if (ret) return ret; =20 - return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]); + return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf); } =20 /* --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CE4B3A641A; Tue, 17 Mar 2026 10:24:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743073; cv=none; b=gh3dL3xFuHp6a0osDnIhjDCteoVQJC+8TuK/IZ/mob1huPVPW1LIS6TMU7QIjANm3BzVa6Oexd0zt8XUIdM1Qhaw6NDFRbenZDanOIh8j39/xuYws5/Od+fZ09VIueHsc50IwCL+KXzcnvz6SyYBhFjav9B1e53rZQ/iLm6M1NE= ARC-Message-Signature: i=1; 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Tue, 17 Mar 2026 10:24:54 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id DAE7A5FC9A; Tue, 17 Mar 2026 10:24:30 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 83FD210450456; Tue, 17 Mar 2026 11:24:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743069; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Y7gkrdgrcQoHFqnHR5pOMxnMUTl2bLc8Wyopo7eXDiI=; b=fC/Q1F/8MKxIz8xrdtw8wBMI9OP+3iX+dGHXTk0nnGG73dK8yPNRsXkZt4zITcDX9HccT8 aFlbWy9dfgCMYvgoYhAuHHVI4mR5umfeW7y7GVA5uAGjYnN9S0wvYomOHPj4OwwZ3L4Yx/ 6EyJeAjWndhlbJDiDar98ORT3hMk/cPF2auCAE2kNYbOSJJnbPSkLELL0KYoYHMfhpM+mo RNWJw4x6RbrVak7GPnDQ2sbu2zfD4TIGemwmwIkRkUM2CUIsSzk7Jip3TEipUXoksOvCmK L7t3ZabgKg19vGLpQUbK28rQDWqJrOMa9retcuGbaFmflg/bcY9mzqjmYikcbA== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:13 +0100 Subject: [PATCH v3 10/27] mtd: spi-nor: swp: Create a helper that writes SR, CR and checks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-10-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 There are many helpers already to either read and/or write SR and/or CR, as well as sometimes check the returned values. In order to be able to switch from a 1 byte status register to a 2 bytes status register while keeping the same level of verification, let's introduce a new helper that writes them both (atomically) and then reads them back (separated) to compare the values. In case 2 bytes registers are not supported, we still have the usual fallback available in the helper being exported to the rest of the core. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/core.c | 65 ++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 66 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 4ba5943cdd2f..1a31266fde1a 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -976,6 +976,54 @@ int spi_nor_write_16bit_cr_and_check(struct spi_nor *n= or, u8 cr) return 0; } =20 +/** + * spi_nor_write_16bit_sr_cr_and_check() - Write the Status Register 1 and= the + * Configuration Register in one shot. Ensure that the bytes written in bo= th + * registers match the received value. + * @nor: pointer to a 'struct spi_nor'. + * @regs: two-byte array with values to be written to the status and + * configuration registers. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_16bit_sr_cr_and_check(struct spi_nor *nor, const = u8 *regs) +{ + u8 written_regs[2]; + int ret; + + written_regs[0] =3D regs[0]; + written_regs[1] =3D regs[1]; + nor->bouncebuf[0] =3D regs[0]; + nor->bouncebuf[1] =3D regs[1]; + + ret =3D spi_nor_write_sr(nor, nor->bouncebuf, 2); + if (ret) + return ret; + + ret =3D spi_nor_read_sr(nor, &nor->bouncebuf[0]); + if (ret) + return ret; + + if (written_regs[0] !=3D nor->bouncebuf[0]) { + dev_dbg(nor->dev, "SR: Read back test failed\n"); + return -EIO; + } + + if (nor->flags & SNOR_F_NO_READ_CR) + return 0; + + ret =3D spi_nor_read_cr(nor, &nor->bouncebuf[1]); + if (ret) + return ret; + + if (written_regs[1] !=3D nor->bouncebuf[1]) { + dev_dbg(nor->dev, "CR: read back test failed\n"); + return -EIO; + } + + return 0; +} + /** * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure t= hat * the byte written match the received value without affecting other bits = in the @@ -993,6 +1041,23 @@ int spi_nor_write_sr_and_check(struct spi_nor *nor, u= 8 sr1) return spi_nor_write_sr1_and_check(nor, sr1); } =20 +/** + * spi_nor_write_sr_cr_and_check() - Write the Status Register 1 and ensur= e that + * the byte written match the received value. Same for the Control Registe= r if + * available. + * @nor: pointer to a 'struct spi_nor'. + * @regs: byte array to be written to the registers. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs) +{ + if (nor->flags & SNOR_F_HAS_16BIT_SR) + return spi_nor_write_16bit_sr_cr_and_check(nor, regs); + + return spi_nor_write_sr1_and_check(nor, regs[0]); +} + /** * spi_nor_write_sr2() - Write the Status Register 2 using the * SPINOR_OP_WRSR2 (3eh) command. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 16b382d4f04f..3dc9ba3bc6da 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -632,6 +632,7 @@ int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len); int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1); int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr); +int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs); =20 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf); --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC7F93A6B6E for ; Tue, 17 Mar 2026 10:24:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743075; cv=none; b=DIdDDqe1+gOC7OINI34SRGN5upn4oJMgVDIWrofu2IjAvK9ENDBhVKrqIeNuuHI5qTqgv8ddH+YUZm621m+9SFI/x+mupptmf0reBZIW8OHdKIgRAvmmMsOh73XVFegvtniVIFVmWEMeaTiiAdO86+/M/LFxcT7h8isvGp5P9Rw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743075; c=relaxed/simple; bh=GHZmXM5aeYs2tOJlVhdumoaqbQGSKeO1/pZkzO0/kP8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZynDqWBPLfpR06seIDjYCgEX6m9ARmzIi4k6ZxBL0yrywC66pitqKm6Lfz1ys8b8qYcARsAuvLEMAG0IX6Usxw6jUwnw2r1glRN7Q9qYvqPJE0j3E7WcqAno5igv1ItTDaWYjGUq2yNSseX0+zxbBjDnA41cddljbEzS6ukZZwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=vo3ID7tL; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="vo3ID7tL" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 6941DC55055; Tue, 17 Mar 2026 10:24:56 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6E7D95FC9A; Tue, 17 Mar 2026 10:24:32 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 550AD10450458; Tue, 17 Mar 2026 11:24:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743071; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Ec0kbPx+edwoqApwKlNsfKYC2JUdHu2CV9kwwUFOJtw=; b=vo3ID7tL65bSVLiFSYDKEvzPrXAoJKJjNr1TWvmprROuC5UJz9uGirrLnMI7lXSyU+m4/i vY3GCXYKvH49YF85+BVBaXI2AxEn0tuexxwUuiywySv5/MHfJel4X0+4+Jq/ZpkrM9b4pF LbwNuGC3xTizmoiVfSWuQK0E0uiO4/4QenN1VqDvqVf1rEFAvFMJV7UL/i10LPCL+EivZY w454Ah5DUgdn+bScI8N/XSzSS6FTU68+wPpSeio2oV3/COjZJcYc1+xYt2+MekhWm4e8Fa MDGP/K2RJhAPDl6WZzadEXm9bJSoqY+46mSrYbF5KKJNeVJNR4Zv+HvIa6PE2g== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:14 +0100 Subject: [PATCH v3 11/27] mtd: spi-nor: swp: Rename a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-11-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 "mask" is not very descriptive when we already manipulate two masks, and soon will manipulate three. Rename it "bp_mask" to align with the existing "tb_mask" and soon "cmp_mask". Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index af6e577d9b42..66f85826ba0d 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -57,9 +57,9 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, const u8 *sr, loff_ u64 *len) { u64 min_prot_len; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 bp, val =3D sr[0] & mask; + u8 bp, val =3D sr[0] & bp_mask; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -160,7 +160,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1] =3D {}, status_new[1] =3D {}; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; loff_t lock_len; @@ -199,7 +199,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) lock_len =3D ofs + len; =20 if (lock_len =3D=3D nor->params->size) { - val =3D mask; + val =3D bp_mask; } else { min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; @@ -208,15 +208,15 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) val =3D (val & ~SR_BP3) | SR_BP3_BIT6; =20 - if (val & ~mask) + if (val & ~bp_mask) return -EINVAL; =20 /* Don't "lock" with no region! */ - if (!(val & mask)) + if (!(val & bp_mask)) return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; =20 /* * Disallow further writes if WP# pin is neither left floating nor @@ -234,7 +234,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) return 0; =20 /* Only modify protection if it will not unlock other areas */ - if ((status_new[0] & mask) < (status_old[0] & mask)) + if ((status_new[0] & bp_mask) < (status_old[0] & bp_mask)) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); @@ -250,7 +250,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1], status_new[1]; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; loff_t lock_len; @@ -306,11 +306,11 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) val =3D (val & ~SR_BP3) | SR_BP3_BIT6; =20 /* Some power-of-two sizes may not be supported */ - if (val & ~mask) + if (val & ~bp_mask) return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; =20 /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) @@ -324,7 +324,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) return 0; =20 /* Only modify protection if it will not lock other areas */ - if ((status_new[0] & mask) > (status_old[0] & mask)) + if ((status_new[0] & bp_mask) > (status_old[0] & bp_mask)) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AE0D3A9620; Tue, 17 Mar 2026 10:24:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743076; cv=none; b=Jp/xqA0tj93XzQpEXXm7cC7bcPr81RJ+WKPbfwMRiMCHVyKKtxnmnEbf0rilD/MlV9U7/GfWrljKcIfZ1AcNMOalNWX2WZm5IDhUzr6dMH8HfgU8wFsL0FgamkKakyaeeH1h/ApcrZEflyxCQxJREWm8j2bbXfIBbL7I14enL5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743076; c=relaxed/simple; bh=wjIUXafk8VGGbnPY3Dsx9uPr5XXbqRZCmWlNeUX3WCo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cZ9stMIGUdU7HiY1H/OBPdY+KkrTlXswh0zSrvfHukRzmG6QTSFhjTg2CVpF/TajDMLTXOuT2ZqNiZC4PbNGsalGwwwET6YHMcRMy8tXDBiFAI0zDihi+W8CwCnt358xzG4WpQNULkqLpB1WipUG5zccekqD+l9AdaEwzr2qZZk= ARC-Authentication-Results: i=1; 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Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 66f85826ba0d..f068cb9c8f6d 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -60,6 +60,7 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, const u8 *sr, loff_ u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 bp, val =3D sr[0] & bp_mask; + bool tb =3D (nor->flags & SNOR_F_HAS_SR_TB) ? sr[0] & tb_mask : 0; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -79,7 +80,7 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, const u8 *sr, loff_ if (*len > nor->params->size) *len =3D nor->params->size; =20 - if (nor->flags & SNOR_F_HAS_SR_TB && sr[0] & tb_mask) + if (tb) *ofs =3D 0; else *ofs =3D nor->params->size - *len; --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E308C3A9D92 for ; Tue, 17 Mar 2026 10:24:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743078; cv=none; b=ktlJEYzG/H60NihsbWBeuf05F7Cql0oWswglNtZy8MjRQ2k44EZJgvrNB9SXt597GAs5+y2/8sp71bCYhQC/oEkfgBWvmJqFMyITI8dLOOjWkpjOEcdOsc/z05dDioVMR2I/T5LSXyMN6g8lPnIt0WogAQIQPXU8un53tigiZUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743078; c=relaxed/simple; bh=qZeCE0msR5ojlr1bTKuEzUtB7a//YcKLIUtu1EhJwhQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JIt7ynl+ZzksuaKI0I+0DFnqHOSYNUOAS8p7i2xJzRsxTASub4z+Oxyfkkm8QzWzgAlbNPxDITha8E6A0r51prbMBN7yJhh0VrXzzO5pomBtYEZxB1xJhXo9v8zndJPZFPRXMp/abYLmO/xHs8syJok/Mw5E6STXqzoArGMGPp8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=sgN+RKmf; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="sgN+RKmf" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 9806DC5505A; Tue, 17 Mar 2026 10:24:59 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 9C2CF5FC9A; Tue, 17 Mar 2026 10:24:35 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8ACCC1045045A; Tue, 17 Mar 2026 11:24:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743074; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=D52TLeXksnZZDY4Xj5CPfUClEwfCTxQc7ZJZFYNQVjg=; b=sgN+RKmfWWKJMb3rQ1EM9SHH3Ab/OV1K3ZngZOJGFAdEfLJMiSRhEFkz2Oz+xKbdL+o057 OtPh/YRfJQ0GgKEecOG2A8MC/FB1DDYxnsybHXLIxIkW8SBWJcMf2uMLH/FnnteR4oYmiv kL5vmJbCUdZlI7F6osc4EqmWgvpjJdqhNhsa7UGipg3vif3feHMkp3pH2Mv+uLS5X4RjC5 z4onW7YerAGgWFG2//b7jOhnuzK0w/86vOvWPonUi7Vti9/2ZW1kOusTanXRhVJFhTTg9S C9Pj84ezuDCDYvtgfMH8PqttiYSkttUGavz3k6FY0pGEGwoVjkZp51c6cjcVRQ== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:16 +0100 Subject: [PATCH v3 13/27] mtd: spi-nor: swp: Create helpers for building the SR register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-13-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The status register contains 3 or 4 BP (Block Protect) bits, 0 or 1 TB (Top/Bottom) bit, soon 0 or 1 CMP (Complement) bit. The last BP bit and the TB bit locations change between vendors. The whole logic of buildling the content of the status register based on some input conditions is used two times and soon will be used 4 times. Create dedicated helpers for these steps. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 83 +++++++++++++++++++++++++++++--------------= ---- 1 file changed, 51 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index f068cb9c8f6d..e2e423b20989 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -123,6 +123,43 @@ static bool spi_nor_is_unlocked_sr(struct spi_nor *nor= , loff_t ofs, u64 len, return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false); } =20 +static int spi_nor_sr_set_bp_mask(struct spi_nor *nor, u8 *sr, u8 pow) +{ + u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 val =3D pow << SR_BP_SHIFT; + + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) + val =3D (val & ~SR_BP3) | SR_BP3_BIT6; + + if (val & ~mask) + return -EINVAL; + + sr[0] =3D val; + + return 0; +} + +static int spi_nor_build_sr(struct spi_nor *nor, const u8 *old_sr, u8 *new= _sr, + u8 pow, bool use_top) +{ + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); + u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); + int ret; + + new_sr[0] =3D old_sr[0] & ~bp_mask & ~tb_mask; + + /* Build BP field */ + ret =3D spi_nor_sr_set_bp_mask(nor, &new_sr[0], pow); + if (ret) + return ret; + + /* Build TB field */ + if (!use_top) + new_sr[0] |=3D tb_mask; + + return 0; +} + /* * Lock a region of the flash. Compatible with ST Micro and similar flash. * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status @@ -162,11 +199,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) int ret; u8 status_old[1] =3D {}, status_new[1] =3D {}; u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); - u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 pow, val; loff_t lock_len; bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; bool use_top; + u8 pow; =20 ret =3D spi_nor_read_sr(nor, nor->bouncebuf); if (ret) @@ -200,24 +236,19 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) lock_len =3D ofs + len; =20 if (lock_len =3D=3D nor->params->size) { - val =3D bp_mask; + pow =3D (nor->flags & SNOR_F_HAS_4BIT_BP) ? GENMASK(3, 0) : GENMASK(2, 0= ); } else { min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; - val =3D pow << SR_BP_SHIFT; - - if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) - val =3D (val & ~SR_BP3) | SR_BP3_BIT6; - - if (val & ~bp_mask) - return -EINVAL; - - /* Don't "lock" with no region! */ - if (!(val & bp_mask)) - return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; + ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); + if (ret) + return ret; + + /* Don't "lock" with no region! */ + if (!(status_new[0] & bp_mask)) + return -EINVAL; =20 /* * Disallow further writes if WP# pin is neither left floating nor @@ -227,9 +258,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) if (!(nor->flags & SNOR_F_NO_WP)) status_new[0] |=3D SR_SRWD; =20 - if (!use_top) - status_new[0] |=3D tb_mask; - /* Don't bother if they're the same */ if (status_new[0] =3D=3D status_old[0]) return 0; @@ -252,11 +280,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) int ret; u8 status_old[1], status_new[1]; u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); - u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 pow, val; loff_t lock_len; bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; bool use_top; + u8 pow; =20 ret =3D spi_nor_read_sr(nor, nor->bouncebuf); if (ret) @@ -297,29 +324,21 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) lock_len =3D ofs; =20 if (lock_len =3D=3D 0) { - val =3D 0; /* fully unlocked */ + pow =3D 0; /* fully unlocked */ } else { min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; - val =3D pow << SR_BP_SHIFT; =20 - if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) - val =3D (val & ~SR_BP3) | SR_BP3_BIT6; - - /* Some power-of-two sizes may not be supported */ - if (val & ~bp_mask) - return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; + ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); + if (ret) + return ret; =20 /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) status_new[0] &=3D ~SR_SRWD; =20 - if (!use_top) - status_new[0] |=3D tb_mask; - /* Don't bother if they're the same */ if (status_new[0] =3D=3D status_old[0]) return 0; --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF9BC3AA1A8 for ; Tue, 17 Mar 2026 10:24:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743080; cv=none; b=e8CEjIqvN2XD+Fsrc+WmjU3BnReqTjA+WmymD7GyAyT6KmdG//x35RRrPmRxANEbz3oifoB1IQoJQNDbQE6B2zdyDGKYieRUmL3K9KLrcqRf34UM9oLDZO0IWbv2iwhKvfaAOj7uMVnC9Z8DhuOTYgRzPnqMl3ursiMLJ0eI5+U= ARC-Message-Signature: i=1; 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Tue, 17 Mar 2026 10:24:37 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 4E65F5FC9A; Tue, 17 Mar 2026 10:24:37 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2C97A1045045C; Tue, 17 Mar 2026 11:24:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743076; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=cErOh0nPQq4JaUTOOkelLy8W6h1AXJeJNMbiy0SldGw=; b=xtA3mxHCOLUNsy2AtBIeiAq4hxQrJdW2TrDwozuJ1tvcqsQs9za7nGFvFmbVj6b17+Df7c CCfAbPcQHKnbkhAXpZP+LlMWRoOgm7mI282KyfIfi9VrpYLXqkUbUSC1mtL1e1i9NFh1eA cNBr0Cm0n+gvKKFEJD8YpT1MPZENDIslPyyYUJiWMzecFdijH1SWICUJ5dUs+xZKR7MDdL 5Ve/vB0EfaAn8ksGbRlC5j3jEVaCcMQc7jfB9F2nHmyv0uyZarDhzWtb0eXT7IuYjFMQBu vU1uGn0FHzxiMCTDrHNjqkbtOolSc/Bd5qUcLnJe0ki1bFFSQA3NZtWXSjZ84Q== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:17 +0100 Subject: [PATCH v3 14/27] mtd: spi-nor: swp: Simplify checking the locked/unlocked range Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-14-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In both the locking/unlocking steps, at the end we verify whether we do not lock/unlock more than requested (in which case an error must be returned). While being possible to do that with very simple mask comparisons, it does not scale when adding extra locking features such as the CMP possibility. In order to make these checks slightly easier to read and more future proof, use existing helpers to read the (future) status register, extract the covered range, and compare it with very usual algebric comparisons. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index e2e423b20989..c45a9ddd5788 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -198,7 +198,8 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1] =3D {}, status_new[1] =3D {}; - u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); + loff_t ofs_old, ofs_new; + u64 len_old, len_new; loff_t lock_len; bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; bool use_top; @@ -246,10 +247,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t= ofs, u64 len) if (ret) return ret; =20 - /* Don't "lock" with no region! */ - if (!(status_new[0] & bp_mask)) - return -EINVAL; - /* * Disallow further writes if WP# pin is neither left floating nor * wrongly tied to GND (that includes internal pull-downs). @@ -262,8 +259,16 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t= ofs, u64 len) if (status_new[0] =3D=3D status_old[0]) return 0; =20 + spi_nor_get_locked_range_sr(nor, status_old, &ofs_old, &len_old); + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + + /* Don't "lock" with no region! */ + if (!len_new) + return -EINVAL; + /* Only modify protection if it will not unlock other areas */ - if ((status_new[0] & bp_mask) < (status_old[0] & bp_mask)) + if (len_old && + (ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old))) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); @@ -279,7 +284,8 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1], status_new[1]; - u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); + loff_t ofs_old, ofs_new; + u64 len_old, len_new; loff_t lock_len; bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; bool use_top; @@ -344,7 +350,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff= _t ofs, u64 len) return 0; =20 /* Only modify protection if it will not lock other areas */ - if ((status_new[0] & bp_mask) > (status_old[0] & bp_mask)) + spi_nor_get_locked_range_sr(nor, status_old, &ofs_old, &len_old); + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + if (len_old && len_new && + (ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new))) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 818073A5424 for ; Tue, 17 Mar 2026 10:24:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743081; cv=none; b=FMKxXRPepsQnXoHbcl9XuRn6Y4Pu4CYwGD8EFhYM0r/b1rHFuAPqlBxroURb7ZetEB4wv/wpRfkVizjNPuNLpvyD/jVHPtKornsLA6klbwaWiQIXBlFeVxpB3yveRxYT1ywucaVgQ/gfJL5sbTRDs/qpmdhipzl/ARTSMn8nG44= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-15-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 As a final preparation step for the introduction of CMP support, make a few more cosmetic changes to simplify the reading of the diff when adding the CMP feature. In particular, define "min_prot_len" earlier as it will be reused and move the definition of the "ret" variable at the end of the stack just because it looks better. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index c45a9ddd5788..c3dbc8832025 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -195,14 +195,14 @@ static int spi_nor_build_sr(struct spi_nor *nor, cons= t u8 *old_sr, u8 *new_sr, */ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len) { - u64 min_prot_len; - int ret; + u64 min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); u8 status_old[1] =3D {}, status_new[1] =3D {}; loff_t ofs_old, ofs_new; u64 len_old, len_new; loff_t lock_len; bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; bool use_top; + int ret; u8 pow; =20 ret =3D spi_nor_read_sr(nor, nor->bouncebuf); @@ -236,12 +236,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) else lock_len =3D ofs + len; =20 - if (lock_len =3D=3D nor->params->size) { + if (lock_len =3D=3D nor->params->size) pow =3D (nor->flags & SNOR_F_HAS_4BIT_BP) ? GENMASK(3, 0) : GENMASK(2, 0= ); - } else { - min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); + else pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; - } =20 ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); if (ret) @@ -281,7 +279,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) */ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { - u64 min_prot_len; + u64 min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); int ret; u8 status_old[1], status_new[1]; loff_t ofs_old, ofs_new; @@ -329,14 +327,11 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) else lock_len =3D ofs; =20 - if (lock_len =3D=3D 0) { + if (lock_len =3D=3D 0) pow =3D 0; /* fully unlocked */ - } else { - min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); + else pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; =20 - } - ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); if (ret) return ret; --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A25A3ACA4E for ; Tue, 17 Mar 2026 10:24:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743083; cv=none; b=hurft6vfRRHzLLGKLTxSFRhQVq/WJZeuwlTQSomPpCvqmS+wgBLZdrMHfG6eebLEB8QyaEAupHmlvP3cjUs6TdrQczkXoDVTQopsT4XI9Wku+dHa06EAX8pFaA9u3Gvoh5/IvyxRi9Zt3QeWbsyHcSHb0EpylqU87vQAI+6Ottc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743083; c=relaxed/simple; bh=zjHHOoL3gtov1X9RRzsBam632I4T1SP5JS4Jbx4DF0k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s2TTiF1Em0TFYhHBxY6LGe6hlvzdnC/CTQHBaHlWC9MSn2scn8jm40g0vQeWXW6Zm7/z/AfZWDksYK6EYtxTmjok9h9pK2f/0HF0iQobKpBJiDiCpo6UtGYSr+NkNGjvx8e0BRPyHNbcx8TtoZKdBHzmjI6qL+wwdgogURezVh8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=kLzcjMjz; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="kLzcjMjz" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id F25CF1A2D73; Tue, 17 Mar 2026 10:24:40 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C96565FC9A; Tue, 17 Mar 2026 10:24:40 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 957BB1045045F; Tue, 17 Mar 2026 11:24:38 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743080; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=0d4fr+bJvxEOshjbMESAzB2lu/MMRIqXAZ81vdf7/Lo=; b=kLzcjMjzGNoRm8c40hnT47T+4Qmsg2VbsxdBna8rTJY6bjZinQZCI3IIaMzHWetgEt1t1k ZXz/5zJL/oM+BDHiq63VpxtGqQrFI6n9smvyzKlvauOQqpitFlRF9YAgofgNJSRxqh17Ld VABlq2XxP8PUtTTDHXcBkh7ZuAjhkuPAIQ4Tb4HcH1vESPxYspYEyt2ZfBS43Jn1ySWllo AdkT9yZ1yDuirtjMRqbVHvbpPjwk80IgLD6nqso8LDW+9wuxtfsbd3sl76fjOZWTdCUgxj FORk6x2ohhbW+rUxMBeGvfcoGcbHmHe7qFh+bH9y0YOQ/cLJooTvH/KVxTjTQA== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:19 +0100 Subject: [PATCH v3 16/27] mtd: spi-nor: Create a local SR cache Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-16-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In order to be able to generate debugfs output without having to actually reach the flash, create a SPI NOR local cache of the status registers. What matters in our case are all the bits related to sector locking. As such, in order to make it clear that this cache is not intended to be used anywhere else, we zero the irrelevant bits. The cache is initialized once during the early init, and then maintained every time the write protection scheme is updated. Suggested-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/core.c | 6 +++++- drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/swp.c | 35 +++++++++++++++++++++++++++++++++-- include/linux/mtd/spi-nor.h | 2 ++ 4 files changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 1a31266fde1a..a2479942e350 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3328,8 +3328,12 @@ static int spi_nor_init(struct spi_nor *nor) */ if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) || (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) && - nor->flags & SNOR_F_SWP_IS_VOLATILE)) + nor->flags & SNOR_F_SWP_IS_VOLATILE)) { spi_nor_try_unlock_all(nor); + } else { + /* In the other cases, make sure the debugfs SR cache is up to date */ + spi_nor_cache_sr_lock_bits(nor, NULL); + } =20 if (nor->addr_nbytes =3D=3D 4 && nor->read_proto !=3D SNOR_PROTO_8_8_8_DTR && diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 3dc9ba3bc6da..091eb934abe4 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -674,6 +674,7 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor, =20 void spi_nor_init_default_locking_ops(struct spi_nor *nor); void spi_nor_try_unlock_all(struct spi_nor *nor); +void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr); void spi_nor_set_mtd_locking_ops(struct spi_nor *nor); void spi_nor_set_mtd_otp_ops(struct spi_nor *nor); =20 diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index c3dbc8832025..7a6c2b8ef921 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -160,6 +160,25 @@ static int spi_nor_build_sr(struct spi_nor *nor, const= u8 *old_sr, u8 *new_sr, return 0; } =20 +/* + * Keep a local cache containing all lock-related bits for debugfs use onl= y. + * This way, debugfs never needs to access the flash directly. + */ +void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr) +{ + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); + u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); + + if (!sr) { + if (spi_nor_read_sr(nor, nor->bouncebuf)) + return; + + sr =3D nor->bouncebuf; + } + + nor->dfs_sr_cache[0] =3D sr[0] & (bp_mask | tb_mask | SR_SRWD); +} + /* * Lock a region of the flash. Compatible with ST Micro and similar flash. * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status @@ -269,7 +288,13 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t= ofs, u64 len) (ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old))) return -EINVAL; =20 - return spi_nor_write_sr_and_check(nor, status_new[0]); + ret =3D spi_nor_write_sr_and_check(nor, status_new[0]); + if (ret) + return ret; + + spi_nor_cache_sr_lock_bits(nor, status_new); + + return 0; } =20 /* @@ -351,7 +376,13 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff= _t ofs, u64 len) (ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new))) return -EINVAL; =20 - return spi_nor_write_sr_and_check(nor, status_new[0]); + ret =3D spi_nor_write_sr_and_check(nor, status_new[0]); + if (ret) + return ret; + + spi_nor_cache_sr_lock_bits(nor, status_new); + + return 0; } =20 /* diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 90a0cf583512..9ad77f9e76c2 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -371,6 +371,7 @@ struct spi_nor_flash_parameter; * @reg_proto: the SPI protocol for read_reg/write_reg/erase operations * @sfdp: the SFDP data of the flash * @debugfs_root: pointer to the debugfs directory + * @dfs_sr_cache: Status Register cached value for debugfs use only * @controller_ops: SPI NOR controller driver specific operations. * @params: [FLASH-SPECIFIC] SPI NOR flash parameters and settings. * The structure includes legacy flash parameters and @@ -409,6 +410,7 @@ struct spi_nor { enum spi_nor_cmd_ext cmd_ext_type; struct sfdp *sfdp; struct dentry *debugfs_root; + u8 dfs_sr_cache[2]; =20 const struct spi_nor_controller_ops *controller_ops; =20 --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1ED923ACA61; Tue, 17 Mar 2026 10:24:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="EQIvQ3kF" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id F417C1A2E5D; Tue, 17 Mar 2026 10:24:42 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CA4F25FC9A; Tue, 17 Mar 2026 10:24:42 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 54F5C104503A6; Tue, 17 Mar 2026 11:24:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743081; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=5c8b+vAxWRpFsI1z94Obh+lca7KIQv9tXkU1B1za+2E=; b=EQIvQ3kFQ8pb3V6jc2K1P5Lui4fnCsGe4ytbe4BtlaZ4uzpvn3PA9he27dx1w3KG4fMC2V WTvBJyi6HmCsnuRoaSCml0BAYrq/qqhmjyusHsQI5vlFdfTbJxPiuRvAVSFHej4w+cyIN4 bTJW6KRIO6pvk75GhsrLaqNNnAghxxpBqDxwxu3ks5PogT3CFQQRuKZSxBCPUMOuTiOTZA l0XNkGFF/CzEd5WwlMJL0MPYDKyAsxyJFF5NtGjfJMYgbpHjWS3vhU3pZiHFQhHUPviVyF vKtzdoIoc8E+9uzj7i/B0LWVt60bhBg+ZehQoKXv0Ow/j20611y77qIcCTngAw== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:20 +0100 Subject: [PATCH v3 17/27] mtd: spi-nor: debugfs: Add locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-17-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The ioctl output may be counter intuitive in some cases. Asking for a "locked status" over a region that is only partially locked will return "unlocked" whereas in practice maybe the biggest part is actually locked. Knowing what is the real software locking state through debugfs would be very convenient for development/debugging purposes, hence this proposal for adding an extra block at the end of the file: a "locked sectors" array which lists every section, if it is locked or not, showing both the address ranges and the sizes in numbers of blocks. Here is an example of output, what is after the "sector map" is new. $ cat /sys/kernel/debug/spi-nor/spi0.0/params name (null) id ef a0 20 00 00 00 size 64.0 MiB write size 1 page size 256 address nbytes 4 flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_16BIT_SR | HAS_S= R_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP opcodes read 0xec dummy cycles 6 erase 0xdc program 0x34 8D extension none protocols read 1S-4S-4S write 1S-1S-4S register 1S-1S-1S erase commands 21 (4.00 KiB) [1] dc (64.0 KiB) [3] c7 (64.0 MiB) sector map region (in hex) | erase mask | overlaid ------------------+------------+--------- 00000000-03ffffff | [ 3] | no locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03ffffff | unlocked | 1024 Signed-off-by: Miquel Raynal --- Here are below more examples of output with various situations. The full output of the "params" content has been manually removed to only show what has been added and how it behaves. $ flash_lock -l /dev/mtd0 0x3f00000 16 $ cat /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03efffff | unlocked | 1008 03f00000-03ffffff | locked | 16 $ $ flash_lock -u /dev/mtd0 0x3f00000 8 $ cat /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03f7ffff | unlocked | 1016 03f80000-03ffffff | locked | 8 $ $ flash_lock -u /dev/mtd0 $ cat /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03ffffff | unlocked | 1024 $ $ flash_lock -l /dev/mtd0 $ cat /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03ffffff | locked | 1024 $ $ flash_lock -u /dev/mtd0 0x20000 1022 $ cat /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | locked | 2 00020000-03ffffff | unlocked | 1022 --- drivers/mtd/spi-nor/core.h | 4 ++++ drivers/mtd/spi-nor/debugfs.c | 22 ++++++++++++++++++++++ drivers/mtd/spi-nor/swp.c | 11 +++++++---- 3 files changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 091eb934abe4..99ed6c54b90f 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -707,6 +707,10 @@ static inline bool spi_nor_needs_sfdp(const struct spi= _nor *nor) return !nor->info->size; } =20 +u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor); +void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr, loff_t= *ofs, u64 *len); +bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len, const = u8 *sr); + #ifdef CONFIG_DEBUG_FS void spi_nor_debugfs_register(struct spi_nor *nor); void spi_nor_debugfs_shutdown(void); diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index d0191eb9f879..821fbc9587dc 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -77,10 +77,12 @@ static void spi_nor_print_flags(struct seq_file *s, uns= igned long flags, static int spi_nor_params_show(struct seq_file *s, void *data) { struct spi_nor *nor =3D s->private; + unsigned int min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); struct spi_nor_flash_parameter *params =3D nor->params; struct spi_nor_erase_map *erase_map =3D ¶ms->erase_map; struct spi_nor_erase_region *region =3D erase_map->regions; const struct flash_info *info =3D nor->info; + loff_t lock_start, lock_length; char buf[16], *str; unsigned int i; =20 @@ -159,6 +161,26 @@ static int spi_nor_params_show(struct seq_file *s, voi= d *data) region[i].overlaid ? "yes" : "no"); } =20 + seq_puts(s, "\nlocked sectors\n"); + seq_puts(s, " region (in hex) | status | #blocks\n"); + seq_puts(s, " ------------------+----------+--------\n"); + + spi_nor_get_locked_range_sr(nor, nor->dfs_sr_cache, &lock_start, &lock_le= ngth); + if (!lock_length || lock_length =3D=3D params->size) { + seq_printf(s, " %08llx-%08llx | %s | %llu\n", 0ULL, params->size - 1, + lock_length ? " locked" : "unlocked", params->size / min_prot_len); + } else if (!lock_start) { + seq_printf(s, " %08llx-%08llx | %s | %llu\n", 0ULL, lock_length - 1, + " locked", lock_length / min_prot_len); + seq_printf(s, " %08llx-%08llx | %s | %llu\n", lock_length, params->size = - 1, + "unlocked", (params->size - lock_length) / min_prot_len); + } else { + seq_printf(s, " %08llx-%08llx | %s | %llu\n", 0ULL, lock_start - 1, + "unlocked", lock_start / min_prot_len); + seq_printf(s, " %08llx-%08llx | %s | %llu\n", lock_start, params->size -= 1, + " locked", lock_length / min_prot_len); + } + return 0; } DEFINE_SHOW_ATTRIBUTE(spi_nor_params); diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 7a6c2b8ef921..8de8459e8e90 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -32,7 +32,7 @@ static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) return SR_TB_BIT5; } =20 -static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) +u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) { unsigned int bp_slots, bp_slots_needed; /* @@ -53,8 +53,8 @@ static u64 spi_nor_get_min_prot_length_sr(struct spi_nor = *nor) return sector_size; } =20 -static void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr,= loff_t *ofs, - u64 *len) +void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr, loff_t= *ofs, + u64 *len) { u64 min_prot_len; u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); @@ -112,7 +112,7 @@ static bool spi_nor_check_lock_status_sr(struct spi_nor= *nor, loff_t ofs, return (ofs >=3D lock_offs_max) || (offs_max <=3D lock_offs); } =20 -static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len,= const u8 *sr) +bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len, const = u8 *sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true); } @@ -410,6 +410,9 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, lo= ff_t ofs, u64 len) * -is_locked(): Checks if the region is *fully* locked, returns false oth= erwise. * This feeback may be misleading because users may get an "= unlocked" * status even though a subpart of the region is effectively= locked. + * + * If in doubt during development, check-out the debugfs output which trie= s to + * be more user friendly. */ static const struct spi_nor_locking_ops spi_nor_sr_locking_ops =3D { .lock =3D spi_nor_sr_lock, --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 612C33ACF1D; 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arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="GRzrNAs3" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 1D8221A2D73; Tue, 17 Mar 2026 10:24:45 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id E7BE25FC9A; Tue, 17 Mar 2026 10:24:44 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 24949104503AE; Tue, 17 Mar 2026 11:24:42 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743084; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=b9DhezCPS05cjlNZjYeTSMYdKUnSbfB8ozmwS4/HxAA=; b=GRzrNAs3smfmylcr+Oz7qxSI9lUobS0K0KB9yyvyr4cQkcBZG5zGEKxpfXFIc7bO/Z90ox TVQiQASAqLgBccRRibCQtR+6XbFda4QuOI+XXaxNcEdbRMFYw9x2yddSEG5dGyHb0pfl+Y l6vOqzphvtmxUTbvKGZKhWzbxDrJEey9ThKAD7xibMdE2kOtTvfjoNwWQnjouwNHr7RTbA u+Y25lPfWNrF1z6ymj3trjPYezgsWydn5u06WEGscz5QfT18K2HQ70Zrx/sDqwZTyOcl3+ LW8IEUxcl0FB59IkLs3SRaiUt+x8baBZHZdQJ5SQj3h1NoK0w5o0VDOlTNzyDA== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:21 +0100 Subject: [PATCH v3 18/27] mtd: spi-nor: debugfs: Add a locked sectors map Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-18-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In order to get a very clear view of the sectors being locked, besides the `params` output giving the ranges, we may want to see a proper map of the sectors and for each of them, their status. Depending on the use case, this map may be easier to parse by humans and gives a more acurate feeling of the situation. At least myself, for the few locking-related developments I recently went through, I found it very useful to get a clearer mental model of what was locked/unlocked. Here is an example of output: $ cat /sys/kernel/debug/spi-nor/spi0.0/locked-sectors-map Locked sectors map (x: locked, .: unlocked, unit: 64kiB) 0x00000000 (# 0): ................ ................ ................ ..= .............. 0x00400000 (# 64): ................ ................ ................ ..= .............. 0x00800000 (# 128): ................ ................ ................ ..= .............. 0x00c00000 (# 192): ................ ................ ................ ..= .............. 0x01000000 (# 256): ................ ................ ................ ..= .............. 0x01400000 (# 320): ................ ................ ................ ..= .............. 0x01800000 (# 384): ................ ................ ................ ..= .............. 0x01c00000 (# 448): ................ ................ ................ ..= .............. 0x02000000 (# 512): ................ ................ ................ ..= .............. 0x02400000 (# 576): ................ ................ ................ ..= .............. 0x02800000 (# 640): ................ ................ ................ ..= .............. 0x02c00000 (# 704): ................ ................ ................ ..= .............. 0x03000000 (# 768): ................ ................ ................ ..= .............. 0x03400000 (# 832): ................ ................ ................ ..= .............. 0x03800000 (# 896): ................ ................ ................ ..= .............. 0x03c00000 (# 960): ................ ................ ................ ..= ............xx The output is wrapped at 64 sectors, spaces every 16 sectors are improving the readability, every line starts by the first sector offset (hex) and number (decimal). Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/debugfs.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index 821fbc9587dc..c290bfe20f73 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -185,6 +185,40 @@ static int spi_nor_params_show(struct seq_file *s, voi= d *data) } DEFINE_SHOW_ATTRIBUTE(spi_nor_params); =20 +static int spi_nor_locked_sectors_map_show(struct seq_file *s, void *data) +{ + struct spi_nor *nor =3D s->private; + struct spi_nor_flash_parameter *params =3D nor->params; + unsigned int min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); + unsigned int offset =3D 0, sector =3D 0; + bool locked; + int i; + + seq_printf(s, "Locked sectors map (x: locked, .: unlocked, unit: %dkiB)\n= ", + min_prot_len / 1024); + while (offset < params->size) { + seq_printf(s, " 0x%08x (#%5d): ", offset, sector); + for (i =3D 0; i < 64 && offset < params->size; i++) { + locked =3D spi_nor_is_locked_sr(nor, offset, min_prot_len, + nor->dfs_sr_cache); + if (locked) + seq_puts(s, "x"); + else + seq_puts(s, "."); + + if (((i + 1) % 16) =3D=3D 0) + seq_puts(s, " "); + + offset +=3D min_prot_len; + sector++; + } + seq_puts(s, "\n"); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(spi_nor_locked_sectors_map); + static void spi_nor_print_read_cmd(struct seq_file *s, u32 cap, struct spi_nor_read_command *cmd) { @@ -270,6 +304,7 @@ void spi_nor_debugfs_register(struct spi_nor *nor) debugfs_create_file("params", 0444, d, nor, &spi_nor_params_fops); debugfs_create_file("capabilities", 0444, d, nor, &spi_nor_capabilities_fops); + debugfs_create_file("locked-sectors-map", 0444, d, nor, &spi_nor_locked_s= ectors_map_fops); } =20 void spi_nor_debugfs_shutdown(void) --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35A4C3AE18D for ; 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bh=hhd+i0LUsTLSToudA1/3v4V3xTFwJTwzl9JTAHOOnfs=; b=YGaLsNL5NIap9iJ1S0r4MDPPQyM4yW3tvARWtSPoLGp7oBcSOQHGKEdjs8dBc8NT7sg9Td jHT1eGTci41sGihzut70/oo+gvNhCs7KKXfuBtxnkPdgr0jD910EU+O0WqkWbMUocXbPfv ury0q8crVqgyO9tjDzYoEAgMYDFnjCfFhGvlwfE9YjD0Q3xyd3WjVgc15qmmnjxVuTAdq4 arQs3W8CKLVqKHRPkBjcm2yMrrFTS098b17VDReWK1anQW6LgCKTzd64CGv7AsdgzW4QSz iSA7B5s4dA1mLblunUtMpu0j5nqksF1DM3JtX0qDIFkyULbVG/7tIz+IChoK5w== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:22 +0100 Subject: [PATCH v3 19/27] mtd: spi-nor: Add steps for testing locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-19-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 As recently raised on the mailing list, it may be useful to propose a list of steps to go through in order to proove the devices have been described correctly, especially since all the block protection information is not stored in any kind of table and is instead filled manually by developpers. Use the debugfs output to ease the comparison between expectations and reality. Signed-off-by: Miquel Raynal --- Documentation/driver-api/mtd/spi-nor.rst | 128 +++++++++++++++++++++++++++= ++++ 1 file changed, 128 insertions(+) diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/drive= r-api/mtd/spi-nor.rst index 148fa4288760..4755eb75fe5e 100644 --- a/Documentation/driver-api/mtd/spi-nor.rst +++ b/Documentation/driver-api/mtd/spi-nor.rst @@ -203,3 +203,131 @@ section, after the ``---`` marker. mtd.writesize =3D 1 mtd.oobsize =3D 0 regions =3D 0 + +5) If your flash supports locking, please go through the following test + procedure to make sure it correctly behaves. The below example + expects the typical situation where eraseblocks and lock sectors have + the same size. In case you enabled MTD_SPI_NOR_USE_4K_SECTORS, you + must adapt `bs` accordingly. + + Warning: These tests may hard lock your device! Make sure: + - The device is not hard locked already (#WP strapped to low and + SR_SRWD bit set) + - If you have a WPn pin, you may want to set `no-wp` in your DT for + the time of the test, to only make use of software protection. + Otherwise, clearing the locking state depends on the WPn + signal and if it is tied to low, the flash will be permanently + locked. + + Test full chip locking and make sure expectations, the MEMISLOCKED + ioctl output, the debugfs output and experimental results are all + aligned:: + + root@1:~# alias show_sectors=3D'grep -A4 "locked sectors" /sys/kernel/= debug/spi-nor/spi0.0/params' + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -i /dev/mtd0 + Device: /dev/mtd0 + Start: 0 + Len: 0x4000000 + Lock status: unlocked + Return code: 0 + root@1:~# mtd_debug erase /dev/mtd0 0 2097152 + Erased 2097152 bytes from address 0x00000000 in flash + root@1:~# mtd_debug write /dev/mtd0 0 2097152 spi_test + Copied 2097152 bytes from spi_test to address 0x00000000 in flash + root@1:~# mtd_debug read /dev/mtd0 0 2097152 spi_read + Copied 2097152 bytes from address 0x00000000 in flash to spi_read + root@1:~# sha256sum spi* + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= read + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= test + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #blocks + ------------------+----------+-------- + 00000000-03ffffff | unlocked | 1024 + + root@1:~# flash_lock -l /dev/mtd0 + root@1:~# flash_lock -i /dev/mtd0 + Device: /dev/mtd0 + Start: 0 + Len: 0x4000000 + Lock status: locked + Return code: 1 + root@1:~# mtd_debug erase /dev/mtd0 0 2097152 + Erased 2097152 bytes from address 0x00000000 in flash + root@1:~# mtd_debug read /dev/mtd0 0 2097152 spi_read + Copied 2097152 bytes from address 0x00000000 in flash to spi_read + root@1:~# sha256sum spi* + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= read + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= test + root@1:~# dd if=3D/dev/urandom of=3D./spi_test2 bs=3D1M count=3D2 + 2+0 records in + 2+0 records out + root@1:~# mtd_debug write /dev/mtd0 0 2097152 spi_test2 + Copied 2097152 bytes from spi_test to address 0x00000000 in flash + root@1:~# mtd_debug read /dev/mtd0 0 2097152 spi_read2 + Copied 2097152 bytes from address 0x00000000 in flash to spi_read + root@1:~# sha256sum spi* + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= read + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= read2 + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= test + bea9334df51c620440f86751cba0799214a016329f1736f9456d40cf40efdc88 spi_= test2 + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #blocks + ------------------+----------+-------- + 00000000-03ffffff | locked | 1024 + + Once we trust the debugfs output we can use it to test various + situations. Check top locking/unlocking (end of the device):: + + root@1:~# bs=3D$(cat /sys/class/mtd/mtd0/erasesize) + root@1:~# size=3D$(cat /sys/class/mtd/mtd0/size) + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 $(($size - (2 * $bs))) 2 # last two + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #blocks + ------------------+----------+-------- + 00000000-03fdffff | unlocked | 1022 + 03fe0000-03ffffff | locked | 2 + root@1:~# flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # last one + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #blocks + ------------------+----------+-------- + 00000000-03feffff | unlocked | 1023 + 03ff0000-03ffffff | locked | 1 + + If the flash features 4 block protection bits (BP), we can protect + more than 4MB (typically 128 64kiB-blocks or more), with a finer + grain than locking the entire device:: + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 $(($size - (2**7 * $bs))) $((2**7)) + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #blocks + ------------------+----------+-------- + 00000000-037fffff | unlocked | 896 + 03800000-03ffffff | locked | 128 + + If the flash features a Top/Bottom (TB) bit, we can protect the + beginning of the flash:: + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 0 2 # first two + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #blocks + ------------------+----------+-------- + 00000000-0001ffff | locked | 2 + 00020000-03ffffff | unlocked | 1022 + root@1:~# flash_lock -u /dev/mtd0 $bs 1 # first one + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #blocks + ------------------+----------+-------- + 00000000-0000ffff | locked | 1 + 00010000-03ffffff | unlocked | 1023 --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFA403AE1AB for ; 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arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="SkqiC7+y" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 7E7EF1A2E74 for ; Tue, 17 Mar 2026 10:24:48 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 534025FC9A; Tue, 17 Mar 2026 10:24:48 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3199210450450; Tue, 17 Mar 2026 11:24:46 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743087; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=TG25gTpMKnFiUp+Sljlgx8mZQgxucUxLjGaX0Scu7NE=; b=SkqiC7+yTIGTo4kiWpqP998FqcN0SBhGSvVSUYSupXZNcXwvGXM1UoQcKp+FbIpGETudpH TwtMU3CfdiPdIrTt63w6a1rXS8GjWjT7pi3KxNfiF1cINdPRjLto/IaYUszWE9ZsiZGR6n Lr+50p135T+v0imIOOMx3RRPegj6P/9MPSNFPCd3tn1+bErAAW59xoP0KmCaBcGA66uElE 2GFRoOQnopBCEn2so6I/rDHHmQ+Q6kWgxfzhpZcRgzjdNRJPCw7h5mMZ0LZNM+znxYd2dd ojNhWljzugqgs59ktreWL0+Xvatr4MSs3cV4Ot1k6JsRXRCqoxpgL6jfMOIshA== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:23 +0100 Subject: [PATCH v3 20/27] mtd: spi-nor: swp: Add support for the complement feature Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-20-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The current locking implementation allows to select a power of two number of blocks, which is going to be the protected amount, as well as telling whether this is the data at the top (end of the device) or the bottom (beginning of the device). This means at most we can cover half of the device or the entire device, but nothing in between. The complement feature allows a much finer grain of configuration, by allowing to invert what is considered locked and unlocked. Add support for this feature. The only known position for the CMP bit is bit 6 of the configuration register. The locking and unlocking logics are kept unchanged if the CMP bit is unavailable. Otherwise, once the regular logic has been applied, we check if we already found an optimal configuration. If not, we try with the CMP bit set. If the coverage is closer to the request, we use it. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/core.c | 3 + drivers/mtd/spi-nor/core.h | 4 + drivers/mtd/spi-nor/debugfs.c | 1 + drivers/mtd/spi-nor/swp.c | 196 +++++++++++++++++++++++++++++++++++---= ---- include/linux/mtd/spi-nor.h | 1 + 5 files changed, 173 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index a2479942e350..e2bcf31d18ca 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2974,6 +2974,9 @@ static void spi_nor_init_flags(struct spi_nor *nor) nor->flags |=3D SNOR_F_HAS_SR_BP3_BIT6; } =20 + if (flags & SPI_NOR_HAS_CMP) + nor->flags |=3D SNOR_F_HAS_SR2_CMP_BIT6; + if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 && !nor->controller_ops) nor->flags |=3D SNOR_F_RWW; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 99ed6c54b90f..333786913ff1 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -141,6 +141,7 @@ enum spi_nor_option_flags { SNOR_F_ECC =3D BIT(15), SNOR_F_NO_WP =3D BIT(16), SNOR_F_SWAP16 =3D BIT(17), + SNOR_F_HAS_SR2_CMP_BIT6 =3D BIT(18), }; =20 struct spi_nor_read_command { @@ -483,6 +484,8 @@ struct spi_nor_id { * SPI_NOR_NO_ERASE: no erase command needed. * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * SPI_NOR_RWW: flash supports reads while write. + * SPI_NOR_HAS_CMP: flash SR2 has complement (CMP) protect bit. = Must + * be used with SPI_NOR_HAS_LOCK. * * @no_sfdp_flags: flags that indicate support that can be discovered via= SFDP. * Used when SFDP tables are not defined in the flash. Th= ese @@ -531,6 +534,7 @@ struct flash_info { #define SPI_NOR_NO_ERASE BIT(6) #define SPI_NOR_QUAD_PP BIT(8) #define SPI_NOR_RWW BIT(9) +#define SPI_NOR_HAS_CMP BIT(10) =20 u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index c290bfe20f73..fb6240dbbfc6 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -29,6 +29,7 @@ static const char *const snor_f_names[] =3D { SNOR_F_NAME(ECC), SNOR_F_NAME(NO_WP), SNOR_F_NAME(SWAP16), + SNOR_F_NAME(HAS_SR2_CMP_BIT6), }; #undef SNOR_F_NAME =20 diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 8de8459e8e90..ac405b1daf96 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -32,6 +32,15 @@ static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) return SR_TB_BIT5; } =20 +static u8 spi_nor_get_sr_cmp_mask(struct spi_nor *nor) +{ + if (!(nor->flags & SNOR_F_NO_READ_CR) && + nor->flags & SNOR_F_HAS_SR2_CMP_BIT6) + return SR2_CMP_BIT6; + else + return 0; +} + u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) { unsigned int bp_slots, bp_slots_needed; @@ -59,8 +68,10 @@ void spi_nor_get_locked_range_sr(struct spi_nor *nor, co= nst u8 *sr, loff_t *ofs, u64 min_prot_len; u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); + u8 cmp_mask =3D spi_nor_get_sr_tb_mask(nor); u8 bp, val =3D sr[0] & bp_mask; bool tb =3D (nor->flags & SNOR_F_HAS_SR_TB) ? sr[0] & tb_mask : 0; + bool cmp =3D sr[1] & cmp_mask; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -68,22 +79,37 @@ void spi_nor_get_locked_range_sr(struct spi_nor *nor, c= onst u8 *sr, loff_t *ofs, bp =3D val >> SR_BP_SHIFT; =20 if (!bp) { - /* No protection */ - *ofs =3D 0; - *len =3D 0; - return; + if (!cmp) { + /* No protection */ + *ofs =3D 0; + *len =3D 0; + return; + } else { + /* Full protection */ + *ofs =3D 0; + *len =3D nor->params->size; + } } =20 min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); *len =3D min_prot_len << (bp - 1); - if (*len > nor->params->size) *len =3D nor->params->size; =20 - if (tb) - *ofs =3D 0; - else - *ofs =3D nor->params->size - *len; + if (cmp) + *len =3D nor->params->size - *len; + + if (!cmp) { + if (tb) + *ofs =3D 0; + else + *ofs =3D nor->params->size - *len; + } else { + if (tb) + *ofs =3D nor->params->size - *len; + else + *ofs =3D 0; + } } =20 /* @@ -140,13 +166,15 @@ static int spi_nor_sr_set_bp_mask(struct spi_nor *nor= , u8 *sr, u8 pow) } =20 static int spi_nor_build_sr(struct spi_nor *nor, const u8 *old_sr, u8 *new= _sr, - u8 pow, bool use_top) + u8 pow, bool use_top, bool cmp) { u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); + u8 cmp_mask =3D spi_nor_get_sr_cmp_mask(nor); int ret; =20 new_sr[0] =3D old_sr[0] & ~bp_mask & ~tb_mask; + new_sr[1] =3D old_sr[1] & ~cmp_mask; =20 /* Build BP field */ ret =3D spi_nor_sr_set_bp_mask(nor, &new_sr[0], pow); @@ -154,9 +182,13 @@ static int spi_nor_build_sr(struct spi_nor *nor, const= u8 *old_sr, u8 *new_sr, return ret; =20 /* Build TB field */ - if (!use_top) + if ((!cmp && !use_top) || (cmp && use_top)) new_sr[0] |=3D tb_mask; =20 + /* Build CMP field */ + if (cmp) + new_sr[1] |=3D cmp_mask; + return 0; } =20 @@ -168,15 +200,22 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, = u8 *sr) { u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); + u8 cmp_mask =3D spi_nor_get_sr_cmp_mask(nor); =20 if (!sr) { if (spi_nor_read_sr(nor, nor->bouncebuf)) return; =20 + if (!(nor->flags & SNOR_F_NO_READ_CR)) { + if (spi_nor_read_cr(nor, nor->bouncebuf + 1)) + return; + } + sr =3D nor->bouncebuf; } =20 nor->dfs_sr_cache[0] =3D sr[0] & (bp_mask | tb_mask | SR_SRWD); + nor->dfs_sr_cache[1] =3D sr[1] & cmp_mask; } =20 /* @@ -185,10 +224,11 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, = u8 *sr) * register * (SR). Does not support these features found in newer SR bitfields: * - SEC: sector/block protect - only handle SEC=3D0 (block protect) - * - CMP: complement protect - only support CMP=3D0 (range is not comple= mented) * * Support for the following is provided conditionally for some flash: * - TB: top/bottom protect + * - CMP: complement protect (BP and TP describe the unlocked part, while + * the reminder is locked) * * Sample table portion for 8MB flash (Winbond w25q64fw): * @@ -215,11 +255,13 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, = u8 *sr) static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len) { u64 min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); - u8 status_old[1] =3D {}, status_new[1] =3D {}; - loff_t ofs_old, ofs_new; - u64 len_old, len_new; + u8 status_old[2] =3D {}, status_new[2] =3D {}, status_new_cmp[2] =3D {}; + u8 *best_status_new =3D status_new; + loff_t ofs_old, ofs_new, ofs_new_cmp; + u64 len_old, len_new, len_new_cmp; loff_t lock_len; - bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; + bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB, + can_be_cmp =3D spi_nor_get_sr_cmp_mask(nor); bool use_top; int ret; u8 pow; @@ -230,6 +272,14 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t= ofs, u64 len) =20 status_old[0] =3D nor->bouncebuf[0]; =20 + if (!(nor->flags & SNOR_F_NO_READ_CR)) { + ret =3D spi_nor_read_cr(nor, nor->bouncebuf + 1); + if (ret) + return ret; + + status_old[1] =3D nor->bouncebuf[1]; + } + /* If nothing in our range is unlocked, we don't need to do anything */ if (spi_nor_is_locked_sr(nor, ofs, len, status_old)) return 0; @@ -260,24 +310,56 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) else pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; =20 - ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); + ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top, false= ); if (ret) return ret; =20 + /* + * In case the region asked is not fully met, maybe we can try with the + * complement feature + */ + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + if (can_be_cmp && len_new !=3D lock_len) { + pow =3D ilog2(nor->params->size - lock_len) - ilog2(min_prot_len) + 1; + ret =3D spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top, = true); + if (ret) + return ret; + + /* + * ilog2() "floors" the result, which means in some cases we may have to + * manually reduce the scope when the complement feature is used. + * The uAPI is to never lock more than what is requested, but less is ac= cepted. + * Make sure we are not covering a too wide range, reduce it otherwise. + */ + spi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_= cmp); + if (len_new_cmp > lock_len) { + pow++; + ret =3D spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top,= true); + if (ret) + return ret; + } + + /* Pick the CMP configuration if we cover a closer range */ + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + spi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_= cmp); + if (len_new_cmp > len_new) + best_status_new =3D status_new_cmp; + } + /* * Disallow further writes if WP# pin is neither left floating nor * wrongly tied to GND (that includes internal pull-downs). * WP# pin hard strapped to GND can be a valid use case. */ if (!(nor->flags & SNOR_F_NO_WP)) - status_new[0] |=3D SR_SRWD; + best_status_new[0] |=3D SR_SRWD; =20 /* Don't bother if they're the same */ - if (status_new[0] =3D=3D status_old[0]) + if (best_status_new[0] =3D=3D status_old[0] && best_status_new[1] =3D=3D = status_old[1]) return 0; =20 spi_nor_get_locked_range_sr(nor, status_old, &ofs_old, &len_old); - spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + spi_nor_get_locked_range_sr(nor, best_status_new, &ofs_new, &len_new); =20 /* Don't "lock" with no region! */ if (!len_new) @@ -288,11 +370,11 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) (ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old))) return -EINVAL; =20 - ret =3D spi_nor_write_sr_and_check(nor, status_new[0]); + ret =3D spi_nor_write_sr_cr_and_check(nor, best_status_new); if (ret) return ret; =20 - spi_nor_cache_sr_lock_bits(nor, status_new); + spi_nor_cache_sr_lock_bits(nor, best_status_new); =20 return 0; } @@ -306,11 +388,13 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) { u64 min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); int ret; - u8 status_old[1], status_new[1]; - loff_t ofs_old, ofs_new; - u64 len_old, len_new; + u8 status_old[2], status_new[2], status_new_cmp[2]; + u8 *best_status_new =3D status_new; + loff_t ofs_old, ofs_new, ofs_new_cmp; + u64 len_old, len_new, len_new_cmp; loff_t lock_len; - bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; + bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB, + can_be_cmp =3D spi_nor_get_sr_cmp_mask(nor); bool use_top; u8 pow; =20 @@ -320,6 +404,14 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff= _t ofs, u64 len) =20 status_old[0] =3D nor->bouncebuf[0]; =20 + if (!(nor->flags & SNOR_F_NO_READ_CR)) { + ret =3D spi_nor_read_cr(nor, nor->bouncebuf + 1); + if (ret) + return ret; + + status_old[1] =3D nor->bouncebuf[1]; + } + /* If nothing in our range is locked, we don't need to do anything */ if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old)) return 0; @@ -357,30 +449,62 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) else pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; =20 - ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); + ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top, false= ); if (ret) return ret; =20 + /* + * In case the region asked is not fully met, maybe we can try with the + * complement feature + */ + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + if (can_be_cmp && len_new !=3D lock_len) { + pow =3D ilog2(nor->params->size - lock_len) - ilog2(min_prot_len) + 1; + ret =3D spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top, = true); + if (ret) + return ret; + + /* + * ilog2() "floors" the result, which means in some cases we may have to + * manually reduce the scope when the complement feature is used. + * The uAPI is to never unlock more than what is requested, but less is = accepted. + * Make sure we are not covering a too small range, increase it otherwis= e. + */ + spi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_= cmp); + if (len_new_cmp < lock_len) { + pow--; + ret =3D spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top,= true); + if (ret) + return ret; + } + + /* Pick the CMP configuration if we cover a closer range */ + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + spi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_= cmp); + if (len_new_cmp > len_new) + best_status_new =3D status_new_cmp; + } + /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) - status_new[0] &=3D ~SR_SRWD; + best_status_new[0] &=3D ~SR_SRWD; =20 /* Don't bother if they're the same */ - if (status_new[0] =3D=3D status_old[0]) + if (best_status_new[0] =3D=3D status_old[0] && best_status_new[1] =3D=3D = status_old[1]) return 0; =20 /* Only modify protection if it will not lock other areas */ spi_nor_get_locked_range_sr(nor, status_old, &ofs_old, &len_old); - spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + spi_nor_get_locked_range_sr(nor, best_status_new, &ofs_new, &len_new); if (len_old && len_new && (ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new))) return -EINVAL; =20 - ret =3D spi_nor_write_sr_and_check(nor, status_new[0]); + ret =3D spi_nor_write_sr_cr_and_check(nor, best_status_new); if (ret) return ret; =20 - spi_nor_cache_sr_lock_bits(nor, status_new); + spi_nor_cache_sr_lock_bits(nor, best_status_new); =20 return 0; } @@ -400,6 +524,14 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, l= off_t ofs, u64 len) if (ret) return ret; =20 + if (!(nor->flags & SNOR_F_NO_READ_CR)) { + ret =3D spi_nor_read_cr(nor, nor->bouncebuf + 1); + if (ret) + return ret; + } else { + nor->bouncebuf[1] =3D 0; + } + return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf); } =20 diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 9ad77f9e76c2..4b92494827b1 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -125,6 +125,7 @@ #define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */ #define SR2_LB2 BIT(4) /* Security Register Lock Bit 2 */ #define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */ +#define SR2_CMP_BIT6 BIT(6) #define SR2_QUAD_EN_BIT7 BIT(7) =20 /* Supported SPI protocols */ --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D0BB3AE6E8 for ; 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bh=7/ZShnKFDMohqlPS8rHFdEyfu+4BivJefw8T/oDlCwI=; b=gDEDqNMlUsolCHS1quv+HEvulyLizeJOQyEuOQB5JbEmouhDvxBkTouFH8pN1/ik3HGOj/ UGM5jghjoUKsHx/5dlrH9lVOXYQLjTY4cMXL/zFHloJVojteL01tcyAvXamOUKPdcdir1+ z2CjLdxtzm2VGpO/aBWLZvFVXAcCsFFkNxQbhfkBpo0OWJAJNv50RwbivNu0H5C0bGtXT6 SurouOuy4AobchJr+AaZmp6heXJENtlqfipytf4XsPQ8KwXHxy1wemPM+UiqppjtjgGrFF IOx/HukZKELS/bDRmhD3o0QdBFnMtjqNHDAqsX/mgsLZv9ykN1F3eO4aZWQxBA== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:24 +0100 Subject: [PATCH v3 21/27] mtd: spi-nor: Add steps for testing locking with CMP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-21-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Extend the test coverage by giving guidelines to verify the CMP bit acts according to our expectations. Signed-off-by: Miquel Raynal --- The instructions listed in this file target people adding support for new chips, however here are below extra steps that I also ran with the same W25H512NWxxAM chip. They are here to prove core correctness. $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 1008 $ show_sectors software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03efffff | locked | 1008 03f00000-03ffffff | unlocked | 16 $ flash_lock -l /dev/mtd0 0 1009 $ show_sectors # should not change software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03efffff | locked | 1008 03f00000-03ffffff | unlocked | 16 $ flash_lock -l /dev/mtd0 0 1015 $ show_sectors # should not change software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03efffff | locked | 1008 03f00000-03ffffff | unlocked | 16 $ flash_lock -l /dev/mtd0 0 1016 $ show_sectors # should cover more software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03f7ffff | locked | 1016 03f80000-03ffffff | unlocked | 8 $ flash_lock -u /dev/mtd0 $((1015 * $bs)) 1 $ show_sectors # should not change software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03f7ffff | locked | 1016 03f80000-03ffffff | unlocked | 8 $ flash_lock -u /dev/mtd0 $((1009 * $bs)) 7 $ show_sectors # should not change software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03f7ffff | locked | 1016 03f80000-03ffffff | unlocked | 8 $ flash_lock -u /dev/mtd0 $((1008 * $bs)) 8 $ show_sectors # range should reduce down to initial value software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03efffff | locked | 1008 03f00000-03ffffff | unlocked | 16 [Similar situations, on the other side of the device] $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $((16 * $bs)) 1008 $ show_sectors software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-000fffff | unlocked | 16 00100000-03ffffff | locked | 1008 $ flash_lock -l /dev/mtd0 $((15 * $bs)) 1009 $ show_sectors # should not change software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-000fffff | unlocked | 16 00100000-03ffffff | locked | 1008 $ flash_lock -l /dev/mtd0 $((9 * $bs)) 1015 $ show_sectors # should not change software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-000fffff | unlocked | 16 00100000-03ffffff | locked | 1008 $ flash_lock -l /dev/mtd0 $((8 * $bs)) 1016 $ show_sectors # should cover more software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0007ffff | unlocked | 8 00080000-03ffffff | locked | 1016 $ flash_lock -u /dev/mtd0 $((8 * $bs)) 1 $ show_sectors # should not change software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0007ffff | unlocked | 8 00080000-03ffffff | locked | 1016 $ flash_lock -u /dev/mtd0 $((8 * $bs)) 7 $ show_sectors # should not change software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0007ffff | unlocked | 8 00080000-03ffffff | locked | 1016 $ flash_lock -u /dev/mtd0 $((8 * $bs)) 8 $ show_sectors # range should reduce down to initial value software locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-000fffff | unlocked | 16 00100000-03ffffff | locked | 1008 --- Documentation/driver-api/mtd/spi-nor.rst | 36 ++++++++++++++++++++++++++++= ++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/drive= r-api/mtd/spi-nor.rst index 4755eb75fe5e..ec46bba8297a 100644 --- a/Documentation/driver-api/mtd/spi-nor.rst +++ b/Documentation/driver-api/mtd/spi-nor.rst @@ -331,3 +331,39 @@ section, after the ``---`` marker. ------------------+----------+-------- 00000000-0000ffff | locked | 1 00010000-03ffffff | unlocked | 1023 + + If the flash features a Complement (CMP) bit, we can protect with + more granularity above half of the capacity. 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bh=3UTw9aN/2yCK3EvGO8QBuf8zar07N1b/IrNqKvh1CgE=; b=2eDnJIsIIFtXSHEnNT0QdUMy/UeGSLx1odw1HIC8E3lP17E8zCWp40u53c4CdsSVYWkBKD ihz4qbr9oJWEGVLa07H+jOqmpl/qnLiCRGqyuQuHUJfFJGp9jq5BQvcnOOLtkjWvliKRpC cyClh4i1C9nyDPuzcQnuvy6ARasEWUUBzX9YpcZtGOM5TcjKHWU35TNxc7ccciQ+C5RWSd vbkbMIwH1fL2ba2vlry/b5GzNODZ/FXIenkEl9o7zIQ9N5U6Vc7gm6HH3E+LoI1fOPZF/Z b+d0ZXjVCC/QjjeafJGM7cx/25dyhYB6wNWP9nWFhTcT6xe36yLGREbou6l0sw== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:25 +0100 Subject: [PATCH v3 22/27] mtd: spi-nor: winbond: Add W25H512NWxxAM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-22-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Signed-off-by: Miquel Raynal --- Test run following the freshly written documentation: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-03ffffff | locked | 1023 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-03ffffff | locked | 1022 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03feffff | locked | 1023 03ff0000-03ffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03fdffff | locked | 1022 03fe0000-03ffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index fb855fe44733..7609dcc768f0 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -358,7 +358,8 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25H512NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x20), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, }, { /* W25H01NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x21), --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63A463B0AC8 for ; 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bh=MeVqIfBpy7cynYdckZP4tUPjyA2vBhyS34Ryk6tlKjQ=; b=iROP7Y4+mNa6qQzIhV7y9fE/sYYMZGI1eUB7v7BU/8QWOjcHu6ygr8YthnN2LqttgP6PXG Y6DRrsxDxQ0Wn05jfLZUIqzHA5VXPIgeXyGtNsA5DBF/8Kfx2jXA9Xg7pmC1EkaA8k/u3I bvlwlaix27qtsZQuAUegi38pDZZW/X/ygk3Dh9/lyyXOv2EvKqjVHWwnEQXYBCAfT8OrIV XgOh/BgTOZWpvcl3zZLsltSp2weIzskFsgJ8ZPsqx8SZ9Qwm4jZeYcKylwwfeBXcM/j5SF U5j8cdnchHqH85RPHyUL3FJNtJBh+AAfcAwpGmcppkLTCTT3hP3TjC0I5w/ObA== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:26 +0100 Subject: [PATCH v3 23/27] mtd: spi-nor: winbond: Add W25H01NWxxAM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-23-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Signed-off-by: Miquel Raynal --- Test run with W25H01NWxxAM: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-07ffffff | locked | 2047 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-07ffffff | locked | 2046 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-07feffff | locked | 2047 07ff0000-07ffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-07fdffff | locked | 2046 07fe0000-07ffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 7609dcc768f0..1b9b0e9598ef 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -363,7 +363,8 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25H01NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x21), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, }, { /* W25H02NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x22), --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D34853B2FD9; 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bh=xcYJgRzc5IqRAQH6jo52JPsF7X3RMUjzZg/GlVf9yBA=; b=zsTXqiQtHZcs9t5+zl3QvTEc+PAi40iPT9o2CqO2e12C1/oVzWUxgnFBFzrCbfNEbMjZbE f3KEI/c3g8KqJJpnhDFyPD5n2YNKoRerCEBFUUfEESWvCoHrWfuGmT9KouGBlJZdDL+Yd5 Uup43kKZxM7B0r6vTcops4yuKg/Diel3theJkyWaEE8YZKoinCwtVozVTQbfPmEzr/9DSE XDQ/7yeIifYIdLQdBWfxW39Uj4ViOQ8OYLMrfG56zgdU5tg54hL7/pZqW3SdRM+2PBvjHf bzpGlaFv8r6viVoyhQVK/DvwzPD13n/22Uih+gjY8TsEoSWI03UqgJNKjmjd5A== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:27 +0100 Subject: [PATCH v3 24/27] mtd: spi-nor: winbond: Add W25H02NWxxAM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-24-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Unfortunately, this chip also comes with an incorrect BFPT table, indicating the Control Register cannot be read back. This is wrong, reading back the register works and has no (observed) side effect. The datasheet clearly indicates supporting the 35h command and all bits from the CR are marked readable. QE and CMP bits are inside, and can be properly read back. Add a fixup for this, otherwise it would defeat the use of the CMP feature. Signed-off-by: Miquel Raynal --- Test run with W25H02NWxxAM: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-0fffffff | locked | 4095 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-0fffffff | locked | 4094 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffeffff | locked | 4095 0fff0000-0fffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffdffff | locked | 4094 0ffe0000-0fffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 1b9b0e9598ef..959fd4f46eb5 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -73,6 +73,26 @@ static const struct spi_nor_fixups w25q256_fixups =3D { .post_bfpt =3D w25q256_post_bfpt_fixups, }; =20 +static int +winbond_rdcr_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt) +{ + /* + * W25H02NW, unlike its W25H512NW nor W25H01NW cousins, improperly sets + * the QE BFPT configuration bits, indicating a non readable CR. This is + * both incorrect and impractical, as the chip features a CMP bit for its + * locking scheme that lays in the Control Register, and needs to be read. + */ + nor->flags &=3D ~SNOR_F_NO_READ_CR; + + return 0; +} + +static const struct spi_nor_fixups winbond_rdcr_fixup =3D { + .post_bfpt =3D winbond_rdcr_post_bfpt_fixup, +}; + /** * winbond_nor_select_die() - Set active die. * @nor: pointer to 'struct spi_nor'. @@ -368,7 +388,9 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25H02NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x22), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, + .fixups =3D &winbond_rdcr_fixup, }, }; =20 --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFBB63B3C16; Tue, 17 Mar 2026 10:24:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743099; cv=none; b=Z2bEP+2wzEp1L5iSswCgvbpH1Fzgv9aL7V+0gIA7hHo1pMinokE/TkChGUWLjo5fUrAE4J//ICzK4E6NFNuq9KNTjr6eYj6MpVYZskfAboyhNX0Py5r7sCWgdt/UiCPfe7JBbpRCm9T+24cEd/sKiN/okpix2ABKCcR6uypdtV8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743099; c=relaxed/simple; bh=Yl80iODVgcF61pX+l543yMYgtqmrTciYNzPD8N0Aq4o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SReufF1YA7dJHfJ9DSO3YKRSNtGeHG7xqCsCxT8wX9AEolF7ugODwtv3eE7I6HBZnipczE83mi1EWpuj+FA16K6HV+XnCQ4dLWajvkmJLOmp00slJRTM4NBHbIf+GA9ZT8gDqpjrOpuOZorTx0LjKiX1UkCSwwt6RmAwep6Y9jk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=mX4RsT2E; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mX4RsT2E" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 7EF314E42639; Tue, 17 Mar 2026 10:24:56 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 504145FC9A; Tue, 17 Mar 2026 10:24:56 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2091D10450458; Tue, 17 Mar 2026 11:24:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773743095; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=QsgGWiMFLmhabGIErgqJOAUgQ784tBeVIxY9n1SL9Sk=; b=mX4RsT2Este2pcERqhF5/iWOeYxlLlG6fnsls5zD5oGj7hrJDu5c1xWmDsqn+1XjagZVsa 8MiDLbe/8pPzN98f/lgT0RxLb5KofRmOE3y1eZtTHoeXtqF57Ltf4ty6Ur74+aQCp+k0c1 k6n1c+1N0EdpbltjyVzsTX2X2LYxjK+1FjVIu6i0r2i1+JLaKb0xnFAnMdXizuL2794v5H vvg2Oxa0MpktR8iaXYcKydEvMdeA9+DcBv0OsicecGuIEWsyoP8xoStc8W10MDNWX463T3 kxeIstU7h1mjdbzCPWJVb7+C8knvKDxBScidJKMw18mK2sYSy3OTRGAsEqYkzQ== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:28 +0100 Subject: [PATCH v3 25/27] mtd: spi-nor: winbond: Add W25H01NWxxIQ CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-25-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Unfortunately, this chip also comes with an incorrect BFPT table, indicating the Control Register cannot be read back. This is wrong, reading back the register works and has no (observed) side effect. The datasheet clearly indicates supporting the 35h command and all bits from the CR are marked readable. QE and CMP bits are inside, and can be properly read back. Add a fixup for this, otherwise it would defeat the use of the CMP feature. Signed-off-by: Miquel Raynal --- Test run with W25H01NWxxIQ: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-07ffffff | locked | 2047 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-07ffffff | locked | 2046 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-07feffff | locked | 2047 07ff0000-07ffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # alll but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-07fdffff | locked | 2046 07fe0000-07ffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 959fd4f46eb5..373c0af9daa2 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -366,7 +366,9 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25Q01NWxxIQ */ .id =3D SNOR_ID(0xef, 0x60, 0x21), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, + .fixups =3D &winbond_rdcr_fixup, }, { /* W25Q01NWxxIM */ .id =3D SNOR_ID(0xef, 0x80, 0x21), --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35CB63B4E85 for ; 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bh=aQ47DiGaPfkMamCb+o5HDFv/4Im96jTt1ueTmPftQyY=; b=dNo0JiN6h95Irl8OGWr2JvTVDPHHT3vHY9NvTjB1bueIR6JXF/Th70ScOAkpZi75mJwNn8 j/pD3u5gpnLKCvzgufRGJgR5mX8fSlXjQT4xZwG9Z1gdN2+W/DcqY1mKnd6eNzjDjVOCIU MqXYBx8Ikkp59FNRiGcJZWPc83Gz1oqzo+s4YShpC0+KdDz0fYFWKZUgUXi4rDaQs7+cCK +5y5SJh/3/hTnf1m1e7/3kyrk6iEjRJTXn7WnrYkgsYAhOKHzytxcwG58r/Y4ur/T5BbTp vbGgkKX87IZv4gsiMq1pePy/0DUlvz0GSIOemRXhKMaxcGRPHiNbMUBRt0aX9g== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:29 +0100 Subject: [PATCH v3 26/27] mtd: spi-nor: winbond: Add W25Q01NWxxIM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-26-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Signed-off-by: Miquel Raynal --- Test run with W25Q01NWxxIM: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-0fffffff | locked | 4095 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-0fffffff | locked | 4094 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffeffff | locked | 4095 0fff0000-0fffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffdffff | locked | 4094 0ffe0000-0fffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 373c0af9daa2..72053a4505f9 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -372,7 +372,8 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25Q01NWxxIM */ .id =3D SNOR_ID(0xef, 0x80, 0x21), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, }, { /* W25Q02NWxxIM */ .id =3D SNOR_ID(0xef, 0x80, 0x22), --=20 2.51.1 From nobody Mon Apr 6 23:37:43 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 077FC3A5E96 for ; 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bh=wXJyxTh9zUcQqoOPuD+RgDBVRNZuUe3FPkKCommQgVQ=; b=RLRMk7medhaQdMZDglFB2RUup/lNY0x+/HHwdND5mrW5cn9USg7Xl15Qg3PNUCt1UtUImZ Bqg9O8vPjeBqCenzWiQ6yggPwJBuYexaj09MF7uO6YaDIL5yW+qgOJHFGQSW9gHCsbk6rY mvuDKgqx3Z3efilAxN1bGdDHwnZ4YBxIpxCZZcTfdvaIlo5fHYgUQr+q2xHANTdM6sn8iN PcSaB1hDmi62xfz/Vi3pp1TXhldkR0mlU6PseRKuqBzMVrt03gUf2r81VnL9eYMdCY3dtQ +gIBjI9O6PsVHshQnPh2XKI1VNuzCZQ4+wer2cF3Sj5gODVrUQhYE5ARTY+VSQ== From: Miquel Raynal Date: Tue, 17 Mar 2026 11:24:30 +0100 Subject: [PATCH v3 27/27] mtd: spi-nor: winbond: Add W25Q02NWxxIM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-27-2ca9ea4e7b9b@bootlin.com> References: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> In-Reply-To: <20260317-winbond-v6-18-rc1-spi-nor-swp-v3-0-2ca9ea4e7b9b@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Tudor Ambarus , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Unfortunately, this chip also comes with an incorrect BFPT table, indicating the Control Register cannot be read back. This is wrong, reading back the register works and has no (observed) side effect. The datasheet clearly indicates supporting the 35h command and all bits from the CR are marked readable. QE and CMP bits are inside, and can be properly read back. Add a fixup for this, otherwise it would defeat the use of the CMP feature. Signed-off-by: Miquel Raynal --- Test run with W25Q02NWxxIM: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-0fffffff | locked | 4095 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-0fffffff | locked | 4094 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffeffff | locked | 4095 0fff0000-0fffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffdffff | locked | 4094 0ffe0000-0fffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 72053a4505f9..639d72f48769 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -377,7 +377,9 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25Q02NWxxIM */ .id =3D SNOR_ID(0xef, 0x80, 0x22), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, + .fixups =3D &winbond_rdcr_fixup, }, { /* W25H512NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x20), --=20 2.51.1