From nobody Tue Apr 7 01:05:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D032C301016; Tue, 17 Mar 2026 14:41:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773758512; cv=none; b=VpdFPgj1oC0oi5ozoWNzXFDxZOYJgzRH5CUChusDKIMqklibnJSmN46y7sqfm6HnyXSdJNez8Yw3mFSzyi39Iw8zQb+yHweJsNuz3WKjxZWCiwXz4DSKpG8O+FxB7adnSqidQ6Ypq7gOrtUd8gruNOpOuq06oT0VOIXvxQFA+38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773758512; c=relaxed/simple; bh=z3YXx0LCjH1mJwUKyn7MRhMVpiIDBfsko6DnOJNiokE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JPsq2obcYdwIRlG7NVh95qup03d6DyQEG/ZMGZTp9pIs9wQjNQmzjqKYuQ7EzQdApDNpwCjVruAzsVWvKGEcEAWaDyYJRqbnUwBE6gaLBrgMh4HtJrBqdlJ+koieEzt6MBHJt+H/c1a5LwR6hnJDZoZRB3o8H43UyAlYqMHfHPQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=O0/eh4n9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="O0/eh4n9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E691CC19424; Tue, 17 Mar 2026 14:41:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773758512; bh=z3YXx0LCjH1mJwUKyn7MRhMVpiIDBfsko6DnOJNiokE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=O0/eh4n9sW75qeM9vEldSMlfyqOJ1Vdc7hc2xfrxMTAnjRW6cYWDyZdRoUf9ntQiv ssQwgJmN9SzktHE5jWxFIvxxhJDhzwb/lAt4T/0erPOogrpOkdOc1g30P+cmygrNTS Pj08N031i6vjtcDI1ldjcWUki0Q3zUn3ZjS7XvxVoLjim2gr9Ds/RarJYU9KopzTaG 1d2/W0yDPEzLgMEvCgev2Q6HWZ1npVADdUw16hNcxL2XBQ6+pm8BsluZ2++Mic5pZA l2Z7sJiIjM9VWy8K+zL9uC5PdFgNXcPQfPEcApZ/s0JWk55/ZAJ+ro7bpwrKmgJCg+ SO8FByygcKbZw== From: Konrad Dybcio Date: Tue, 17 Mar 2026 15:41:19 +0100 Subject: [PATCH 6/6] arm64: dts: qcom: sm8750: Fix GIC_ITS range length Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-topic-its_range_fixup-v1-6-49be8076adb1@oss.qualcomm.com> References: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> In-Reply-To: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tengfei Fan , Dmitry Baryshkov , Jingyi Wang , Luca Weiss , Vinod Koul , Dmitry Baryshkov , Sai Prakash Ranjan , Neil Armstrong , Abel Vesa , Raviteja Laggyshetty , Melody Olvera , Taniya Das Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jishnu Prakash , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773758475; l=796; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=XbcnE3Jrn4Fw+kZkercW8VwU79ST4EZI5xCdtUdrmBY=; b=k/VS0KyXrZyj9GibgdD7zD+MVtRVwbzHKzjCOe8JPFKIb8HbxkeFCB1rGDpoBu5r1QQ+fvRDS ZulPXZlmLUAAIOsahEKYtVAhcJQIitueYlBIt/Euzi0RujYQ/ZFxUqC X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Currently, the GITS_SGIR register is cut off. Fix it up. Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index f56b1f889b85..04d47f1347ee 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -4658,7 +4658,7 @@ intc: interrupt-controller@16000000 { =20 gic_its: msi-controller@16040000 { compatible =3D "arm,gic-v3-its"; - reg =3D <0x0 0x16040000 0x0 0x20000>; + reg =3D <0x0 0x16040000 0x0 0x40000>; =20 msi-controller; #msi-cells =3D <1>; --=20 2.53.0